🎨 Cosmetic and comments

This commit is contained in:
Scott Lahteine
2023-12-16 23:22:38 -06:00
parent a3101a03ff
commit 39e42ebe6a
449 changed files with 3345 additions and 3655 deletions

View File

@@ -1,7 +1,9 @@
/**
* Marlin 3D Printer Firmware
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -119,7 +119,6 @@ void spiBegin() {
while (!TEST(SPSR, SPIF)) { /* Intentionally left empty */ }
}
/** begin spi transaction */
void spiBeginTransaction(uint32_t spiClock, uint8_t bitOrder, uint8_t dataMode) {
// Based on Arduino SPI library
@@ -175,7 +174,6 @@ void spiBegin() {
SPSR = clockDiv | 0x01;
}
#else // SOFTWARE_SPI || FORCE_SOFT_SPI
// ------------------------

View File

@@ -63,7 +63,6 @@
static volatile int8_t Channel[_Nbr_16timers]; // counter for the servo being pulsed for each timer (or -1 if refresh interval)
/************ static functions common to all instances ***********************/
static inline void handle_interrupts(const timer16_Sequence_t timer, volatile uint16_t* TCNTn, volatile uint16_t* OCRnA) {

View File

@@ -91,7 +91,6 @@ void endstop_ISR() { endstops.update(); }
#endif
// Install Pin change interrupt for a pin. Can be called multiple times.
void pciSetup(const int8_t pin) {
if (digitalPinHasPCICR(pin)) {

View File

@@ -682,7 +682,6 @@
#define PF7_PWM 0
#define PF7_DDR DDRF
/**
* Some of the pin mapping functions of the Teensduino extension to the Arduino IDE
* do not function the same as the other Arduino extensions.

View File

@@ -90,7 +90,6 @@ void PRINT_ARRAY_NAME(uint8_t x) {
#define GET_ARRAY_IS_DIGITAL(x) pgm_read_byte(&pin_array[x].is_digital)
#if defined(__AVR_ATmega1284P__) // 1284 IDE extensions set this to the number of
#undef NUM_DIGITAL_PINS // digital only pins while all other CPUs have it
#define NUM_DIGITAL_PINS 32 // set to digital only + digital/analog
@@ -164,7 +163,6 @@ static bool pwm_status(uint8_t pin) {
SERIAL_ECHO_SP(2);
} // pwm_status
const volatile uint8_t* const PWM_other[][3] PROGMEM = {
{ &TCCR0A, &TCCR0B, &TIMSK0 },
{ &TCCR1A, &TCCR1B, &TIMSK1 },
@@ -182,7 +180,6 @@ const volatile uint8_t* const PWM_other[][3] PROGMEM = {
#endif
};
const volatile uint8_t* const PWM_OCR[][3] PROGMEM = {
#ifdef TIMER0A
@@ -218,7 +215,6 @@ const volatile uint8_t* const PWM_OCR[][3] PROGMEM = {
#endif
};
#define TCCR_A(T) pgm_read_word(&PWM_other[T][0])
#define TCCR_B(T) pgm_read_word(&PWM_other[T][1])
#define TIMSK(T) pgm_read_word(&PWM_other[T][2])

View File

@@ -22,11 +22,10 @@
#pragma once
//
// some of the pin mapping functions of the Teensduino extension to the Arduino IDE
// do not function the same as the other Arduino extensions
// Some of the pin mapping functions of the Arduino IDE Teensduino extension
// function differently from other Arduino extensions.
//
#define TEENSYDUINO_IDE
//digitalPinToTimer(pin) function works like Arduino but Timers are not defined
@@ -48,8 +47,6 @@
#define PE 5
#define PF 6
#undef digitalPinToPort
const uint8_t PROGMEM digital_pin_to_port_PGM[] = {
PD, // 0 - PD0 - INT0 - PWM
PD, // 1 - PD1 - INT1 - PWM
@@ -101,7 +98,7 @@ const uint8_t PROGMEM digital_pin_to_port_PGM[] = {
PE, // 47 - PE3 (not defined in teensyduino)
};
#define digitalPinToPort(P) ( pgm_read_byte( digital_pin_to_port_PGM + (P) ) )
#define digitalPinToPort(P) pgm_read_byte(digital_pin_to_port_PGM[P])
// digitalPinToBitMask(pin) is OK

View File

@@ -231,7 +231,6 @@ const uint8_t PROGMEM digital_pin_to_bit_mask_PGM_plus_70[] = {
#define digitalPinToBitMask_plus_70(P) ( pgm_read_byte( digital_pin_to_bit_mask_PGM_plus_70 + (P) ) )
const uint8_t PROGMEM digital_pin_to_timer_PGM_plus_70[] = {
// TIMERS
// ------------------------

View File

@@ -1,7 +1,9 @@
/**
* Marlin 3D Printer Firmware
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -120,7 +120,6 @@ void u8g_spiSend_sw_AVR_mode_3(uint8_t val) {
U8G_ATOMIC_END();
}
#if ENABLED(FYSETC_MINI_12864)
#define SPISEND_SW_AVR u8g_spiSend_sw_AVR_mode_3
#else

View File

@@ -1,7 +1,9 @@
/**
* Marlin 3D Printer Firmware
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -1,9 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
* Copyright (c) 2015-2016 Nico Tonnhofer wurstnase.reprap@gmail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -474,7 +474,6 @@ void MarlinSerial<Cfg>::flushTX() {
}
}
// If not using the USB port as serial port
#if defined(SERIAL_PORT) && SERIAL_PORT >= 0
template class MarlinSerial< MarlinSerialCfg<SERIAL_PORT> >;

View File

@@ -73,7 +73,7 @@ void install_min_serial() {
}
#if DISABLED(DYNAMIC_VECTORTABLE)
extern "C" {
extern "C" {
__attribute__((naked)) void JumpHandler_ASM() {
__asm__ __volatile__ (
"b CommonHandler_ASM\n"
@@ -84,6 +84,12 @@ extern "C" {
void __attribute__((naked, alias("JumpHandler_ASM"))) UsageFault_Handler();
void __attribute__((naked, alias("JumpHandler_ASM"))) MemManage_Handler();
void __attribute__((naked, alias("JumpHandler_ASM"))) NMI_Handler();
}
void __attribute__((naked, alias("JumpHandler_ASM"))) HardFault_Handler();
void __attribute__((naked, alias("JumpHandler_ASM"))) BusFault_Handler();
void __attribute__((naked, alias("JumpHandler_ASM"))) UsageFault_Handler();
void __attribute__((naked, alias("JumpHandler_ASM"))) MemManage_Handler();
void __attribute__((naked, alias("JumpHandler_ASM"))) NMI_Handler();
}
#endif

View File

@@ -1,10 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
* Copyright (c) 2015-2016 Nico Tonnhofer wurstnase.reprap@gmail.com
* Copyright (c) 2016 Victor Perez victor_pv@hotmail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -1,10 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
* Copyright (c) 2015-2016 Nico Tonnhofer wurstnase.reprap@gmail.com
* Copyright (c) 2016 Victor Perez victor_pv@hotmail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -49,7 +49,6 @@ extern volatile uint32_t *SODR_A, *SODR_B, *CODR_A, *CODR_B;
#define PWM_MAP_INIT_ROW(IO,ZZ) { ZZ == 'A' ? SODR_A : SODR_B, ZZ == 'A' ? CODR_A : CODR_B, 1 << _PIN(IO) }
#define PWM_MAP_INIT { PWM_MAP_INIT_ROW(MOTOR_CURRENT_PWM_X_PIN, 'B'), \
PWM_MAP_INIT_ROW(MOTOR_CURRENT_PWM_Y_PIN, 'B'), \
PWM_MAP_INIT_ROW(MOTOR_CURRENT_PWM_Z_PIN, 'B'), \

View File

@@ -168,7 +168,6 @@ const G2_PinDescription G2_g_APinDescription[] = {
{ PIOB, PIO_PB21, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, NO_ADC, NO_ADC, NOT_ON_PWM, NOT_ON_TIMER }, // PIN 52
{ PIOB, PIO_PB14, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, NO_ADC, NO_ADC, NOT_ON_PWM, NOT_ON_TIMER }, // PIN 53
// 54 .. 65 - Analog pins
// ----------------------
{ PIOA, PIO_PA16X1_AD7, ID_PIOA, PIO_INPUT, PIO_DEFAULT, PIN_ATTR_ANALOG, ADC0, ADC7, NOT_ON_PWM, NOT_ON_TIMER }, // AD0

View File

@@ -1,9 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
* Copyright (c) 2015-2016 Nico Tonnhofer wurstnase.reprap@gmail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -1,8 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -142,7 +142,6 @@
*/
#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())
/**
* \brief Set aligned boundary.
*/
@@ -283,7 +282,6 @@ typedef double F64; //!< 64-bit floating-point number.
typedef uint32_t iram_size_t;
//! @}
/*! \name Status Types
*/
//! @{
@@ -291,7 +289,6 @@ typedef bool Status_bool_t; //!< Boolean status.
typedef U8 Status_t; //!< 8-bit-coded status.
//! @}
/*! \name Aliasing Aggregate Types
*/
//! @{
@@ -462,7 +459,6 @@ typedef struct
#endif
//! @}
#ifndef __ASSEMBLY__ // not for assembling.
//! \name Optimization Control
@@ -581,7 +577,6 @@ typedef struct
//! @}
/*! \name Zero-Bit Counting
*
* Under GCC, __builtin_clz and __builtin_ctz behave like macros when
@@ -692,7 +687,6 @@ typedef struct
//! @}
/*! \name Bit Reversing
*/
//! @{
@@ -732,7 +726,6 @@ typedef struct
//! @}
/*! \name Alignment
*/
//! @{
@@ -798,7 +791,6 @@ typedef struct
*/
#define Long_call(addr) ((*(void (*)(void))(addr))())
/*! \name MCU Endianism Handling
* ARM is MCU little endianism.
*/
@@ -868,7 +860,6 @@ typedef struct
#define CPU_TO_BE32(x) swap32(x)
//! @}
/*! \name Endianism Conversion
*
* The same considerations as for clz and ctz apply here but GCC's
@@ -955,7 +946,6 @@ typedef struct
//! @}
/*! \name Target Abstraction
*/
//! @{
@@ -997,7 +987,6 @@ typedef U8 Byte; //!< 8-bit unsigned integer.
#endif // #ifndef __ASSEMBLY__
#ifdef __ICCARM__
#define SHORTENUM __packed
#elif defined(__GNUC__)

View File

@@ -81,7 +81,6 @@
#define LUN_0_NAME "\"SD/MMC Card\""
//! @}
/*! \name Actions Associated with Memory Accesses
*
* Write here the action to associate with each memory access.
@@ -112,5 +111,4 @@
#define GLOBAL_WR_PROTECT false //!< Management of a global write protection.
//! @}
#endif // _CONF_ACCESS_H_

View File

@@ -96,5 +96,4 @@
// - UPLL frequency: 480MHz
// - USB clock: 480 / 1 = 480MHz
#endif /* CONF_CLOCK_H_INCLUDED */

View File

@@ -88,7 +88,6 @@
#endif
//@}
/**
* USB Device Callbacks definitions (Optional)
* @{
@@ -150,7 +149,6 @@
//@}
/**
* USB Interface Configuration
* @{
@@ -210,7 +208,6 @@
//@}
//@}
/**
* Configuration of MSC interface
* @{
@@ -245,7 +242,6 @@
//@}
/**
* Description of Composite Device
* @{

View File

@@ -68,7 +68,6 @@
#endif
#include "ctrl_access.h"
//_____ D E F I N I T I O N S ______________________________________________
#ifdef FREERTOS_USED
@@ -112,7 +111,6 @@ static xSemaphoreHandle ctrl_access_semphr = NULL;
#endif // FREERTOS_USED
#if MAX_LUN
/*! \brief Initializes an entry of the LUN descriptor table.
@@ -242,17 +240,14 @@ static const struct
#endif
#if GLOBAL_WR_PROTECT == true
bool g_wr_protect;
#endif
/*! \name Control Interface
*/
//! @{
#ifdef FREERTOS_USED
bool ctrl_access_init(void)
@@ -270,7 +265,6 @@ bool ctrl_access_init(void)
return true;
}
/*! \brief Locks accesses to LUNs.
*
* \return \c true if the access was successfully locked, else \c false.
@@ -288,7 +282,6 @@ static bool ctrl_access_lock(void)
#endif // FREERTOS_USED
U8 get_nb_lun(void)
{
#if MEM_USB == ENABLE
@@ -309,13 +302,11 @@ U8 get_nb_lun(void)
#endif
}
U8 get_cur_lun(void)
{
return LUN_ID_0;
}
Ctrl_status mem_test_unit_ready(U8 lun)
{
Ctrl_status status;
@@ -337,7 +328,6 @@ Ctrl_status mem_test_unit_ready(U8 lun)
return status;
}
Ctrl_status mem_read_capacity(U8 lun, U32 *u32_nb_sector)
{
Ctrl_status status;
@@ -359,7 +349,6 @@ Ctrl_status mem_read_capacity(U8 lun, U32 *u32_nb_sector)
return status;
}
U8 mem_sector_size(U8 lun)
{
U8 sector_size;
@@ -381,7 +370,6 @@ U8 mem_sector_size(U8 lun)
return sector_size;
}
bool mem_unload(U8 lun, bool unload)
{
bool unloaded;
@@ -433,7 +421,6 @@ bool mem_wr_protect(U8 lun)
return wr_protect;
}
bool mem_removal(U8 lun)
{
bool removal;
@@ -458,7 +445,6 @@ bool mem_removal(U8 lun)
return removal;
}
const char *mem_name(U8 lun)
{
#if MAX_LUN==0
@@ -475,17 +461,14 @@ const char *mem_name(U8 lun)
#endif
}
//! @}
#if ACCESS_USB == true
/*! \name MEM <-> USB Interface
*/
//! @{
Ctrl_status memory_2_usb(U8 lun, U32 addr, U16 nb_sector)
{
Ctrl_status status;
@@ -505,7 +488,6 @@ Ctrl_status memory_2_usb(U8 lun, U32 addr, U16 nb_sector)
return status;
}
Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector)
{
Ctrl_status status;
@@ -525,19 +507,16 @@ Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector)
return status;
}
//! @}
#endif // ACCESS_USB == true
#if ACCESS_MEM_TO_RAM == true
/*! \name MEM <-> RAM Interface
*/
//! @{
Ctrl_status memory_2_ram(U8 lun, U32 addr, void *ram)
{
Ctrl_status status;
@@ -564,7 +543,6 @@ Ctrl_status memory_2_ram(U8 lun, U32 addr, void *ram)
return status;
}
Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram)
{
Ctrl_status status;
@@ -591,19 +569,16 @@ Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram)
return status;
}
//! @}
#endif // ACCESS_MEM_TO_RAM == true
#if ACCESS_STREAM == true
/*! \name Streaming MEM <-> MEM Interface
*/
//! @{
#if ACCESS_MEM_TO_MEM == true
#include "fat.h"
@@ -625,21 +600,18 @@ Ctrl_status stream_mem_to_mem(U8 src_lun, U32 src_addr, U8 dest_lun, U32 dest_ad
#endif // ACCESS_MEM_TO_MEM == true
Ctrl_status stream_state(U8 id)
{
UNUSED(id);
return CTRL_GOOD;
}
U16 stream_stop(U8 id)
{
UNUSED(id);
return 0;
}
//! @}
#endif // ACCESS_STREAM

View File

@@ -56,7 +56,6 @@
* Support and FAQ: visit <a href="https://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _CTRL_ACCESS_H_
#define _CTRL_ACCESS_H_
@@ -89,7 +88,6 @@ typedef enum
CTRL_BUSY = FAIL + 2 //!< Memory not initialized or changed.
} Ctrl_status;
// FYI: Each Logical Unit Number (LUN) corresponds to a memory.
// Check LUN defines.
@@ -136,7 +134,6 @@ typedef enum
#define LUN_ID_USB (MAX_LUN) //!< First dynamic LUN (USB host mass storage).
//! @}
// Include LUN header files.
#if LUN_0 == ENABLE
#include LUN_0_INCLUDE
@@ -166,13 +163,11 @@ typedef enum
#include LUN_USB_INCLUDE
#endif
// Check the configuration of write protection in conf_access.h.
#ifndef GLOBAL_WR_PROTECT
#error GLOBAL_WR_PROTECT must be defined as true or false in conf_access.h
#endif
#if GLOBAL_WR_PROTECT == true
//! Write protect.
@@ -180,7 +175,6 @@ extern bool g_wr_protect;
#endif
/*! \name Control Interface
*/
//! @{
@@ -279,7 +273,6 @@ extern const char *mem_name(U8 lun);
//! @}
#if ACCESS_USB == true
/*! \name MEM <-> USB Interface
@@ -310,7 +303,6 @@ extern Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector);
#endif // ACCESS_USB == true
#if ACCESS_MEM_TO_RAM == true
/*! \name MEM <-> RAM Interface
@@ -341,7 +333,6 @@ extern Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram);
#endif // ACCESS_MEM_TO_RAM == true
#if ACCESS_STREAM == true
/*! \name Streaming MEM <-> MEM Interface

View File

@@ -108,31 +108,23 @@ struct genclk_config {
uint32_t ctrl;
};
static inline void genclk_config_defaults(struct genclk_config *p_cfg,
uint32_t ul_id)
{
static inline void genclk_config_defaults(struct genclk_config *p_cfg, uint32_t ul_id) {
ul_id = ul_id;
p_cfg->ctrl = 0;
}
static inline void genclk_config_read(struct genclk_config *p_cfg,
uint32_t ul_id)
{
static inline void genclk_config_read(struct genclk_config *p_cfg, uint32_t ul_id) {
p_cfg->ctrl = PMC->PMC_PCK[ul_id];
}
static inline void genclk_config_write(const struct genclk_config *p_cfg,
uint32_t ul_id)
{
static inline void genclk_config_write(const struct genclk_config *p_cfg, uint32_t ul_id) {
PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
}
//! \name Programmable Clock Source and Prescaler configuration
//@{
static inline void genclk_config_set_source(struct genclk_config *p_cfg,
enum genclk_source e_src)
{
static inline void genclk_config_set_source(struct genclk_config *p_cfg, enum genclk_source e_src) {
p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);
switch (e_src) {
@@ -164,29 +156,23 @@ static inline void genclk_config_set_source(struct genclk_config *p_cfg,
}
}
static inline void genclk_config_set_divider(struct genclk_config *p_cfg,
uint32_t e_divider)
{
static inline void genclk_config_set_divider(struct genclk_config *p_cfg, uint32_t e_divider) {
p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;
p_cfg->ctrl |= e_divider;
}
//@}
static inline void genclk_enable(const struct genclk_config *p_cfg,
uint32_t ul_id)
{
static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id) {
PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
pmc_enable_pck(ul_id);
}
static inline void genclk_disable(uint32_t ul_id)
{
static inline void genclk_disable(uint32_t ul_id) {
pmc_disable_pck(ul_id);
}
static inline void genclk_enable_source(enum genclk_source e_src)
{
static inline void genclk_enable_source(enum genclk_source e_src) {
switch (e_src) {
case GENCLK_PCK_SRC_SLCK_RC:
if (!osc_is_ready(OSC_SLCK_32K_RC)) {
@@ -244,17 +230,17 @@ static inline void genclk_enable_source(enum genclk_source e_src)
}
break;
#ifdef CONFIG_PLL0_SOURCE
#ifdef CONFIG_PLL0_SOURCE
case GENCLK_PCK_SRC_PLLACK:
pll_enable_config_defaults(0);
break;
#endif
#endif
#ifdef CONFIG_PLL1_SOURCE
#ifdef CONFIG_PLL1_SOURCE
case GENCLK_PCK_SRC_PLLBCK:
pll_enable_config_defaults(1);
break;
#endif
#endif
case GENCLK_PCK_SRC_MCK:
break;

View File

@@ -57,7 +57,6 @@
#include "preprocessor.h"
//! Maximal number of repetitions supported by MREPEAT.
#define MREPEAT_LIMIT 256

View File

@@ -62,28 +62,28 @@ extern "C" {
* should be defined by the board code, otherwise default value are used.
*/
#ifndef BOARD_FREQ_SLCK_XTAL
# warning The board slow clock xtal frequency has not been defined.
# define BOARD_FREQ_SLCK_XTAL (32768UL)
#warning The board slow clock xtal frequency has not been defined.
#define BOARD_FREQ_SLCK_XTAL (32768UL)
#endif
#ifndef BOARD_FREQ_SLCK_BYPASS
# warning The board slow clock bypass frequency has not been defined.
# define BOARD_FREQ_SLCK_BYPASS (32768UL)
#warning The board slow clock bypass frequency has not been defined.
#define BOARD_FREQ_SLCK_BYPASS (32768UL)
#endif
#ifndef BOARD_FREQ_MAINCK_XTAL
# warning The board main clock xtal frequency has not been defined.
# define BOARD_FREQ_MAINCK_XTAL (12000000UL)
#warning The board main clock xtal frequency has not been defined.
#define BOARD_FREQ_MAINCK_XTAL (12000000UL)
#endif
#ifndef BOARD_FREQ_MAINCK_BYPASS
# warning The board main clock bypass frequency has not been defined.
# define BOARD_FREQ_MAINCK_BYPASS (12000000UL)
#warning The board main clock bypass frequency has not been defined.
#define BOARD_FREQ_MAINCK_BYPASS (12000000UL)
#endif
#ifndef BOARD_OSC_STARTUP_US
# warning The board main clock xtal startup time has not been defined.
# define BOARD_OSC_STARTUP_US (15625UL)
#warning The board main clock xtal startup time has not been defined.
#define BOARD_OSC_STARTUP_US (15625UL)
#endif
/**
@@ -115,8 +115,7 @@ extern "C" {
#define OSC_MAINCK_BYPASS_HZ BOARD_FREQ_MAINCK_BYPASS //!< External bypass oscillator.
//@}
static inline void osc_enable(uint32_t ul_id)
{
static inline void osc_enable(uint32_t ul_id) {
switch (ul_id) {
case OSC_SLCK_32K_RC:
break;
@@ -129,7 +128,6 @@ static inline void osc_enable(uint32_t ul_id)
pmc_switch_sclk_to_32kxtal(PMC_OSC_BYPASS);
break;
case OSC_MAINCK_4M_RC:
pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);
break;
@@ -142,7 +140,6 @@ static inline void osc_enable(uint32_t ul_id)
pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);
break;
case OSC_MAINCK_XTAL:
pmc_switch_mainck_to_xtal(PMC_OSC_XTAL/*,
pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US,
@@ -157,8 +154,7 @@ static inline void osc_enable(uint32_t ul_id)
}
}
static inline void osc_disable(uint32_t ul_id)
{
static inline void osc_disable(uint32_t ul_id) {
switch (ul_id) {
case OSC_SLCK_32K_RC:
case OSC_SLCK_32K_XTAL:
@@ -181,8 +177,7 @@ static inline void osc_disable(uint32_t ul_id)
}
}
static inline bool osc_is_ready(uint32_t ul_id)
{
static inline bool osc_is_ready(uint32_t ul_id) {
switch (ul_id) {
case OSC_SLCK_32K_RC:
return 1;
@@ -202,8 +197,7 @@ static inline bool osc_is_ready(uint32_t ul_id)
return 0;
}
static inline uint32_t osc_get_rate(uint32_t ul_id)
{
static inline uint32_t osc_get_rate(uint32_t ul_id) {
switch (ul_id) {
case OSC_SLCK_32K_RC:
return OSC_SLCK_32K_RC_HZ;
@@ -241,8 +235,7 @@ static inline uint32_t osc_get_rate(uint32_t ul_id)
*
* \param id A number identifying the oscillator to wait for.
*/
static inline void osc_wait_ready(uint8_t id)
{
static inline void osc_wait_ready(uint8_t id) {
while (!osc_is_ready(id)) {
/* Do nothing */
}

View File

@@ -113,15 +113,15 @@ struct pll_config {
* is hidden in this implementation. Use mul as mul effective value.
*/
static inline void pll_config_init(struct pll_config *p_cfg,
enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul)
{
enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul) {
uint32_t vco_hz;
Assert(e_src < PLL_NR_SOURCES);
if (ul_div == 0 && ul_mul == 0) { /* Must only be true for UTMI PLL */
p_cfg->ctrl = CKGR_UCKR_UPLLCOUNT(PLL_COUNT);
} else { /* PLLA */
}
else { /* PLLA */
/* Calculate internal VCO frequency */
vco_hz = osc_get_rate(e_src) / ul_div;
Assert(vco_hz >= PLL_INPUT_MIN_HZ);
@@ -142,68 +142,55 @@ static inline void pll_config_init(struct pll_config *p_cfg,
CONFIG_PLL##pll_id##_DIV, \
CONFIG_PLL##pll_id##_MUL)
static inline void pll_config_read(struct pll_config *p_cfg, uint32_t ul_pll_id)
{
static inline void pll_config_read(struct pll_config *p_cfg, uint32_t ul_pll_id) {
Assert(ul_pll_id < NR_PLLS);
if (ul_pll_id == PLLA_ID) {
p_cfg->ctrl = PMC->CKGR_PLLAR;
} else {
p_cfg->ctrl = PMC->CKGR_UCKR;
}
p_cfg->ctrl = ul_pll_id == PLLA_ID ? PMC->CKGR_PLLAR : PMC->CKGR_UCKR;
}
static inline void pll_config_write(const struct pll_config *p_cfg, uint32_t ul_pll_id)
{
static inline void pll_config_write(const struct pll_config *p_cfg, uint32_t ul_pll_id) {
Assert(ul_pll_id < NR_PLLS);
if (ul_pll_id == PLLA_ID) {
pmc_disable_pllack(); // Always stop PLL first!
PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;
} else {
}
else
PMC->CKGR_UCKR = p_cfg->ctrl;
}
}
static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id)
{
static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id) {
Assert(ul_pll_id < NR_PLLS);
if (ul_pll_id == PLLA_ID) {
pmc_disable_pllack(); // Always stop PLL first!
PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;
} else {
PMC->CKGR_UCKR = p_cfg->ctrl | CKGR_UCKR_UPLLEN;
}
else
PMC->CKGR_UCKR = p_cfg->ctrl | CKGR_UCKR_UPLLEN;
}
/**
* \note This will only disable the selected PLL, not the underlying oscillator (mainck).
*/
static inline void pll_disable(uint32_t ul_pll_id)
{
static inline void pll_disable(uint32_t ul_pll_id) {
Assert(ul_pll_id < NR_PLLS);
if (ul_pll_id == PLLA_ID) {
if (ul_pll_id == PLLA_ID)
pmc_disable_pllack();
} else {
else
PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;
}
}
static inline uint32_t pll_is_locked(uint32_t ul_pll_id)
{
static inline uint32_t pll_is_locked(uint32_t ul_pll_id) {
Assert(ul_pll_id < NR_PLLS);
if (ul_pll_id == PLLA_ID) {
if (ul_pll_id == PLLA_ID)
return pmc_is_locked_pllack();
} else {
else
return pmc_is_locked_upll();
}
}
static inline void pll_enable_source(enum pll_source e_src)
{
static inline void pll_enable_source(enum pll_source e_src) {
switch (e_src) {
case PLL_SRC_MAINCK_4M_RC:
case PLL_SRC_MAINCK_8M_RC:
@@ -220,15 +207,13 @@ static inline void pll_enable_source(enum pll_source e_src)
}
}
static inline void pll_enable_config_defaults(unsigned int ul_pll_id)
{
static inline void pll_enable_config_defaults(unsigned int ul_pll_id) {
struct pll_config pllcfg;
if (pll_is_locked(ul_pll_id)) {
return; // Pll already running
}
if (pll_is_locked(ul_pll_id)) return; // Pll already running
switch (ul_pll_id) {
#ifdef CONFIG_PLL0_SOURCE
#ifdef CONFIG_PLL0_SOURCE
case 0:
pll_enable_source(CONFIG_PLL0_SOURCE);
pll_config_init(&pllcfg,
@@ -236,8 +221,8 @@ static inline void pll_enable_config_defaults(unsigned int ul_pll_id)
CONFIG_PLL0_DIV,
CONFIG_PLL0_MUL);
break;
#endif
#ifdef CONFIG_PLL1_SOURCE
#endif
#ifdef CONFIG_PLL1_SOURCE
case 1:
pll_enable_source(CONFIG_PLL1_SOURCE);
pll_config_init(&pllcfg,
@@ -245,7 +230,7 @@ static inline void pll_enable_config_defaults(unsigned int ul_pll_id)
CONFIG_PLL1_DIV,
CONFIG_PLL1_MUL);
break;
#endif
#endif
default:
Assert(false);
break;
@@ -264,13 +249,10 @@ static inline void pll_enable_config_defaults(unsigned int ul_pll_id)
* \retval STATUS_OK The PLL is now locked.
* \retval ERR_TIMEOUT Timed out waiting for PLL to become locked.
*/
static inline int pll_wait_for_lock(unsigned int pll_id)
{
static inline int pll_wait_for_lock(unsigned int pll_id) {
Assert(pll_id < NR_PLLS);
while (!pll_is_locked(pll_id)) {
/* Do nothing */
}
while (!pll_is_locked(pll_id)) { /* Do nothing */ }
return 0;
}

View File

@@ -51,5 +51,4 @@
#include "stringz.h"
#include "mrepeat.h"
#endif // _PREPROCESSOR_H_

View File

@@ -57,7 +57,6 @@
#ifndef _SBC_PROTOCOL_H_
#define _SBC_PROTOCOL_H_
/**
* \ingroup usb_msc_protocol
* \defgroup usb_sbc_protocol SCSI Block Commands protocol definitions
@@ -87,7 +86,6 @@ enum scsi_sbc_mode {
SCSI_MS_MODE_CACHING = 0x08, //!< Caching mode page
};
//! \name SBC-2 Device-Specific Parameter
//@{
#define SCSI_MS_SBC_WP 0x80 //!< Write Protected
@@ -139,16 +137,16 @@ struct sbc_caching_mode_page {
struct sbc_rdwr_error_recovery_mode_page {
uint8_t page_code;
uint8_t page_length;
#define SPC_MP_RW_ERR_RECOV_PAGE_LENGTH 0x0A
#define SPC_MP_RW_ERR_RECOV_PAGE_LENGTH 0x0A
uint8_t flags1;
#define SBC_MP_RW_ERR_RECOV_AWRE (1 << 7)
#define SBC_MP_RW_ERR_RECOV_ARRE (1 << 6)
#define SBC_MP_RW_ERR_RECOV_TB (1 << 5)
#define SBC_MP_RW_ERR_RECOV_RC (1 << 4)
#define SBC_MP_RW_ERR_RECOV_ERR (1 << 3)
#define SBC_MP_RW_ERR_RECOV_PER (1 << 2)
#define SBC_MP_RW_ERR_RECOV_DTE (1 << 1)
#define SBC_MP_RW_ERR_RECOV_DCR (1 << 0)
#define SBC_MP_RW_ERR_RECOV_AWRE (1 << 7)
#define SBC_MP_RW_ERR_RECOV_ARRE (1 << 6)
#define SBC_MP_RW_ERR_RECOV_TB (1 << 5)
#define SBC_MP_RW_ERR_RECOV_RC (1 << 4)
#define SBC_MP_RW_ERR_RECOV_ERR (1 << 3)
#define SBC_MP_RW_ERR_RECOV_PER (1 << 2)
#define SBC_MP_RW_ERR_RECOV_DTE (1 << 1)
#define SBC_MP_RW_ERR_RECOV_DCR (1 << 0)
uint8_t read_retry_count;
uint8_t correction_span;
uint8_t head_offset_count;

View File

@@ -45,7 +45,6 @@
* Support and FAQ: visit <a href="https://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SD_MMC_SPI_MEM_H_
#define _SD_MMC_SPI_MEM_H_
@@ -63,17 +62,14 @@
#error sd_mmc_spi_mem.h is #included although SD_MMC_SPI_MEM is disabled
#endif
#include "ctrl_access.h"
//_____ D E F I N I T I O N S ______________________________________________
#define SD_MMC_REMOVED 0
#define SD_MMC_INSERTED 1
#define SD_MMC_REMOVING 2
//---- CONTROL FUNCTIONS ----
//!
//! @brief This function initializes the hw/sw resources required to drive the SD_MMC_SPI.
@@ -133,7 +129,6 @@ extern bool sd_mmc_spi_wr_protect(void);
//!
extern bool sd_mmc_spi_removal(void);
//---- ACCESS DATA FUNCTIONS ----
#if ACCESS_USB == true

View File

@@ -85,51 +85,51 @@ COMPILER_PACK_SET(1)
*/
struct scsi_inquiry_data {
uint8_t pq_pdt; //!< Peripheral Qual / Peripheral Dev Type
#define SCSI_INQ_PQ_CONNECTED 0x00 //!< Peripheral connected
#define SCSI_INQ_PQ_NOT_CONN 0x20 //!< Peripheral not connected
#define SCSI_INQ_PQ_NOT_SUPP 0x60 //!< Peripheral not supported
#define SCSI_INQ_DT_DIR_ACCESS 0x00 //!< Direct Access (SBC)
#define SCSI_INQ_DT_SEQ_ACCESS 0x01 //!< Sequential Access
#define SCSI_INQ_DT_PRINTER 0x02 //!< Printer
#define SCSI_INQ_DT_PROCESSOR 0x03 //!< Processor device
#define SCSI_INQ_DT_WRITE_ONCE 0x04 //!< Write-once device
#define SCSI_INQ_DT_CD_DVD 0x05 //!< CD/DVD device
#define SCSI_INQ_DT_OPTICAL 0x07 //!< Optical Memory
#define SCSI_INQ_DT_MC 0x08 //!< Medium Changer
#define SCSI_INQ_DT_ARRAY 0x0C //!< Storage Array Controller
#define SCSI_INQ_DT_ENCLOSURE 0x0D //!< Enclosure Services
#define SCSI_INQ_DT_RBC 0x0E //!< Simplified Direct Access
#define SCSI_INQ_DT_OCRW 0x0F //!< Optical card reader/writer
#define SCSI_INQ_DT_BCC 0x10 //!< Bridge Controller Commands
#define SCSI_INQ_DT_OSD 0x11 //!< Object-based Storage
#define SCSI_INQ_DT_NONE 0x1F //!< No Peripheral
#define SCSI_INQ_PQ_CONNECTED 0x00 //!< Peripheral connected
#define SCSI_INQ_PQ_NOT_CONN 0x20 //!< Peripheral not connected
#define SCSI_INQ_PQ_NOT_SUPP 0x60 //!< Peripheral not supported
#define SCSI_INQ_DT_DIR_ACCESS 0x00 //!< Direct Access (SBC)
#define SCSI_INQ_DT_SEQ_ACCESS 0x01 //!< Sequential Access
#define SCSI_INQ_DT_PRINTER 0x02 //!< Printer
#define SCSI_INQ_DT_PROCESSOR 0x03 //!< Processor device
#define SCSI_INQ_DT_WRITE_ONCE 0x04 //!< Write-once device
#define SCSI_INQ_DT_CD_DVD 0x05 //!< CD/DVD device
#define SCSI_INQ_DT_OPTICAL 0x07 //!< Optical Memory
#define SCSI_INQ_DT_MC 0x08 //!< Medium Changer
#define SCSI_INQ_DT_ARRAY 0x0C //!< Storage Array Controller
#define SCSI_INQ_DT_ENCLOSURE 0x0D //!< Enclosure Services
#define SCSI_INQ_DT_RBC 0x0E //!< Simplified Direct Access
#define SCSI_INQ_DT_OCRW 0x0F //!< Optical card reader/writer
#define SCSI_INQ_DT_BCC 0x10 //!< Bridge Controller Commands
#define SCSI_INQ_DT_OSD 0x11 //!< Object-based Storage
#define SCSI_INQ_DT_NONE 0x1F //!< No Peripheral
uint8_t flags1; //!< Flags (byte 1)
#define SCSI_INQ_RMB 0x80 //!< Removable Medium
#define SCSI_INQ_RMB 0x80 //!< Removable Medium
uint8_t version; //!< Version
#define SCSI_INQ_VER_NONE 0x00 //!< No standards conformance
#define SCSI_INQ_VER_SPC 0x03 //!< SCSI Primary Commands (link to SBC)
#define SCSI_INQ_VER_SPC2 0x04 //!< SCSI Primary Commands - 2 (link to SBC-2)
#define SCSI_INQ_VER_SPC3 0x05 //!< SCSI Primary Commands - 3 (link to SBC-2)
#define SCSI_INQ_VER_SPC4 0x06 //!< SCSI Primary Commands - 4 (link to SBC-3)
#define SCSI_INQ_VER_NONE 0x00 //!< No standards conformance
#define SCSI_INQ_VER_SPC 0x03 //!< SCSI Primary Commands (link to SBC)
#define SCSI_INQ_VER_SPC2 0x04 //!< SCSI Primary Commands - 2 (link to SBC-2)
#define SCSI_INQ_VER_SPC3 0x05 //!< SCSI Primary Commands - 3 (link to SBC-2)
#define SCSI_INQ_VER_SPC4 0x06 //!< SCSI Primary Commands - 4 (link to SBC-3)
uint8_t flags3; //!< Flags (byte 3)
#define SCSI_INQ_NORMACA 0x20 //!< Normal ACA Supported
#define SCSI_INQ_HISUP 0x10 //!< Hierarchal LUN addressing
#define SCSI_INQ_RSP_SPC2 0x02 //!< SPC-2 / SPC-3 response format
#define SCSI_INQ_NORMACA 0x20 //!< Normal ACA Supported
#define SCSI_INQ_HISUP 0x10 //!< Hierarchal LUN addressing
#define SCSI_INQ_RSP_SPC2 0x02 //!< SPC-2 / SPC-3 response format
uint8_t addl_len; //!< Additional Length (n-4)
#define SCSI_INQ_ADDL_LEN(tot) ((tot)-5) //!< Total length is \a tot
#define SCSI_INQ_ADDL_LEN(tot) ((tot)-5) //!< Total length is \a tot
uint8_t flags5; //!< Flags (byte 5)
#define SCSI_INQ_SCCS 0x80
#define SCSI_INQ_SCCS 0x80
uint8_t flags6; //!< Flags (byte 6)
#define SCSI_INQ_BQUE 0x80
#define SCSI_INQ_ENCSERV 0x40
#define SCSI_INQ_MULTIP 0x10
#define SCSI_INQ_MCHGR 0x08
#define SCSI_INQ_ADDR16 0x01
#define SCSI_INQ_BQUE 0x80
#define SCSI_INQ_ENCSERV 0x40
#define SCSI_INQ_MULTIP 0x10
#define SCSI_INQ_MCHGR 0x08
#define SCSI_INQ_ADDR16 0x01
uint8_t flags7; //!< Flags (byte 7)
#define SCSI_INQ_WBUS16 0x20
#define SCSI_INQ_SYNC 0x10
#define SCSI_INQ_LINKED 0x08
#define SCSI_INQ_CMDQUE 0x02
#define SCSI_INQ_WBUS16 0x20
#define SCSI_INQ_SYNC 0x10
#define SCSI_INQ_LINKED 0x08
#define SCSI_INQ_CMDQUE 0x02
uint8_t vendor_id[8]; //!< T10 Vendor Identification
uint8_t product_id[16]; //!< Product Identification
uint8_t product_rev[4]; //!< Product Revision Level
@@ -141,28 +141,28 @@ struct scsi_inquiry_data {
struct scsi_request_sense_data {
/* 1st byte: REQUEST SENSE response flags*/
uint8_t valid_reponse_code;
#define SCSI_SENSE_VALID 0x80 //!< Indicates the INFORMATION field contains valid information
#define SCSI_SENSE_RESPONSE_CODE_MASK 0x7F
#define SCSI_SENSE_CURRENT 0x70 //!< Response code 70h (current errors)
#define SCSI_SENSE_DEFERRED 0x71
#define SCSI_SENSE_VALID 0x80 //!< Indicates the INFORMATION field contains valid information
#define SCSI_SENSE_RESPONSE_CODE_MASK 0x7F
#define SCSI_SENSE_CURRENT 0x70 //!< Response code 70h (current errors)
#define SCSI_SENSE_DEFERRED 0x71
/* 2nd byte */
uint8_t obsolete;
/* 3rd byte */
uint8_t sense_flag_key;
#define SCSI_SENSE_FILEMARK 0x80 //!< Indicates that the current command has read a filemark or setmark.
#define SCSI_SENSE_EOM 0x40 //!< Indicates that an end-of-medium condition exists.
#define SCSI_SENSE_ILI 0x20 //!< Indicates that the requested logical block length did not match the logical block length of the data on the medium.
#define SCSI_SENSE_RESERVED 0x10 //!< Reserved
#define SCSI_SENSE_KEY(x) (x&0x0F) //!< Sense Key
#define SCSI_SENSE_FILEMARK 0x80 //!< Indicates that the current command has read a filemark or setmark.
#define SCSI_SENSE_EOM 0x40 //!< Indicates that an end-of-medium condition exists.
#define SCSI_SENSE_ILI 0x20 //!< Indicates that the requested logical block length did not match the logical block length of the data on the medium.
#define SCSI_SENSE_RESERVED 0x10 //!< Reserved
#define SCSI_SENSE_KEY(x) (x&0x0F) //!< Sense Key
/* 4th to 7th bytes - INFORMATION field */
uint8_t information[4];
/* 8th byte - ADDITIONAL SENSE LENGTH field */
uint8_t AddSenseLen;
#define SCSI_SENSE_ADDL_LEN(total_len) ((total_len) - 8)
#define SCSI_SENSE_ADDL_LEN(total_len) ((total_len) - 8)
/* 9th to 12th byte - COMMAND-SPECIFIC INFORMATION field */
uint8_t CmdSpecINFO[4];
@@ -178,7 +178,7 @@ struct scsi_request_sense_data {
/* 16th byte */
uint8_t SenseKeySpec[3];
#define SCSI_SENSE_SKSV 0x80 //!< Indicates the SENSE-KEY SPECIFIC field contains valid information
#define SCSI_SENSE_SKSV 0x80 //!< Indicates the SENSE-KEY SPECIFIC field contains valid information
};
COMPILER_PACK_RESET()
@@ -200,7 +200,6 @@ enum scsi_vpd_page_code {
#define SCSI_VPD_ID_TYPE_T10 1
/* Sense keys */
enum scsi_sense_key {
SCSI_SK_NO_SENSE = 0x0,
@@ -252,27 +251,26 @@ enum scsi_spc_mode {
struct spc_control_page_info_execpt {
uint8_t page_code;
uint8_t page_length;
#define SPC_MP_INFEXP_PAGE_LENGTH 0x0A
#define SPC_MP_INFEXP_PAGE_LENGTH 0x0A
uint8_t flags1;
#define SPC_MP_INFEXP_PERF (1<<7) //!< Initiator Control
#define SPC_MP_INFEXP_EBF (1<<5) //!< Caching Analysis Permitted
#define SPC_MP_INFEXP_EWASC (1<<4) //!< Discontinuity
#define SPC_MP_INFEXP_DEXCPT (1<<3) //!< Size enable
#define SPC_MP_INFEXP_TEST (1<<2) //!< Writeback Cache Enable
#define SPC_MP_INFEXP_LOGERR (1<<0) //!< Log errors bit
#define SPC_MP_INFEXP_PERF (1<<7) //!< Initiator Control
#define SPC_MP_INFEXP_EBF (1<<5) //!< Caching Analysis Permitted
#define SPC_MP_INFEXP_EWASC (1<<4) //!< Discontinuity
#define SPC_MP_INFEXP_DEXCPT (1<<3) //!< Size enable
#define SPC_MP_INFEXP_TEST (1<<2) //!< Writeback Cache Enable
#define SPC_MP_INFEXP_LOGERR (1<<0) //!< Log errors bit
uint8_t mrie;
#define SPC_MP_INFEXP_MRIE_NO_REPORT 0x00
#define SPC_MP_INFEXP_MRIE_ASYNC_EVENT 0x01
#define SPC_MP_INFEXP_MRIE_GEN_UNIT 0x02
#define SPC_MP_INFEXP_MRIE_COND_RECOV_ERROR 0x03
#define SPC_MP_INFEXP_MRIE_UNCOND_RECOV_ERROR 0x04
#define SPC_MP_INFEXP_MRIE_NO_SENSE 0x05
#define SPC_MP_INFEXP_MRIE_ONLY_REPORT 0x06
#define SPC_MP_INFEXP_MRIE_NO_REPORT 0x00
#define SPC_MP_INFEXP_MRIE_ASYNC_EVENT 0x01
#define SPC_MP_INFEXP_MRIE_GEN_UNIT 0x02
#define SPC_MP_INFEXP_MRIE_COND_RECOV_ERROR 0x03
#define SPC_MP_INFEXP_MRIE_UNCOND_RECOV_ERROR 0x04
#define SPC_MP_INFEXP_MRIE_NO_SENSE 0x05
#define SPC_MP_INFEXP_MRIE_ONLY_REPORT 0x06
be32_t interval_timer;
be32_t report_count;
};
enum scsi_spc_mode_sense_pc {
SCSI_MS_SENSE_PC_CURRENT = 0,
SCSI_MS_SENSE_PC_CHANGEABLE = 1,
@@ -280,20 +278,15 @@ enum scsi_spc_mode_sense_pc {
SCSI_MS_SENSE_PC_SAVED = 3,
};
static inline bool scsi_mode_sense_dbd_is_set(const uint8_t * cdb)
{
static inline bool scsi_mode_sense_dbd_is_set(const uint8_t * cdb) {
return (cdb[1] >> 3) & 1;
}
static inline uint8_t scsi_mode_sense_get_page_code(const uint8_t * cdb)
{
static inline uint8_t scsi_mode_sense_get_page_code(const uint8_t * cdb) {
return cdb[2] & 0x3F;
}
static inline uint8_t scsi_mode_sense_get_pc(const uint8_t * cdb)
{
static inline uint8_t scsi_mode_sense_get_pc(const uint8_t * cdb) {
return cdb[2] >> 6;
}

View File

@@ -136,7 +136,7 @@ extern "C" {
* initialization.
*/
#ifndef CONFIG_SYSCLK_SOURCE
# define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC
#endif
/**
* \def CONFIG_SYSCLK_PRES
@@ -149,7 +149,7 @@ extern "C" {
* after initialization.
*/
#ifndef CONFIG_SYSCLK_PRES
# define CONFIG_SYSCLK_PRES 0
#define CONFIG_SYSCLK_PRES 0
#endif
//@}
@@ -197,7 +197,7 @@ extern "C" {
* USB is not required.
*/
#ifdef __DOXYGEN__
# define CONFIG_USBCLK_SOURCE
#define CONFIG_USBCLK_SOURCE
#endif
/**
@@ -209,10 +209,9 @@ extern "C" {
* defined.
*/
#ifdef __DOXYGEN__
# define CONFIG_USBCLK_DIV
#define CONFIG_USBCLK_DIV
#endif
extern void sysclk_enable_usb(void);
extern void sysclk_disable_usb(void);

View File

@@ -83,7 +83,6 @@ static usb_iface_desc_t UDC_DESC_STORAGE *udc_ptr_iface;
//! @}
//! \name Internal structure to store the USB device main strings
//! @{

View File

@@ -172,8 +172,7 @@ extern "C" {
}
\endcode
*/
static inline bool udc_include_vbus_monitoring(void)
{
static inline bool udc_include_vbus_monitoring(void) {
return udd_include_vbus_monitoring();
}
@@ -192,32 +191,26 @@ void udc_stop(void);
* then it will attach device when an acceptable Vbus
* level from the host is detected.
*/
static inline void udc_attach(void)
{
static inline void udc_attach(void) {
udd_attach();
}
/**
* \brief Detaches the device from the bus
*
* The driver must remove pull-up on USB line D- or D+.
*/
static inline void udc_detach(void)
{
static inline void udc_detach(void) {
udd_detach();
}
/*! \brief The USB driver sends a resume signal called \e "Upstream Resume"
* This is authorized only when the remote wakeup feature is enabled by host.
*/
static inline void udc_remotewakeup(void)
{
static inline void udc_remotewakeup(void) {
udd_send_remotewakeup();
}
/**
* \brief Returns a pointer on the current interface descriptor
*
@@ -692,6 +685,4 @@ usb_iface_desc_t UDC_DESC_STORAGE *udc_get_interface_desc(void);
} \endcode
*/
#endif // _UDC_H_

View File

@@ -80,19 +80,17 @@ extern "C" {
#define UDC_DESC_STORAGE
// Descriptor storage in internal RAM
#if (defined UDC_DATA_USE_HRAM_SUPPORT)
# if defined(__GNUC__)
# define UDC_DATA(x) COMPILER_WORD_ALIGNED __attribute__((__section__(".data_hram0")))
# define UDC_BSS(x) COMPILER_ALIGNED(x) __attribute__((__section__(".bss_hram0")))
# elif defined(__ICCAVR32__)
# define UDC_DATA(x) COMPILER_ALIGNED(x) __data32
# define UDC_BSS(x) COMPILER_ALIGNED(x) __data32
# endif
#else
# define UDC_DATA(x) COMPILER_ALIGNED(x)
# define UDC_BSS(x) COMPILER_ALIGNED(x)
#if defined(__GNUC__)
#define UDC_DATA(x) COMPILER_WORD_ALIGNED __attribute__((__section__(".data_hram0")))
#define UDC_BSS(x) COMPILER_ALIGNED(x) __attribute__((__section__(".bss_hram0")))
#elif defined(__ICCAVR32__)
#define UDC_DATA(x) COMPILER_ALIGNED(x) __data32
#define UDC_BSS(x) COMPILER_ALIGNED(x) __data32
#endif
#else
#define UDC_DATA(x) COMPILER_ALIGNED(x)
#define UDC_BSS(x) COMPILER_ALIGNED(x)
#endif
/**
* \brief Configuration descriptor and UDI link for one USB speed
@@ -104,7 +102,6 @@ typedef struct {
udi_api_t UDC_DESC_STORAGE *UDC_DESC_STORAGE * udi_apis;
} udc_config_speed_t;
/**
* \brief All information about the USB Device
*/
@@ -113,14 +110,14 @@ typedef struct {
usb_dev_desc_t UDC_DESC_STORAGE *confdev_lsfs;
//! USB configuration descriptor and UDI API pointers for low or full speed
udc_config_speed_t UDC_DESC_STORAGE *conf_lsfs;
#ifdef USB_DEVICE_HS_SUPPORT
#ifdef USB_DEVICE_HS_SUPPORT
//! USB device descriptor for high speed
usb_dev_desc_t UDC_DESC_STORAGE *confdev_hs;
//! USB device qualifier, only use in high speed mode
usb_dev_qual_desc_t UDC_DESC_STORAGE *qualifier;
//! USB configuration descriptor and UDI API pointers for high speed
udc_config_speed_t UDC_DESC_STORAGE *conf_hs;
#endif
#endif
usb_dev_bos_desc_t UDC_DESC_STORAGE *conf_bos;
} udc_config_t;

View File

@@ -103,20 +103,16 @@ typedef struct {
extern udd_ctrl_request_t udd_g_ctrlreq;
//! Return true if the setup request \a udd_g_ctrlreq indicates IN data transfer
#define Udd_setup_is_in() \
(USB_REQ_DIR_IN == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK))
#define Udd_setup_is_in() (USB_REQ_DIR_IN == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK))
//! Return true if the setup request \a udd_g_ctrlreq indicates OUT data transfer
#define Udd_setup_is_out() \
(USB_REQ_DIR_OUT == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK))
#define Udd_setup_is_out() (USB_REQ_DIR_OUT == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK))
//! Return the type of the SETUP request \a udd_g_ctrlreq. \see usb_reqtype.
#define Udd_setup_type() \
(udd_g_ctrlreq.req.bmRequestType & USB_REQ_TYPE_MASK)
#define Udd_setup_type() (udd_g_ctrlreq.req.bmRequestType & USB_REQ_TYPE_MASK)
//! Return the recipient of the SETUP request \a udd_g_ctrlreq. \see usb_recipient
#define Udd_setup_recipient() \
(udd_g_ctrlreq.req.bmRequestType & USB_REQ_RECIP_MASK)
#define Udd_setup_recipient() (udd_g_ctrlreq.req.bmRequestType & USB_REQ_RECIP_MASK)
/**
* \brief End of halt callback function type.
@@ -134,8 +130,7 @@ typedef void (*udd_callback_halt_cleared_t)(void);
* \param status UDD_EP_TRANSFER_ABORT, if transfer is aborted
* \param n number of data transferred
*/
typedef void (*udd_callback_trans_t) (udd_ep_status_t status,
iram_size_t nb_transferred, udd_ep_id_t ep);
typedef void (*udd_callback_trans_t) (udd_ep_status_t status, iram_size_t nb_transferred, udd_ep_id_t ep);
/**
* \brief Authorizes the VBUS event
@@ -218,7 +213,6 @@ void udd_send_remotewakeup(void);
*/
void udd_set_setup_payload( uint8_t *payload, uint16_t payload_size );
/**
* \name Endpoint Management
*
@@ -239,8 +233,7 @@ void udd_set_setup_payload( uint8_t *payload, uint16_t payload_size );
*
* \return \c 1 if the endpoint is enabled, otherwise \c 0.
*/
bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes,
uint16_t MaxEndpointSize);
bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes, uint16_t MaxEndpointSize);
/**
* \brief Disables an endpoint
@@ -294,8 +287,7 @@ bool udd_ep_clear_halt(udd_ep_id_t ep);
*
* \return \c 1 if the register is accepted, otherwise \c 0.
*/
bool udd_ep_wait_stall_clear(udd_ep_id_t ep,
udd_callback_halt_cleared_t callback);
bool udd_ep_wait_stall_clear(udd_ep_id_t ep, udd_callback_halt_cleared_t callback);
/**
* \brief Allows to receive or send data on an endpoint
@@ -321,9 +313,8 @@ bool udd_ep_wait_stall_clear(udd_ep_id_t ep,
*
* \return \c 1 if function was successfully done, otherwise \c 0.
*/
bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket,
uint8_t * buf, iram_size_t buf_size,
udd_callback_trans_t callback);
bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket, uint8_t * buf, iram_size_t buf_size, udd_callback_trans_t callback);
/**
* \brief Aborts transfer on going on endpoint
*
@@ -339,7 +330,6 @@ void udd_ep_abort(udd_ep_id_t ep);
//@}
/**
* \name High speed test mode management
*
@@ -352,7 +342,6 @@ void udd_test_mode_se0_nak(void);
void udd_test_mode_packet(void);
//@}
/**
* \name UDC callbacks to provide for UDD
*

View File

@@ -457,7 +457,6 @@ void udi_cdc_data_sof_notify(void)
#endif
}
// ------------------------
//------- Internal routines to control serial line
@@ -520,7 +519,6 @@ static void udi_cdc_ctrl_state_change(uint8_t port, bool b_set, le16_t bit_mask)
udi_cdc_ctrl_state_notify(port, ep_comm);
}
static void udi_cdc_ctrl_state_notify(uint8_t port, udd_ep_id_t ep)
{
#if UDI_CDC_PORT_NB == 1 // To optimize code
@@ -542,7 +540,6 @@ static void udi_cdc_ctrl_state_notify(uint8_t port, udd_ep_id_t ep)
}
}
static void udi_cdc_serial_state_msg_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep)
{
uint8_t port;
@@ -578,11 +575,9 @@ static void udi_cdc_serial_state_msg_sent(udd_ep_status_t status, iram_size_t n,
udi_cdc_ctrl_state_notify(port, ep);
}
// ------------------------
//------- Internal routines to process data transfer
static bool udi_cdc_rx_start(uint8_t port)
{
irqflags_t flags;
@@ -632,7 +627,6 @@ static bool udi_cdc_rx_start(uint8_t port)
udi_cdc_data_received);
}
static void udi_cdc_data_received(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep)
{
uint8_t buf_sel_trans;
@@ -668,7 +662,6 @@ static void udi_cdc_data_received(udd_ep_status_t status, iram_size_t n, udd_ep_
udi_cdc_rx_start(port);
}
static void udi_cdc_data_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep)
{
uint8_t port;
@@ -700,7 +693,6 @@ static void udi_cdc_data_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t
udi_cdc_tx_send(port);
}
static void udi_cdc_tx_send(uint8_t port)
{
irqflags_t flags;
@@ -780,11 +772,9 @@ static void udi_cdc_tx_send(uint8_t port)
udi_cdc_data_sent);
}
// ------------------------
//------- Application interface
//------- Application interface
void udi_cdc_ctrl_signal_dcd(bool b_set)

View File

@@ -106,7 +106,6 @@ typedef struct {
usb_ep_desc_t ep_notify;
} udi_cdc_comm_desc_t;
/**
* \brief Data Class interface descriptor
*
@@ -121,7 +120,6 @@ typedef struct {
usb_ep_desc_t ep_out;
} udi_cdc_data_desc_t;
//! CDC communication endpoints size for all speeds
#define UDI_CDC_COMM_EP_SIZE 64
//! CDC data endpoints size for FS speed (8B, 16B, 32B, 64B)
@@ -136,13 +134,13 @@ typedef struct {
//@{
//! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_0
#define UDI_CDC_IAD_STRING_ID_0 0
#define UDI_CDC_IAD_STRING_ID_0 0
#endif
#ifndef UDI_CDC_COMM_STRING_ID_0
#define UDI_CDC_COMM_STRING_ID_0 0
#define UDI_CDC_COMM_STRING_ID_0 0
#endif
#ifndef UDI_CDC_DATA_STRING_ID_0
#define UDI_CDC_DATA_STRING_ID_0 0
#define UDI_CDC_DATA_STRING_ID_0 0
#endif
#define UDI_CDC_IAD_DESC_0 UDI_CDC_IAD_DESC(0)
#define UDI_CDC_COMM_DESC_0 UDI_CDC_COMM_DESC(0)
@@ -151,13 +149,13 @@ typedef struct {
//! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_1
#define UDI_CDC_IAD_STRING_ID_1 0
#define UDI_CDC_IAD_STRING_ID_1 0
#endif
#ifndef UDI_CDC_COMM_STRING_ID_1
#define UDI_CDC_COMM_STRING_ID_1 0
#define UDI_CDC_COMM_STRING_ID_1 0
#endif
#ifndef UDI_CDC_DATA_STRING_ID_1
#define UDI_CDC_DATA_STRING_ID_1 0
#define UDI_CDC_DATA_STRING_ID_1 0
#endif
#define UDI_CDC_IAD_DESC_1 UDI_CDC_IAD_DESC(1)
#define UDI_CDC_COMM_DESC_1 UDI_CDC_COMM_DESC(1)
@@ -166,13 +164,13 @@ typedef struct {
//! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_2
#define UDI_CDC_IAD_STRING_ID_2 0
#define UDI_CDC_IAD_STRING_ID_2 0
#endif
#ifndef UDI_CDC_COMM_STRING_ID_2
#define UDI_CDC_COMM_STRING_ID_2 0
#define UDI_CDC_COMM_STRING_ID_2 0
#endif
#ifndef UDI_CDC_DATA_STRING_ID_2
#define UDI_CDC_DATA_STRING_ID_2 0
#define UDI_CDC_DATA_STRING_ID_2 0
#endif
#define UDI_CDC_IAD_DESC_2 UDI_CDC_IAD_DESC(2)
#define UDI_CDC_COMM_DESC_2 UDI_CDC_COMM_DESC(2)
@@ -181,13 +179,13 @@ typedef struct {
//! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_3
#define UDI_CDC_IAD_STRING_ID_3 0
#define UDI_CDC_IAD_STRING_ID_3 0
#endif
#ifndef UDI_CDC_COMM_STRING_ID_3
#define UDI_CDC_COMM_STRING_ID_3 0
#define UDI_CDC_COMM_STRING_ID_3 0
#endif
#ifndef UDI_CDC_DATA_STRING_ID_3
#define UDI_CDC_DATA_STRING_ID_3 0
#define UDI_CDC_DATA_STRING_ID_3 0
#endif
#define UDI_CDC_IAD_DESC_3 UDI_CDC_IAD_DESC(3)
#define UDI_CDC_COMM_DESC_3 UDI_CDC_COMM_DESC(3)
@@ -196,13 +194,13 @@ typedef struct {
//! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_4
#define UDI_CDC_IAD_STRING_ID_4 0
#define UDI_CDC_IAD_STRING_ID_4 0
#endif
#ifndef UDI_CDC_COMM_STRING_ID_4
#define UDI_CDC_COMM_STRING_ID_4 0
#define UDI_CDC_COMM_STRING_ID_4 0
#endif
#ifndef UDI_CDC_DATA_STRING_ID_4
#define UDI_CDC_DATA_STRING_ID_4 0
#define UDI_CDC_DATA_STRING_ID_4 0
#endif
#define UDI_CDC_IAD_DESC_4 UDI_CDC_IAD_DESC(4)
#define UDI_CDC_COMM_DESC_4 UDI_CDC_COMM_DESC(4)
@@ -211,13 +209,13 @@ typedef struct {
//! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_5
#define UDI_CDC_IAD_STRING_ID_5 0
#define UDI_CDC_IAD_STRING_ID_5 0
#endif
#ifndef UDI_CDC_COMM_STRING_ID_5
#define UDI_CDC_COMM_STRING_ID_5 0
#define UDI_CDC_COMM_STRING_ID_5 0
#endif
#ifndef UDI_CDC_DATA_STRING_ID_5
#define UDI_CDC_DATA_STRING_ID_5 0
#define UDI_CDC_DATA_STRING_ID_5 0
#endif
#define UDI_CDC_IAD_DESC_5 UDI_CDC_IAD_DESC(5)
#define UDI_CDC_COMM_DESC_5 UDI_CDC_COMM_DESC(5)
@@ -226,13 +224,13 @@ typedef struct {
//! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_6
#define UDI_CDC_IAD_STRING_ID_6 0
#define UDI_CDC_IAD_STRING_ID_6 0
#endif
#ifndef UDI_CDC_COMM_STRING_ID_6
#define UDI_CDC_COMM_STRING_ID_6 0
#define UDI_CDC_COMM_STRING_ID_6 0
#endif
#ifndef UDI_CDC_DATA_STRING_ID_6
#define UDI_CDC_DATA_STRING_ID_6 0
#define UDI_CDC_DATA_STRING_ID_6 0
#endif
#define UDI_CDC_IAD_DESC_6 UDI_CDC_IAD_DESC(6)
#define UDI_CDC_COMM_DESC_6 UDI_CDC_COMM_DESC(6)
@@ -240,7 +238,6 @@ typedef struct {
#define UDI_CDC_DATA_DESC_6_HS UDI_CDC_DATA_DESC_HS(6)
//@}
//! Content of CDC IAD interface descriptor for all speeds
#define UDI_CDC_IAD_DESC(port) { \
.bLength = sizeof(usb_iad_desc_t),\
@@ -627,18 +624,15 @@ iram_size_t udi_cdc_multi_write_buf(uint8_t port, const void* buf, iram_size_t s
* Add to application C-file:
* \code
static bool my_flag_autorize_cdc_transfert = false;
bool my_callback_cdc_enable(void)
{
bool my_callback_cdc_enable(void) {
my_flag_autorize_cdc_transfert = true;
return true;
}
void my_callback_cdc_disable(void)
{
void my_callback_cdc_disable(void) {
my_flag_autorize_cdc_transfert = false;
}
void task(void)
{
void task(void) {
if (my_flag_autorize_cdc_transfert) {
udi_cdc_putc('A');
udi_cdc_getc();

View File

@@ -109,7 +109,6 @@ UDC_DESC_STORAGE usb_dev_desc_t udc_device_desc = {
.bNumConfigurations = 1
};
#ifdef USB_DEVICE_HS_SUPPORT
//! USB Device Qualifier Descriptor for HS
COMPILER_WORD_ALIGNED

View File

@@ -93,7 +93,6 @@ UDC_DESC_STORAGE usb_dev_desc_t udc_device_desc = {
.bNumConfigurations = 1
};
#ifdef USB_DEVICE_HS_SUPPORT
//! USB Device Qualifier Descriptor for HS
COMPILER_WORD_ALIGNED
@@ -147,7 +146,6 @@ UDC_DESC_STORAGE udc_desc_t udc_desc_hs = {
};
#endif
/**
* \name UDC structures which contains all USB Device definitions
*/

View File

@@ -86,7 +86,6 @@ UDC_DESC_STORAGE udi_api_t udi_api_msc = {
};
//@}
/**
* \ingroup udi_msc_group
* \defgroup udi_msc_group_internal Implementation of UDI MSC
@@ -137,7 +136,6 @@ volatile bool udi_msc_b_reset_trans = true;
//@}
/**
* \name Internal routines
*/
@@ -190,7 +188,6 @@ static void udi_msc_cbw_received(udd_ep_status_t status,
static bool udi_msc_cbw_validate(uint32_t alloc_len, uint8_t dir_flag);
//@}
/**
* \name Routines to process small data packet
*/
@@ -217,7 +214,6 @@ static void udi_msc_data_sent(udd_ep_status_t status, iram_size_t nb_sent,
udd_ep_id_t ep);
//@}
/**
* \name Routines to process CSW packet
*/
@@ -250,7 +246,6 @@ static void udi_msc_csw_sent(udd_ep_status_t status, iram_size_t nb_sent,
udd_ep_id_t ep);
//@}
/**
* \name Routines manage sense data
*/
@@ -307,7 +302,6 @@ static void udi_msc_sense_fail_cdb_invalid(void);
static void udi_msc_sense_command_invalid(void);
//@}
/**
* \name Routines manage SCSI Commands
*/
@@ -372,9 +366,7 @@ static void udi_msc_sbc_trans(bool b_read);
//@}
bool udi_msc_enable(void)
{
bool udi_msc_enable(void) {
uint8_t lun;
udi_msc_b_trans_req = false;
udi_msc_b_cbw_invalid = false;
@@ -397,18 +389,14 @@ bool udi_msc_enable(void)
return true;
}
void udi_msc_disable(void)
{
void udi_msc_disable(void) {
udi_msc_b_trans_req = false;
udi_msc_b_ack_trans = true;
udi_msc_b_reset_trans = true;
UDI_MSC_DISABLE_EXT();
}
bool udi_msc_setup(void)
{
bool udi_msc_setup(void) {
if (Udd_setup_is_in()) {
// Requests Interface GET
if (Udd_setup_type() == USB_REQ_TYPE_CLASS) {
@@ -451,17 +439,14 @@ bool udi_msc_setup(void)
return false; // Not supported request
}
uint8_t udi_msc_getsetting(void)
{
uint8_t udi_msc_getsetting(void) {
return 0; // MSC don't have multiple alternate setting
}
// ------------------------
//------- Routines to process CBW packet
static void udi_msc_cbw_invalid(void)
{
static void udi_msc_cbw_invalid(void) {
if (!udi_msc_b_cbw_invalid)
return; // Don't re-stall endpoint if error reset by setup
udd_ep_set_halt(UDI_MSC_EP_OUT);
@@ -469,8 +454,7 @@ static void udi_msc_cbw_invalid(void)
udd_ep_wait_stall_clear(UDI_MSC_EP_OUT, udi_msc_cbw_invalid);
}
static void udi_msc_csw_invalid(void)
{
static void udi_msc_csw_invalid(void) {
if (!udi_msc_b_cbw_invalid)
return; // Don't re-stall endpoint if error reset by setup
udd_ep_set_halt(UDI_MSC_EP_IN);
@@ -478,8 +462,7 @@ static void udi_msc_csw_invalid(void)
udd_ep_wait_stall_clear(UDI_MSC_EP_IN, udi_msc_csw_invalid);
}
static void udi_msc_cbw_wait(void)
{
static void udi_msc_cbw_wait(void) {
// Register buffer and callback on OUT endpoint
if (!udd_ep_run(UDI_MSC_EP_OUT, true,
(uint8_t *) & udi_msc_cbw,
@@ -490,10 +473,8 @@ static void udi_msc_cbw_wait(void)
}
}
static void udi_msc_cbw_received(udd_ep_status_t status,
iram_size_t nb_received, udd_ep_id_t ep)
{
iram_size_t nb_received, udd_ep_id_t ep) {
UNUSED(ep);
// Check status of transfer
if (UDD_EP_TRANSFER_OK != status) {
@@ -582,9 +563,7 @@ static void udi_msc_cbw_received(udd_ep_status_t status,
}
}
static bool udi_msc_cbw_validate(uint32_t alloc_len, uint8_t dir_flag)
{
static bool udi_msc_cbw_validate(uint32_t alloc_len, uint8_t dir_flag) {
/*
* The following cases should result in a phase error:
* - Case 2: Hn < Di
@@ -612,12 +591,10 @@ static bool udi_msc_cbw_validate(uint32_t alloc_len, uint8_t dir_flag)
return true;
}
// ------------------------
//------- Routines to process small data packet
static void udi_msc_data_send(uint8_t * buffer, uint8_t buf_size)
{
static void udi_msc_data_send(uint8_t * buffer, uint8_t buf_size) {
// Sends data on IN endpoint
if (!udd_ep_run(UDI_MSC_EP_IN, true,
buffer, buf_size, udi_msc_data_sent)) {
@@ -627,10 +604,8 @@ static void udi_msc_data_send(uint8_t * buffer, uint8_t buf_size)
}
}
static void udi_msc_data_sent(udd_ep_status_t status, iram_size_t nb_sent,
udd_ep_id_t ep)
{
udd_ep_id_t ep) {
UNUSED(ep);
if (UDD_EP_TRANSFER_OK != status) {
// Error protocol
@@ -644,12 +619,10 @@ static void udi_msc_data_sent(udd_ep_status_t status, iram_size_t nb_sent,
udi_msc_csw_process();
}
// ------------------------
//------- Routines to process CSW packet
static void udi_msc_csw_process(void)
{
static void udi_msc_csw_process(void) {
if (0 != udi_msc_csw.dCSWDataResidue) {
// Residue not NULL
// then STALL next request from USB host on corresponding endpoint
@@ -664,9 +637,7 @@ static void udi_msc_csw_process(void)
udi_msc_csw_send();
}
void udi_msc_csw_send(void)
{
void udi_msc_csw_send(void) {
// Sends CSW on IN endpoint
if (!udd_ep_run(UDI_MSC_EP_IN, false,
(uint8_t *) & udi_msc_csw,
@@ -678,10 +649,8 @@ void udi_msc_csw_send(void)
}
}
static void udi_msc_csw_sent(udd_ep_status_t status, iram_size_t nb_sent,
udd_ep_id_t ep)
{
udd_ep_id_t ep) {
UNUSED(ep);
UNUSED(status);
UNUSED(nb_sent);
@@ -690,20 +659,17 @@ static void udi_msc_csw_sent(udd_ep_status_t status, iram_size_t nb_sent,
udi_msc_cbw_wait();
}
// ------------------------
//------- Routines manage sense data
static void udi_msc_clear_sense(void)
{
static void udi_msc_clear_sense(void) {
memset((uint8_t*)&udi_msc_sense, 0, sizeof(struct scsi_request_sense_data));
udi_msc_sense.valid_reponse_code = SCSI_SENSE_VALID | SCSI_SENSE_CURRENT;
udi_msc_sense.AddSenseLen = SCSI_SENSE_ADDL_LEN(sizeof(udi_msc_sense));
}
static void udi_msc_sense_fail(uint8_t sense_key, uint16_t add_sense,
uint32_t lba)
{
uint32_t lba) {
udi_msc_clear_sense();
udi_msc_csw.bCSWStatus = USB_CSW_STATUS_FAIL;
udi_msc_sense.sense_flag_key = sense_key;
@@ -715,53 +681,39 @@ static void udi_msc_sense_fail(uint8_t sense_key, uint16_t add_sense,
udi_msc_sense.AddSnsCodeQlfr = add_sense;
}
static void udi_msc_sense_pass(void)
{
static void udi_msc_sense_pass(void) {
udi_msc_clear_sense();
udi_msc_csw.bCSWStatus = USB_CSW_STATUS_PASS;
}
static void udi_msc_sense_fail_not_present(void)
{
static void udi_msc_sense_fail_not_present(void) {
udi_msc_sense_fail(SCSI_SK_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
}
static void udi_msc_sense_fail_busy_or_change(void)
{
udi_msc_sense_fail(SCSI_SK_UNIT_ATTENTION,
SCSI_ASC_NOT_READY_TO_READY_CHANGE, 0);
static void udi_msc_sense_fail_busy_or_change(void) {
udi_msc_sense_fail(SCSI_SK_UNIT_ATTENTION, SCSI_ASC_NOT_READY_TO_READY_CHANGE, 0);
}
static void udi_msc_sense_fail_hardware(void)
{
udi_msc_sense_fail(SCSI_SK_HARDWARE_ERROR,
SCSI_ASC_NO_ADDITIONAL_SENSE_INFO, 0);
static void udi_msc_sense_fail_hardware(void) {
udi_msc_sense_fail(SCSI_SK_HARDWARE_ERROR, SCSI_ASC_NO_ADDITIONAL_SENSE_INFO, 0);
}
static void udi_msc_sense_fail_protected(void)
{
static void udi_msc_sense_fail_protected(void) {
udi_msc_sense_fail(SCSI_SK_DATA_PROTECT, SCSI_ASC_WRITE_PROTECTED, 0);
}
static void udi_msc_sense_fail_cdb_invalid(void)
{
udi_msc_sense_fail(SCSI_SK_ILLEGAL_REQUEST,
SCSI_ASC_INVALID_FIELD_IN_CDB, 0);
static void udi_msc_sense_fail_cdb_invalid(void) {
udi_msc_sense_fail(SCSI_SK_ILLEGAL_REQUEST, SCSI_ASC_INVALID_FIELD_IN_CDB, 0);
}
static void udi_msc_sense_command_invalid(void)
{
udi_msc_sense_fail(SCSI_SK_ILLEGAL_REQUEST,
SCSI_ASC_INVALID_COMMAND_OPERATION_CODE, 0);
static void udi_msc_sense_command_invalid(void) {
udi_msc_sense_fail(SCSI_SK_ILLEGAL_REQUEST, SCSI_ASC_INVALID_COMMAND_OPERATION_CODE, 0);
}
// ------------------------
//------- Routines manage SCSI Commands
static void udi_msc_spc_requestsense(void)
{
static void udi_msc_spc_requestsense(void) {
uint8_t length = udi_msc_cbw.CDB[4];
// Can't send more than sense data length
@@ -774,9 +726,7 @@ static void udi_msc_spc_requestsense(void)
udi_msc_data_send((uint8_t*)&udi_msc_sense, length);
}
static void udi_msc_spc_inquiry(void)
{
static void udi_msc_spc_inquiry(void) {
uint8_t length, i;
UDC_DATA(4)
// Constant inquiry data for all LUNs
@@ -835,9 +785,7 @@ static void udi_msc_spc_inquiry(void)
udi_msc_data_send((uint8_t *) & udi_msc_inquiry_data, length);
}
static bool udi_msc_spc_testunitready_global(void)
{
static bool udi_msc_spc_testunitready_global(void) {
switch (mem_test_unit_ready(udi_msc_cbw.bCBWLUN)) {
case CTRL_GOOD:
return true; // Don't change sense data
@@ -855,9 +803,7 @@ static bool udi_msc_spc_testunitready_global(void)
return false;
}
static void udi_msc_spc_testunitready(void)
{
static void udi_msc_spc_testunitready(void) {
if (udi_msc_spc_testunitready_global()) {
// LUN ready, then update sense data with status pass
udi_msc_sense_pass();
@@ -866,9 +812,7 @@ static void udi_msc_spc_testunitready(void)
udi_msc_csw_process();
}
static void udi_msc_spc_mode_sense(bool b_sense10)
{
static void udi_msc_spc_mode_sense(bool b_sense10) {
// Union of all mode sense structures
union sense_6_10 {
struct {
@@ -943,9 +887,7 @@ static void udi_msc_spc_mode_sense(bool b_sense10)
udi_msc_data_send((uint8_t *) & sense, request_lgt);
}
static void udi_msc_spc_prevent_allow_medium_removal(void)
{
static void udi_msc_spc_prevent_allow_medium_removal(void) {
uint8_t prevent = udi_msc_cbw.CDB[4];
if (0 == prevent) {
udi_msc_sense_pass();
@@ -955,9 +897,7 @@ static void udi_msc_spc_prevent_allow_medium_removal(void)
udi_msc_csw_process();
}
static void udi_msc_sbc_start_stop(void)
{
static void udi_msc_sbc_start_stop(void) {
bool start = 0x1 & udi_msc_cbw.CDB[4];
bool loej = 0x2 & udi_msc_cbw.CDB[4];
if (loej) {
@@ -967,9 +907,7 @@ static void udi_msc_sbc_start_stop(void)
udi_msc_csw_process();
}
static void udi_msc_sbc_read_capacity(void)
{
static void udi_msc_sbc_read_capacity(void) {
UDC_BSS(4) static struct sbc_read_capacity10_data udi_msc_capacity;
if (!udi_msc_cbw_validate(sizeof(udi_msc_capacity),
@@ -1003,9 +941,7 @@ static void udi_msc_sbc_read_capacity(void)
sizeof(udi_msc_capacity));
}
static void udi_msc_sbc_trans(bool b_read)
{
static void udi_msc_sbc_trans(bool b_read) {
uint32_t trans_size;
if (!b_read) {
@@ -1038,9 +974,7 @@ static void udi_msc_sbc_trans(bool b_read)
UDI_MSC_NOTIFY_TRANS_EXT();
}
bool udi_msc_process_trans(void)
{
bool udi_msc_process_trans(void) {
Ctrl_status status;
if (!udi_msc_b_trans_req)
@@ -1084,10 +1018,8 @@ bool udi_msc_process_trans(void)
return true;
}
static void udi_msc_trans_ack(udd_ep_status_t status, iram_size_t n,
udd_ep_id_t ep)
{
udd_ep_id_t ep) {
UNUSED(ep);
UNUSED(n);
// Update variable to signal the end of transfer
@@ -1095,10 +1027,8 @@ static void udi_msc_trans_ack(udd_ep_status_t status, iram_size_t n,
udi_msc_b_ack_trans = true;
}
bool udi_msc_trans_block(bool b_read, uint8_t * block, iram_size_t block_size,
void (*callback) (udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep))
{
void (*callback) (udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep)) {
if (!udi_msc_b_ack_trans)
return false; // No possible, transfer on going

View File

@@ -129,7 +129,6 @@ typedef struct {
}
//@}
/**
* \ingroup udi_group
* \defgroup udi_msc_group USB Device Interface (UDI) for Mass Storage Class (MSC)
@@ -170,7 +169,6 @@ bool udi_msc_trans_block(bool b_read, uint8_t * block, iram_size_t block_size,
}
#endif
/**
* \page udi_msc_quickstart Quick start guide for USB device Mass Storage module (UDI MSC)
*
@@ -215,18 +213,15 @@ bool udi_msc_trans_block(bool b_read, uint8_t * block, iram_size_t block_size,
* Add to application C-file:
* \code
static bool my_flag_autorize_msc_transfert = false;
bool my_callback_msc_enable(void)
{
bool my_callback_msc_enable(void) {
my_flag_autorize_msc_transfert = true;
return true;
}
void my_callback_msc_disable(void)
{
void my_callback_msc_disable(void) {
my_flag_autorize_msc_transfert = false;
}
void task(void)
{
void task(void) {
udi_msc_process_trans();
}
\endcode

View File

@@ -276,7 +276,6 @@
# endif
#endif
/**
* \name Power management routine.
*/
@@ -293,7 +292,6 @@ static bool udd_b_idle;
//! State of sleep manager
static bool udd_b_sleep_initialized = false;
/*! \brief Authorize or not the CPU powerdown mode
*
* \param b_enable true to authorize idle mode
@@ -321,7 +319,6 @@ static void udd_sleep_mode(bool b_idle)
//@}
/**
* \name Control endpoint low level management routine.
*
@@ -393,7 +390,6 @@ static void udd_ctrl_send_zlp_out(void);
//! \brief Call callback associated to setup request
static void udd_ctrl_endofrequest(void);
/**
* \brief Main interrupt routine for control endpoint
*
@@ -405,7 +401,6 @@ static bool udd_ctrl_interrupt(void);
//@}
/**
* \name Management of bulk/interrupt/isochronous endpoints
*
@@ -443,7 +438,6 @@ typedef struct {
uint8_t stall_requested:1;
} udd_ep_job_t;
//! Array to register a job on bulk/interrupt/isochronous endpoint
static udd_ep_job_t udd_ep_job[USB_DEVICE_MAX_EP];
@@ -505,7 +499,6 @@ static bool udd_ep_interrupt(void);
#endif // (0!=USB_DEVICE_MAX_EP)
//@}
// ------------------------
//--- INTERNAL ROUTINES TO MANAGED GLOBAL EVENTS
@@ -642,13 +635,11 @@ udd_interrupt_sof_end:
return;
}
bool udd_include_vbus_monitoring(void)
{
return true;
}
void udd_enable(void)
{
irqflags_t flags;
@@ -735,7 +726,6 @@ void udd_enable(void)
cpu_irq_restore(flags);
}
void udd_disable(void)
{
irqflags_t flags;
@@ -776,7 +766,6 @@ void udd_disable(void)
cpu_irq_restore(flags);
}
void udd_attach(void)
{
irqflags_t flags;
@@ -817,7 +806,6 @@ void udd_attach(void)
cpu_irq_restore(flags);
}
void udd_detach(void)
{
otg_unfreeze_clock();
@@ -828,7 +816,6 @@ void udd_detach(void)
udd_sleep_mode(false);
}
bool udd_is_high_speed(void)
{
#ifdef USB_DEVICE_HS_SUPPORT
@@ -838,7 +825,6 @@ bool udd_is_high_speed(void)
#endif
}
void udd_set_address(uint8_t address)
{
udd_disable_address();
@@ -846,13 +832,11 @@ void udd_set_address(uint8_t address)
udd_enable_address();
}
uint8_t udd_getaddress(void)
{
return udd_get_configured_address();
}
uint16_t udd_get_frame_number(void)
{
return udd_frame_number();
@@ -875,14 +859,12 @@ void udd_send_remotewakeup(void)
}
}
void udd_set_setup_payload(uint8_t *payload, uint16_t payload_size)
{
udd_g_ctrlreq.payload = payload;
udd_g_ctrlreq.payload_size = payload_size;
}
#if (0 != USB_DEVICE_MAX_EP)
bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes,
uint16_t MaxEndpointSize)
@@ -1006,7 +988,6 @@ bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes,
return true;
}
void udd_ep_free(udd_ep_id_t ep)
{
uint8_t ep_index = ep & USB_EP_ADDR_MASK;
@@ -1019,14 +1000,12 @@ void udd_ep_free(udd_ep_id_t ep)
udd_ep_job[ep_index - 1].stall_requested = false;
}
bool udd_ep_is_halted(udd_ep_id_t ep)
{
uint8_t ep_index = ep & USB_EP_ADDR_MASK;
return Is_udd_endpoint_stall_requested(ep_index);
}
bool udd_ep_set_halt(udd_ep_id_t ep)
{
uint8_t ep_index = ep & USB_EP_ADDR_MASK;
@@ -1067,7 +1046,6 @@ bool udd_ep_set_halt(udd_ep_id_t ep)
return true;
}
bool udd_ep_clear_halt(udd_ep_id_t ep)
{
uint8_t ep_index = ep & USB_EP_ADDR_MASK;
@@ -1108,7 +1086,6 @@ bool udd_ep_clear_halt(udd_ep_id_t ep)
return true;
}
bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket,
uint8_t * buf, iram_size_t buf_size,
udd_callback_trans_t callback)
@@ -1175,7 +1152,6 @@ bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket,
#endif
}
void udd_ep_abort(udd_ep_id_t ep)
{
uint8_t ep_index = ep & USB_EP_ADDR_MASK;
@@ -1204,7 +1180,6 @@ void udd_ep_abort(udd_ep_id_t ep)
udd_ep_abort_job(ep);
}
bool udd_ep_wait_stall_clear(udd_ep_id_t ep,
udd_callback_halt_cleared_t callback)
{
@@ -1239,7 +1214,6 @@ bool udd_ep_wait_stall_clear(udd_ep_id_t ep,
}
#endif // (0 != USB_DEVICE_MAX_EP)
#ifdef USB_DEVICE_HS_SUPPORT
void udd_test_mode_j(void)
@@ -1248,20 +1222,17 @@ void udd_test_mode_j(void)
udd_enable_hs_test_mode_j();
}
void udd_test_mode_k(void)
{
udd_enable_hs_test_mode();
udd_enable_hs_test_mode_k();
}
void udd_test_mode_se0_nak(void)
{
udd_enable_hs_test_mode();
}
void udd_test_mode_packet(void)
{
uint8_t i;
@@ -1305,8 +1276,6 @@ void udd_test_mode_packet(void)
}
#endif // USB_DEVICE_HS_SUPPORT
// ------------------------
//--- INTERNAL ROUTINES TO MANAGED THE CONTROL ENDPOINT
@@ -1356,7 +1325,6 @@ static void udd_ctrl_init(void)
udd_ep_control_state = UDD_EPCTRL_SETUP;
}
static void udd_ctrl_setup_received(void)
{
irqflags_t flags;
@@ -1418,7 +1386,6 @@ static void udd_ctrl_setup_received(void)
}
}
static void udd_ctrl_in_sent(void)
{
static bool b_shortpacket = false;
@@ -1502,7 +1469,6 @@ static void udd_ctrl_in_sent(void)
cpu_irq_restore(flags);
}
static void udd_ctrl_out_received(void)
{
irqflags_t flags;
@@ -1593,7 +1559,6 @@ static void udd_ctrl_out_received(void)
cpu_irq_restore(flags);
}
static void udd_ctrl_underflow(void)
{
if (Is_udd_out_received(0))
@@ -1610,7 +1575,6 @@ static void udd_ctrl_underflow(void)
}
}
static void udd_ctrl_overflow(void)
{
if (Is_udd_in_send(0))
@@ -1626,7 +1590,6 @@ static void udd_ctrl_overflow(void)
}
}
static void udd_ctrl_stall_data(void)
{
// Stall all packets on IN & OUT control endpoint
@@ -1634,7 +1597,6 @@ static void udd_ctrl_stall_data(void)
udd_enable_stall_handshake(0);
}
static void udd_ctrl_send_zlp_in(void)
{
irqflags_t flags;
@@ -1652,7 +1614,6 @@ static void udd_ctrl_send_zlp_in(void)
cpu_irq_restore(flags);
}
static void udd_ctrl_send_zlp_out(void)
{
irqflags_t flags;
@@ -1668,7 +1629,6 @@ static void udd_ctrl_send_zlp_out(void)
cpu_irq_restore(flags);
}
static void udd_ctrl_endofrequest(void)
{
// If a callback is registered then call it
@@ -1677,7 +1637,6 @@ static void udd_ctrl_endofrequest(void)
}
}
static bool udd_ctrl_interrupt(void)
{
@@ -1728,7 +1687,6 @@ static bool udd_ctrl_interrupt(void)
return false;
}
// ------------------------
//--- INTERNAL ROUTINES TO MANAGED THE BULK/INTERRUPT/ISOCHRONOUS ENDPOINTS
@@ -1743,7 +1701,6 @@ static void udd_ep_job_table_reset(void)
}
}
static void udd_ep_job_table_kill(void)
{
uint8_t i;
@@ -1754,7 +1711,6 @@ static void udd_ep_job_table_kill(void)
}
}
static void udd_ep_abort_job(udd_ep_id_t ep)
{
ep &= USB_EP_ADDR_MASK;
@@ -1763,7 +1719,6 @@ static void udd_ep_abort_job(udd_ep_id_t ep)
udd_ep_finish_job(&udd_ep_job[ep - 1], true, ep);
}
static void udd_ep_finish_job(udd_ep_job_t * ptr_job, bool b_abort, uint8_t ep_num)
{
if (ptr_job->busy == false) {
@@ -1834,7 +1789,6 @@ static void udd_ep_trans_done(udd_ep_id_t ep)
udd_dma_ctrl |= UOTGHS_DEVDMACONTROL_END_BUFFIT |
UOTGHS_DEVDMACONTROL_CHANN_ENB;
// Disable IRQs to have a short sequence
// between read of EOT_STA and DMA enable
flags = cpu_irq_save();

View File

@@ -129,7 +129,6 @@ extern "C" {
#define Is_udd_vbus_transition() (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUSTI))
//! @}
//! @name UOTGHS device attach control
//! These macros manage the UOTGHS Device attach.
//! @{
@@ -141,7 +140,6 @@ extern "C" {
#define Is_udd_detached() (Tst_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_DETACH))
//! @}
//! @name UOTGHS device bus events control
//! These macros manage the UOTGHS Device bus events.
//! @{
@@ -246,7 +244,6 @@ extern "C" {
#define udd_get_configured_address() (Rd_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_UADD_Msk))
//! @}
//! @name UOTGHS Device endpoint drivers
//! These macros manage the common features of the endpoints.
//! @{
@@ -330,7 +327,6 @@ extern "C" {
#define udd_data_toggle(ep) (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_DTSEQ_Msk))
//! @}
//! @name UOTGHS Device control endpoint
//! These macros control the endpoints.
//! @{
@@ -530,7 +526,6 @@ extern "C" {
//! Tests if IN sending interrupt is enabled
#define Is_udd_in_send_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_TXINE))
//! Get 64-, 32-, 16- or 8-bit access to FIFO data register of selected endpoint.
//! @param ep Endpoint of which to access FIFO data register
//! @param scale Data scale in bits: 64, 32, 16 or 8
@@ -652,7 +647,6 @@ typedef struct {
//! @}
//! @}
/// @cond 0
/**INDENT-OFF**/
#ifdef __cplusplus

View File

@@ -53,7 +53,6 @@
extern "C" {
#endif
//! \ingroup usb_group
//! \defgroup otg_group UOTGHS OTG Driver
//! UOTGHS low-level driver for OTG features
@@ -74,7 +73,6 @@ bool otg_dual_enable(void);
*/
void otg_dual_disable(void);
//! @name UOTGHS OTG ID pin management
//! The ID pin come from the USB OTG connector (A and B receptable) and
//! allows to select the USB mode host or device.
@@ -130,8 +128,8 @@ void otg_dual_disable(void);
#define otg_reset() \
do { \
UOTGHS->UOTGHS_CTRL = 0; \
while( UOTGHS->UOTGHS_SR & 0x3FFF) {\
UOTGHS->UOTGHS_SCR = 0xFFFFFFFF;\
while( UOTGHS->UOTGHS_SR & 0x3FFF) { \
UOTGHS->UOTGHS_SCR = 0xFFFFFFFF; \
} \
} while (0)
//! Enable USB macro
@@ -166,7 +164,6 @@ void otg_dual_disable(void);
Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK),\
Rd_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMVALUE_Msk))
//! Get the dual-role device state of the internal USB finite state machine of the UOTGHS controller
#define otg_get_fsm_drd_state() (Rd_bitfield(UOTGHS->UOTGHS_FSM, UOTGHS_FSM_DRDSTATE_Msk))
#define Is_otg_a_suspend() (4==otg_get_fsm_drd_state())

View File

@@ -374,7 +374,6 @@ typedef struct {
uint8_t bNumDeviceCaps;
} usb_dev_bos_desc_t;
/**
* \brief USB Device Capabilities - USB 2.0 Extension Descriptor structure
*
@@ -411,7 +410,6 @@ typedef struct {
uint8_t iFunction; //!< Index of string descriptor
} usb_association_desc_t;
/**
* \brief Standard USB configuration descriptor structure
*/
@@ -426,7 +424,6 @@ typedef struct {
uint8_t bMaxPower;
} usb_conf_desc_t;
#define USB_CONFIG_ATTR_MUST_SET (1 << 7) //!< Must always be set
#define USB_CONFIG_ATTR_BUS_POWERED (0 << 6) //!< Bus-powered
#define USB_CONFIG_ATTR_SELF_POWERED (1 << 6) //!< Self-powered
@@ -475,7 +472,6 @@ typedef struct {
uint8_t bInterval;
} usb_ep_desc_t;
/**
* \brief A standard USB string descriptor structure
*/

View File

@@ -168,7 +168,6 @@ COMPILER_PACK_SET(1)
//! \name USB CDC Descriptors
//@{
//! CDC Header Functional Descriptor
typedef struct {
uint8_t bFunctionLength;
@@ -203,7 +202,6 @@ typedef struct {
uint8_t bSlaveInterface0;
} usb_cdc_union_desc_t;
//! \name USB CDC Call Management Capabilities
//@{
//! Device handles call management itself
@@ -278,7 +276,6 @@ typedef struct {
//@}
//@}
//! \name USB CDC notification message
//@{

View File

@@ -47,7 +47,6 @@
#ifndef _USB_PROTOCOL_MSC_H_
#define _USB_PROTOCOL_MSC_H_
/**
* \ingroup usb_protocol_group
* \defgroup usb_msc_protocol USB Mass Storage Class (MSC) protocol definitions
@@ -89,7 +88,6 @@
#define MSC_PROTOCOL_BULK 0x50 //!< Bulk-only
//@}
/**
* \brief MSC USB requests (bRequest)
*/
@@ -98,7 +96,6 @@ enum usb_reqid_msc {
USB_REQ_MSC_GET_MAX_LUN = 0xFE //!< Get Max LUN
};
COMPILER_PACK_SET(1)
/**
@@ -122,7 +119,6 @@ struct usb_msc_cbw {
#define USB_CBW_LEN_MASK 0x1F //!< Valid bits in bCBWCBLength
//@}
/**
* \name A Command Status Wrapper (CSW).
*/

View File

@@ -1,7 +1,9 @@
/**
* Marlin 3D Printer Firmware
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -4,7 +4,6 @@
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
* Copyright (c) 2017 Victor Perez
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -1,7 +1,9 @@
/**
* Marlin 3D Printer Firmware
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -1,7 +1,9 @@
/**
* Marlin 3D Printer Firmware
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -41,7 +41,6 @@
static SPISettings spiConfig;
#ifndef LCD_SPI_SPEED
#ifdef SD_SPI_SPEED
#define LCD_SPI_SPEED SD_SPI_SPEED // Assume SPI speed shared with SD
@@ -101,6 +100,6 @@ uint8_t u8g_eps_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_pt
return 1;
}
#endif // ANY(MKS_MINI_12864, FYSETC_MINI_12864_2_1)
#endif // MKS_MINI_12864 || FYSETC_MINI_12864_2_1
#endif // ARDUINO_ARCH_ESP32

View File

@@ -19,6 +19,7 @@
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#ifdef __PLAT_LINUX__
#include "../../inc/MarlinConfig.h"

View File

@@ -1,9 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
* Copyright (c) 2015-2016 Nico Tonnhofer wurstnase.reprap@gmail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -60,7 +60,6 @@
#define INVALID_SERVO 255 // flag indicating an invalid servo index
// Types
typedef struct {

View File

@@ -1,9 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
* Copyright (c) 2015-2016 Nico Tonnhofer wurstnase.reprap@gmail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -1,8 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -1,9 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
* Copyright (c) 2015-2016 Nico Tonnhofer wurstnase.reprap@gmail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -318,7 +318,7 @@ void SPIClass::dmaSend(void *buf, uint16_t length, bool minc) {
// Enable DMA
GPDMA_ChannelCmd(0, ENABLE);
/*
/**
* Observed behaviour on normal data transfer completion (SKR 1.3 board / LPC1768 MCU)
* GPDMA_STAT_INTTC flag is SET
* GPDMA_STAT_INTERR flag is NOT SET

View File

@@ -33,7 +33,7 @@ static void TX(char c) { _DBC(c); }
void install_min_serial() { HAL_min_serial_out = &TX; }
#if DISABLED(DYNAMIC_VECTORTABLE)
extern "C" {
extern "C" {
__attribute__((naked)) void JumpHandler_ASM() {
__asm__ __volatile__ (
"b CommonHandler_ASM\n"
@@ -44,7 +44,7 @@ extern "C" {
void __attribute__((naked, alias("JumpHandler_ASM"))) UsageFault_Handler();
void __attribute__((naked, alias("JumpHandler_ASM"))) MemManage_Handler();
void __attribute__((naked, alias("JumpHandler_ASM"))) NMI_Handler();
}
}
#endif
#endif // POSTMORTEM_DEBUGGING

View File

@@ -1,9 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
* Copyright (c) 2015-2016 Nico Tonnhofer wurstnase.reprap@gmail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -1,8 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -34,7 +34,6 @@ uint8_t u8g_com_HAL_LPC1768_ST7920_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t ar
uint8_t u8g_com_HAL_LPC1768_ST7920_sw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr);
uint8_t u8g_com_HAL_LPC1768_ssd_hw_i2c_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr);
// connect U8g com generic com names to the desired driver
#define U8G_COM_HW_SPI u8g_com_HAL_LPC1768_hw_spi_fn // use LPC1768 specific hardware SPI routine
#define U8G_COM_SW_SPI u8g_com_HAL_LPC1768_sw_spi_fn // use LPC1768 specific software SPI routine

View File

@@ -125,5 +125,4 @@ uint8_t u8g_com_HAL_LPC1768_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val,
}
#endif // HAS_MARLINUI_U8GLIB
#endif // TARGET_LPC1768

View File

@@ -194,5 +194,4 @@ uint8_t u8g_com_HAL_LPC1768_ssd_hw_i2c_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_v
}
#endif // HAS_MARLINUI_U8GLIB
#endif // TARGET_LPC1768

View File

@@ -134,5 +134,4 @@ uint8_t u8g_com_HAL_LPC1768_ST7920_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t ar
}
#endif // HAS_MARLINUI_U8GLIB
#endif // TARGET_LPC1768

View File

@@ -8,14 +8,12 @@ DriverVer =04/14/2008, 5.1.2600.5512
[Manufacturer]
%PROVIDER%=DeviceList,ntamd64
[DeviceList]
%DESCRIPTION%=LPC1768USB, USB\VID_1D50&PID_6029&MI_00
[DeviceList.ntamd64]
%DESCRIPTION%=LPC1768USB, USB\VID_1D50&PID_6029&MI_00
[LPC1768USB]
include=mdmcpq.inf
CopyFiles=FakeModemCopyFileSection
@@ -28,7 +26,6 @@ AddService=usbser, 0x00000002, LowerFilter_Service_Inst
[SerialPropPageAddReg]
HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
[Strings]
PROVIDER = "marlinfw.org"
DRIVER.SVC = "Marlin USB Driver"

View File

@@ -1,9 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2021 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
* Copyright (c) 2015-2016 Nico Tonnhofer wurstnase.reprap@gmail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -1,9 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2021 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
* Copyright (c) 2015-2016 Nico Tonnhofer wurstnase.reprap@gmail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -2,6 +2,9 @@
* Marlin 3D Printer Firmware
* Copyright (c) 2021 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or

View File

@@ -61,7 +61,6 @@
#define INVALID_SERVO 255 // flag indicating an invalid servo index
// Types
typedef struct {

View File

@@ -2,6 +2,9 @@
* Marlin 3D Printer Firmware
* Copyright (c) 2021 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or

View File

@@ -1,8 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2021 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -21,6 +21,10 @@
*/
#pragma once
/**
* Native/Simulator LCD-specific defines
*/
void usleep(uint64_t microsec);
// The following are optional depending on the platform.

View File

@@ -31,7 +31,6 @@
* resulted in using about about 25% of the CPU's time.
*/
#ifdef __cplusplus
extern "C" {
#endif

View File

@@ -100,6 +100,7 @@ static void u8g_com_st7920_write_byte_sw_spi(uint8_t rs, uint8_t val) {
swSpiTransfer(val & 0x0F0, SPI_speed, SCK_pin_ST7920_HAL, -1, MOSI_pin_ST7920_HAL_HAL);
swSpiTransfer(val << 4, SPI_speed, SCK_pin_ST7920_HAL, -1, MOSI_pin_ST7920_HAL_HAL);
}
#ifdef __cplusplus
extern "C" {
#endif
@@ -163,6 +164,7 @@ uint8_t u8g_com_ST7920_sw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void
}
return 1;
}
#ifdef __cplusplus
}
#endif

View File

@@ -40,8 +40,6 @@
DefaultSerial3 MSerial2(false, Serial2);
#endif
#define WDT_CONFIG_PER_7_Val 0x9u
#define WDT_CONFIG_PER_Pos 0
#define WDT_CONFIG_PER_7 (WDT_CONFIG_PER_7_Val << WDT_CONFIG_PER_Pos)
@@ -165,7 +163,6 @@ void MarlinHAL::adc_init() {
ADC->REFCTRL.reg = ADC_REFCTRL_REFSEL_INTVCC1;
ADC->AVGCTRL.reg = ADC_AVGCTRL_SAMPLENUM_32| ADC_AVGCTRL_ADJRES(4);;
ADC->CTRLB.reg = ADC_CTRLB_PRESCALER_DIV128 |
ADC_CTRLB_RESSEL_16BIT |
ADC_CTRLB_FREERUN;

View File

@@ -47,7 +47,6 @@ typedef ForwardSerial1Class< decltype(Serial2) > DefaultSerial3;
extern DefaultSerial2 MSerial0;
extern DefaultSerial3 MSerial1;
#define __MSERIAL(X) MSerial##X
#define _MSERIAL(X) __MSERIAL(X)
#define MSERIAL(X) _MSERIAL(INCREMENT(X))

View File

@@ -57,8 +57,6 @@
: (P == 3 && WITHIN(B, 20, 21)) ? 10 + (B) - 20 \
: -1)
#define A2_AIN 3
#define A3_AIN 4
#define A4_AIN 5

View File

@@ -55,7 +55,6 @@
#define TIMER_TCCHANNEL(t) ((t) & 1)
#define TC_COUNTER_START_VAL 0xFFFF
static volatile int8_t currentServoIndex[_Nbr_16timers]; // index for the servo being pulsed for each timer (or -1 if refresh interval)
FORCE_INLINE static uint16_t getTimerCount() {

View File

@@ -99,8 +99,7 @@ bool PersistentStore::access_finish() {
volatile uint32_t *dst_addr = (volatile uint32_t *) &flashdata;
uint32_t *pointer = (uint32_t *) buffer;
for (uint32_t i = 0; i < TOTAL_FLASH_SIZE; i+=4) {
for (uint32_t i = 0; i < TOTAL_FLASH_SIZE; i += 4) {
*dst_addr = (uint32_t) *pointer;
pointer++;
dst_addr ++;
@@ -120,7 +119,7 @@ bool PersistentStore::write_data(int &pos, const uint8_t *value, size_t size, ui
if (!hasWritten) {
// init temp buffer
buffer = (uint8_t *) malloc(MARLIN_EEPROM_SIZE);
hasWritten=true;
hasWritten = true;
}
memcpy(buffer+pos,value,size);
@@ -132,7 +131,7 @@ bool PersistentStore::read_data(int &pos, uint8_t *value, size_t size, uint16_t
volatile uint8_t *dst_addr = (volatile uint8_t *) &flashdata;
dst_addr += pos;
memcpy(value,(const void *) dst_addr,size);
memcpy(value, (const void *)dst_addr, size);
pos += size;
return false;
}

View File

@@ -129,7 +129,7 @@
* Added as necessary or if I feel like it- not a comprehensive list!
*/
/*
/**
* Some of these share the same source and so can't be used in the same time
*/
#define PWM_PIN(P) (WITHIN(P, 2, 13) || WITHIN(P, 22, 23) || WITHIN(P, 44, 45) || P == 48)

View File

@@ -19,5 +19,4 @@
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*
*/
#pragma once

View File

@@ -54,7 +54,6 @@
#define TIMER_TCCHANNEL(t) ((t) & 1)
#define TC_COUNTER_START_VAL 0xFFFF
static volatile int8_t currentServoIndex[_Nbr_16timers]; // index for the servo being pulsed for each timer (or -1 if refresh interval)
FORCE_INLINE static uint16_t getTimerCount() {

View File

@@ -130,7 +130,7 @@
#ifdef ADAFRUIT_GRAND_CENTRAL_M4
/*
/**
* Adafruit Grand Central M4 has a lot of PWMs the availables are listed here.
* Some of these share the same source and so can't be used in the same time
*/
@@ -176,7 +176,7 @@
#define digitalPinToAnalogInput(P) (WITHIN(P, 67, 74) ? (P) - 67 : WITHIN(P, 54, 61) ? 8 + (P) - 54 : WITHIN(P, 12, 13) ? 16 + (P) - 12 : P == 9 ? 18 : -1)
/*
/**
* pins
*/

View File

@@ -27,7 +27,7 @@
#ifdef ADAFRUIT_GRAND_CENTRAL_M4
/*
/**
* AGCM4 Default SPI Pins
*
* SS SCK MISO MOSI

View File

@@ -1,10 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
* Copyright (c) 2015-2016 Nico Tonnhofer wurstnase.reprap@gmail.com
* Copyright (c) 2017 Victor Perez
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -1,10 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
* Copyright (c) 2015-2016 Nico Tonnhofer wurstnase.reprap@gmail.com
* Copyright (c) 2017 Victor Perez
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -4,7 +4,6 @@
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
* Copyright (c) 2017 Victor Perez
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -4,7 +4,6 @@
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
* Copyright (c) 2017 Victor Perez
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -4,7 +4,6 @@
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
* Copyright (c) 2017 Victor Perez
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -4,7 +4,6 @@
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
* Copyright (c) 2017 Victor Perez
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -1,10 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
* Copyright (c) 2015-2016 Nico Tonnhofer wurstnase.reprap@gmail.com
* Copyright (c) 2016 Victor Perez victor_pv@hotmail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -1,10 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
* Copyright (c) 2015-2016 Nico Tonnhofer wurstnase.reprap@gmail.com
* Copyright (c) 2016 Victor Perez victor_pv@hotmail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -1,10 +1,9 @@
/**
* Marlin 3D Printer Firmware
*
* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
* Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
* Copyright (c) 2015-2016 Nico Tonnhofer wurstnase.reprap@gmail.com
* Copyright (c) 2016 Victor Perez victor_pv@hotmail.com
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

View File

@@ -4,7 +4,6 @@
*
* Based on Sprinter and grbl.
* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
* Copyright (c) 2017 Victor Perez
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

Some files were not shown because too many files have changed in this diff Show More