From 6b5e19cfc4157707980debedbdbf9740d6b78f3d Mon Sep 17 00:00:00 2001
From: Chris <52449218+shadow578@users.noreply.github.com>
Date: Wed, 15 May 2024 22:45:52 +0200
Subject: [PATCH] =?UTF-8?q?=F0=9F=90=9B=20Fix=20HC32=20watchdog=20timeout?=
 =?UTF-8?q?=20(#27084)?=
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by reducing PCLK3 clock
---
 Marlin/src/HAL/HC32/sysclock.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Marlin/src/HAL/HC32/sysclock.cpp b/Marlin/src/HAL/HC32/sysclock.cpp
index d205d725cc..cf40ed2f0d 100644
--- a/Marlin/src/HAL/HC32/sysclock.cpp
+++ b/Marlin/src/HAL/HC32/sysclock.cpp
@@ -104,7 +104,7 @@ void core_hook_sysclock_init() {
       .enPclk0Div = ClkSysclkDiv1, // PCLK0 = 200 MHz (Timer6 (not used))
       .enPclk1Div = ClkSysclkDiv4, // PCLK1 = 50 MHz (USART, SPI, I2S, Timer0 (step+temp), TimerA (Servo))
       .enPclk2Div = ClkSysclkDiv4, // PCLK2 = 50 MHz (ADC)
-      .enPclk3Div = ClkSysclkDiv4, // PCLK3 = 50 MHz (I2C, WDT)
+      .enPclk3Div = ClkSysclkDiv8, // PCLK3 = 25 MHz (I2C, WDT)
       .enPclk4Div = ClkSysclkDiv2, // PCLK4 = 100 MHz (ADC ctl)
   };
   sysclock_set_clock_dividers(&sysClkConf);