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🐛 Fix HC32 temperature ADC (#27085)

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This commit is contained in:
Chris
2024-05-15 22:49:40 +02:00
committed by GitHub
parent 6b5e19cfc4
commit 6eedeaedaf
3 changed files with 27 additions and 10 deletions
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2
Marlin/src/HAL/HC32/HAL.h
View File

@@ -142,7 +142,7 @@
// ADC // ADC
// //
#define HAL_ADC_VREF_MV 3300 #define HAL_ADC_VREF_MV 3300
#define HAL_ADC_RESOLUTION 10 #define HAL_ADC_RESOLUTION 12
#define GET_PIN_MAP_PIN(index) index #define GET_PIN_MAP_PIN(index) index
#define GET_PIN_MAP_INDEX(pin) pin #define GET_PIN_MAP_INDEX(pin) pin

4
Marlin/src/HAL/HC32/MarlinHAL.cpp
View File

@@ -232,7 +232,9 @@ int MarlinHAL::freeMemory() {
return &top - _sbrk(0); return &top - _sbrk(0);
} }
void MarlinHAL::adc_init() {} void MarlinHAL::adc_init() {
analogReadResolution(HAL_ADC_RESOLUTION);
}
void MarlinHAL::adc_enable(const pin_t pin) { void MarlinHAL::adc_enable(const pin_t pin) {
#if TEMP_SENSOR_SOC #if TEMP_SENSOR_SOC

31
Marlin/src/HAL/HC32/sysclock.cpp
View File

@@ -96,29 +96,44 @@ void core_hook_sysclock_init() {
#endif #endif
#endif #endif
// Setup clock divisors for sysclk = 200 MHz: // sysclk is now configured to 200 MHz PLL output
constexpr uint32_t sysclock = 200000000;
// Setup clock divisors for sysclk = 200 MHz
// Note: PCLK1 is used for step+temp timers, and need to be kept at 50 MHz (until there is a better solution) // Note: PCLK1 is used for step+temp timers, and need to be kept at 50 MHz (until there is a better solution)
stc_clk_sysclk_cfg_t sysClkConf = { constexpr stc_clk_sysclk_cfg_t sysClkConf = {
.enHclkDiv = ClkSysclkDiv1, // HCLK = 200 MHz (CPU) .enHclkDiv = ClkSysclkDiv1, // HCLK = 200 MHz (CPU)
.enExclkDiv = ClkSysclkDiv2, // EXCLK = 100 MHz (SDIO) .enExclkDiv = ClkSysclkDiv2, // EXCLK = 100 MHz (SDIO)
.enPclk0Div = ClkSysclkDiv1, // PCLK0 = 200 MHz (Timer6 (not used)) .enPclk0Div = ClkSysclkDiv2, // PCLK0 = 100 MHz (Timer6 (not used))
.enPclk1Div = ClkSysclkDiv4, // PCLK1 = 50 MHz (USART, SPI, I2S, Timer0 (step+temp), TimerA (Servo)) .enPclk1Div = ClkSysclkDiv4, // PCLK1 = 50 MHz (USART, SPI, I2S, Timer0 (step+temp), TimerA (Servo))
.enPclk2Div = ClkSysclkDiv4, // PCLK2 = 50 MHz (ADC) .enPclk2Div = ClkSysclkDiv8, // PCLK2 = 25 MHz (ADC)
.enPclk3Div = ClkSysclkDiv8, // PCLK3 = 25 MHz (I2C, WDT) .enPclk3Div = ClkSysclkDiv8, // PCLK3 = 25 MHz (I2C, WDT)
.enPclk4Div = ClkSysclkDiv2, // PCLK4 = 100 MHz (ADC ctl) .enPclk4Div = ClkSysclkDiv2, // PCLK4 = 100 MHz (ADC ctl)
}; };
#if ARDUINO_CORE_VERSION_INT >= GET_VERSION_INT(1, 2, 0)
assert_system_clocks_valid<
sysclock,
sysClkConf.enHclkDiv,
sysClkConf.enPclk0Div,
sysClkConf.enPclk1Div,
sysClkConf.enPclk2Div,
sysClkConf.enPclk3Div,
sysClkConf.enPclk4Div,
sysClkConf.enExclkDiv
>();
#endif
sysclock_set_clock_dividers(&sysClkConf); sysclock_set_clock_dividers(&sysClkConf);
// Set power mode // Set power mode
#define POWER_MODE_SYSTEM_CLOCK 200000000 // 200 MHz power_mode_update_pre(sysclock);
power_mode_update_pre(POWER_MODE_SYSTEM_CLOCK);
// Switch to MPLL as sysclk source // Switch to MPLL as sysclk source
CLK_SetSysClkSource(CLKSysSrcMPLL); CLK_SetSysClkSource(CLKSysSrcMPLL);
// Set power mode // Set power mode
power_mode_update_post(POWER_MODE_SYSTEM_CLOCK); power_mode_update_post(sysclock);
#undef POWER_MODE_SYSTEM_CLOCK
} }
#endif // ARDUINO_ARCH_HC32 #endif // ARDUINO_ARCH_HC32