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This commit is contained in:
Scott Lahteine
2023-06-05 00:43:31 -05:00
parent 3b681f7b74
commit 70288c6c4f
19 changed files with 1415 additions and 1554 deletions
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38
Marlin/src/HAL/DUE/usb/genclk.h
View File

@@ -108,31 +108,23 @@ struct genclk_config {
uint32_t ctrl; uint32_t ctrl;
}; };
static inline void genclk_config_defaults(struct genclk_config *p_cfg, static inline void genclk_config_defaults(struct genclk_config *p_cfg, uint32_t ul_id) {
uint32_t ul_id)
{
ul_id = ul_id; ul_id = ul_id;
p_cfg->ctrl = 0; p_cfg->ctrl = 0;
} }
static inline void genclk_config_read(struct genclk_config *p_cfg, static inline void genclk_config_read(struct genclk_config *p_cfg, uint32_t ul_id) {
uint32_t ul_id)
{
p_cfg->ctrl = PMC->PMC_PCK[ul_id]; p_cfg->ctrl = PMC->PMC_PCK[ul_id];
} }
static inline void genclk_config_write(const struct genclk_config *p_cfg, static inline void genclk_config_write(const struct genclk_config *p_cfg, uint32_t ul_id) {
uint32_t ul_id)
{
PMC->PMC_PCK[ul_id] = p_cfg->ctrl; PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
} }
//! \name Programmable Clock Source and Prescaler configuration //! \name Programmable Clock Source and Prescaler configuration
//@{ //@{
static inline void genclk_config_set_source(struct genclk_config *p_cfg, static inline void genclk_config_set_source(struct genclk_config *p_cfg, enum genclk_source e_src) {
enum genclk_source e_src)
{
p_cfg->ctrl &= (~PMC_PCK_CSS_Msk); p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);
switch (e_src) { switch (e_src) {
@@ -164,29 +156,23 @@ static inline void genclk_config_set_source(struct genclk_config *p_cfg,
} }
} }
static inline void genclk_config_set_divider(struct genclk_config *p_cfg, static inline void genclk_config_set_divider(struct genclk_config *p_cfg, uint32_t e_divider) {
uint32_t e_divider)
{
p_cfg->ctrl &= ~PMC_PCK_PRES_Msk; p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;
p_cfg->ctrl |= e_divider; p_cfg->ctrl |= e_divider;
} }
//@} //@}
static inline void genclk_enable(const struct genclk_config *p_cfg, static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id) {
uint32_t ul_id)
{
PMC->PMC_PCK[ul_id] = p_cfg->ctrl; PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
pmc_enable_pck(ul_id); pmc_enable_pck(ul_id);
} }
static inline void genclk_disable(uint32_t ul_id) static inline void genclk_disable(uint32_t ul_id) {
{
pmc_disable_pck(ul_id); pmc_disable_pck(ul_id);
} }
static inline void genclk_enable_source(enum genclk_source e_src) static inline void genclk_enable_source(enum genclk_source e_src) {
{
switch (e_src) { switch (e_src) {
case GENCLK_PCK_SRC_SLCK_RC: case GENCLK_PCK_SRC_SLCK_RC:
if (!osc_is_ready(OSC_SLCK_32K_RC)) { if (!osc_is_ready(OSC_SLCK_32K_RC)) {
@@ -244,17 +230,17 @@ static inline void genclk_enable_source(enum genclk_source e_src)
} }
break; break;
#ifdef CONFIG_PLL0_SOURCE #ifdef CONFIG_PLL0_SOURCE
case GENCLK_PCK_SRC_PLLACK: case GENCLK_PCK_SRC_PLLACK:
pll_enable_config_defaults(0); pll_enable_config_defaults(0);
break; break;
#endif #endif
#ifdef CONFIG_PLL1_SOURCE #ifdef CONFIG_PLL1_SOURCE
case GENCLK_PCK_SRC_PLLBCK: case GENCLK_PCK_SRC_PLLBCK:
pll_enable_config_defaults(1); pll_enable_config_defaults(1);
break; break;
#endif #endif
case GENCLK_PCK_SRC_MCK: case GENCLK_PCK_SRC_MCK:
break; break;

35
Marlin/src/HAL/DUE/usb/osc.h
View File

@@ -62,28 +62,28 @@ extern "C" {
* should be defined by the board code, otherwise default value are used. * should be defined by the board code, otherwise default value are used.
*/ */
#ifndef BOARD_FREQ_SLCK_XTAL #ifndef BOARD_FREQ_SLCK_XTAL
# warning The board slow clock xtal frequency has not been defined. #warning The board slow clock xtal frequency has not been defined.
# define BOARD_FREQ_SLCK_XTAL (32768UL) #define BOARD_FREQ_SLCK_XTAL (32768UL)
#endif #endif
#ifndef BOARD_FREQ_SLCK_BYPASS #ifndef BOARD_FREQ_SLCK_BYPASS
# warning The board slow clock bypass frequency has not been defined. #warning The board slow clock bypass frequency has not been defined.
# define BOARD_FREQ_SLCK_BYPASS (32768UL) #define BOARD_FREQ_SLCK_BYPASS (32768UL)
#endif #endif
#ifndef BOARD_FREQ_MAINCK_XTAL #ifndef BOARD_FREQ_MAINCK_XTAL
# warning The board main clock xtal frequency has not been defined. #warning The board main clock xtal frequency has not been defined.
# define BOARD_FREQ_MAINCK_XTAL (12000000UL) #define BOARD_FREQ_MAINCK_XTAL (12000000UL)
#endif #endif
#ifndef BOARD_FREQ_MAINCK_BYPASS #ifndef BOARD_FREQ_MAINCK_BYPASS
# warning The board main clock bypass frequency has not been defined. #warning The board main clock bypass frequency has not been defined.
# define BOARD_FREQ_MAINCK_BYPASS (12000000UL) #define BOARD_FREQ_MAINCK_BYPASS (12000000UL)
#endif #endif
#ifndef BOARD_OSC_STARTUP_US #ifndef BOARD_OSC_STARTUP_US
# warning The board main clock xtal startup time has not been defined. #warning The board main clock xtal startup time has not been defined.
# define BOARD_OSC_STARTUP_US (15625UL) #define BOARD_OSC_STARTUP_US (15625UL)
#endif #endif
/** /**
@@ -115,8 +115,7 @@ extern "C" {
#define OSC_MAINCK_BYPASS_HZ BOARD_FREQ_MAINCK_BYPASS //!< External bypass oscillator. #define OSC_MAINCK_BYPASS_HZ BOARD_FREQ_MAINCK_BYPASS //!< External bypass oscillator.
//@} //@}
static inline void osc_enable(uint32_t ul_id) static inline void osc_enable(uint32_t ul_id) {
{
switch (ul_id) { switch (ul_id) {
case OSC_SLCK_32K_RC: case OSC_SLCK_32K_RC:
break; break;
@@ -157,8 +156,7 @@ static inline void osc_enable(uint32_t ul_id)
} }
} }
static inline void osc_disable(uint32_t ul_id) static inline void osc_disable(uint32_t ul_id) {
{
switch (ul_id) { switch (ul_id) {
case OSC_SLCK_32K_RC: case OSC_SLCK_32K_RC:
case OSC_SLCK_32K_XTAL: case OSC_SLCK_32K_XTAL:
@@ -181,8 +179,7 @@ static inline void osc_disable(uint32_t ul_id)
} }
} }
static inline bool osc_is_ready(uint32_t ul_id) static inline bool osc_is_ready(uint32_t ul_id) {
{
switch (ul_id) { switch (ul_id) {
case OSC_SLCK_32K_RC: case OSC_SLCK_32K_RC:
return 1; return 1;
@@ -202,8 +199,7 @@ static inline bool osc_is_ready(uint32_t ul_id)
return 0; return 0;
} }
static inline uint32_t osc_get_rate(uint32_t ul_id) static inline uint32_t osc_get_rate(uint32_t ul_id) {
{
switch (ul_id) { switch (ul_id) {
case OSC_SLCK_32K_RC: case OSC_SLCK_32K_RC:
return OSC_SLCK_32K_RC_HZ; return OSC_SLCK_32K_RC_HZ;
@@ -241,8 +237,7 @@ static inline uint32_t osc_get_rate(uint32_t ul_id)
* *
* \param id A number identifying the oscillator to wait for. * \param id A number identifying the oscillator to wait for.
*/ */
static inline void osc_wait_ready(uint8_t id) static inline void osc_wait_ready(uint8_t id) {
{
while (!osc_is_ready(id)) { while (!osc_is_ready(id)) {
/* Do nothing */ /* Do nothing */
} }

72
Marlin/src/HAL/DUE/usb/pll.h
View File

@@ -113,15 +113,15 @@ struct pll_config {
* is hidden in this implementation. Use mul as mul effective value. * is hidden in this implementation. Use mul as mul effective value.
*/ */
static inline void pll_config_init(struct pll_config *p_cfg, static inline void pll_config_init(struct pll_config *p_cfg,
enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul) enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul) {
{
uint32_t vco_hz; uint32_t vco_hz;
Assert(e_src < PLL_NR_SOURCES); Assert(e_src < PLL_NR_SOURCES);
if (ul_div == 0 && ul_mul == 0) { /* Must only be true for UTMI PLL */ if (ul_div == 0 && ul_mul == 0) { /* Must only be true for UTMI PLL */
p_cfg->ctrl = CKGR_UCKR_UPLLCOUNT(PLL_COUNT); p_cfg->ctrl = CKGR_UCKR_UPLLCOUNT(PLL_COUNT);
} else { /* PLLA */ }
else { /* PLLA */
/* Calculate internal VCO frequency */ /* Calculate internal VCO frequency */
vco_hz = osc_get_rate(e_src) / ul_div; vco_hz = osc_get_rate(e_src) / ul_div;
Assert(vco_hz >= PLL_INPUT_MIN_HZ); Assert(vco_hz >= PLL_INPUT_MIN_HZ);
@@ -142,68 +142,55 @@ static inline void pll_config_init(struct pll_config *p_cfg,
CONFIG_PLL##pll_id##_DIV, \ CONFIG_PLL##pll_id##_DIV, \
CONFIG_PLL##pll_id##_MUL) CONFIG_PLL##pll_id##_MUL)
static inline void pll_config_read(struct pll_config *p_cfg, uint32_t ul_pll_id) static inline void pll_config_read(struct pll_config *p_cfg, uint32_t ul_pll_id) {
{
Assert(ul_pll_id < NR_PLLS); Assert(ul_pll_id < NR_PLLS);
p_cfg->ctrl = ul_pll_id == PLLA_ID ? PMC->CKGR_PLLAR : PMC->CKGR_UCKR;
if (ul_pll_id == PLLA_ID) {
p_cfg->ctrl = PMC->CKGR_PLLAR;
} else {
p_cfg->ctrl = PMC->CKGR_UCKR;
}
} }
static inline void pll_config_write(const struct pll_config *p_cfg, uint32_t ul_pll_id) static inline void pll_config_write(const struct pll_config *p_cfg, uint32_t ul_pll_id) {
{
Assert(ul_pll_id < NR_PLLS); Assert(ul_pll_id < NR_PLLS);
if (ul_pll_id == PLLA_ID) { if (ul_pll_id == PLLA_ID) {
pmc_disable_pllack(); // Always stop PLL first! pmc_disable_pllack(); // Always stop PLL first!
PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl; PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;
} else { }
else
PMC->CKGR_UCKR = p_cfg->ctrl; PMC->CKGR_UCKR = p_cfg->ctrl;
}
} }
static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id) static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id) {
{
Assert(ul_pll_id < NR_PLLS); Assert(ul_pll_id < NR_PLLS);
if (ul_pll_id == PLLA_ID) { if (ul_pll_id == PLLA_ID) {
pmc_disable_pllack(); // Always stop PLL first! pmc_disable_pllack(); // Always stop PLL first!
PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl; PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;
} else {
PMC->CKGR_UCKR = p_cfg->ctrl | CKGR_UCKR_UPLLEN;
} }
else
PMC->CKGR_UCKR = p_cfg->ctrl | CKGR_UCKR_UPLLEN;
} }
/** /**
* \note This will only disable the selected PLL, not the underlying oscillator (mainck). * \note This will only disable the selected PLL, not the underlying oscillator (mainck).
*/ */
static inline void pll_disable(uint32_t ul_pll_id) static inline void pll_disable(uint32_t ul_pll_id) {
{
Assert(ul_pll_id < NR_PLLS); Assert(ul_pll_id < NR_PLLS);
if (ul_pll_id == PLLA_ID) { if (ul_pll_id == PLLA_ID)
pmc_disable_pllack(); pmc_disable_pllack();
} else { else
PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN; PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;
}
} }
static inline uint32_t pll_is_locked(uint32_t ul_pll_id) static inline uint32_t pll_is_locked(uint32_t ul_pll_id) {
{
Assert(ul_pll_id < NR_PLLS); Assert(ul_pll_id < NR_PLLS);
if (ul_pll_id == PLLA_ID) { if (ul_pll_id == PLLA_ID)
return pmc_is_locked_pllack(); return pmc_is_locked_pllack();
} else { else
return pmc_is_locked_upll(); return pmc_is_locked_upll();
}
} }
static inline void pll_enable_source(enum pll_source e_src) static inline void pll_enable_source(enum pll_source e_src) {
{
switch (e_src) { switch (e_src) {
case PLL_SRC_MAINCK_4M_RC: case PLL_SRC_MAINCK_4M_RC:
case PLL_SRC_MAINCK_8M_RC: case PLL_SRC_MAINCK_8M_RC:
@@ -220,15 +207,13 @@ static inline void pll_enable_source(enum pll_source e_src)
} }
} }
static inline void pll_enable_config_defaults(unsigned int ul_pll_id) static inline void pll_enable_config_defaults(unsigned int ul_pll_id) {
{
struct pll_config pllcfg; struct pll_config pllcfg;
if (pll_is_locked(ul_pll_id)) { if (pll_is_locked(ul_pll_id)) return; // Pll already running
return; // Pll already running
}
switch (ul_pll_id) { switch (ul_pll_id) {
#ifdef CONFIG_PLL0_SOURCE #ifdef CONFIG_PLL0_SOURCE
case 0: case 0:
pll_enable_source(CONFIG_PLL0_SOURCE); pll_enable_source(CONFIG_PLL0_SOURCE);
pll_config_init(&pllcfg, pll_config_init(&pllcfg,
@@ -236,8 +221,8 @@ static inline void pll_enable_config_defaults(unsigned int ul_pll_id)
CONFIG_PLL0_DIV, CONFIG_PLL0_DIV,
CONFIG_PLL0_MUL); CONFIG_PLL0_MUL);
break; break;
#endif #endif
#ifdef CONFIG_PLL1_SOURCE #ifdef CONFIG_PLL1_SOURCE
case 1: case 1:
pll_enable_source(CONFIG_PLL1_SOURCE); pll_enable_source(CONFIG_PLL1_SOURCE);
pll_config_init(&pllcfg, pll_config_init(&pllcfg,
@@ -245,7 +230,7 @@ static inline void pll_enable_config_defaults(unsigned int ul_pll_id)
CONFIG_PLL1_DIV, CONFIG_PLL1_DIV,
CONFIG_PLL1_MUL); CONFIG_PLL1_MUL);
break; break;
#endif #endif
default: default:
Assert(false); Assert(false);
break; break;
@@ -264,13 +249,10 @@ static inline void pll_enable_config_defaults(unsigned int ul_pll_id)
* \retval STATUS_OK The PLL is now locked. * \retval STATUS_OK The PLL is now locked.
* \retval ERR_TIMEOUT Timed out waiting for PLL to become locked. * \retval ERR_TIMEOUT Timed out waiting for PLL to become locked.
*/ */
static inline int pll_wait_for_lock(unsigned int pll_id) static inline int pll_wait_for_lock(unsigned int pll_id) {
{
Assert(pll_id < NR_PLLS); Assert(pll_id < NR_PLLS);
while (!pll_is_locked(pll_id)) { while (!pll_is_locked(pll_id)) { /* Do nothing */ }
/* Do nothing */
}
return 0; return 0;
} }

19
Marlin/src/HAL/DUE/usb/sbc_protocol.h
View File

@@ -57,7 +57,6 @@
#ifndef _SBC_PROTOCOL_H_ #ifndef _SBC_PROTOCOL_H_
#define _SBC_PROTOCOL_H_ #define _SBC_PROTOCOL_H_
/** /**
* \ingroup usb_msc_protocol * \ingroup usb_msc_protocol
* \defgroup usb_sbc_protocol SCSI Block Commands protocol definitions * \defgroup usb_sbc_protocol SCSI Block Commands protocol definitions
@@ -139,16 +138,16 @@ struct sbc_caching_mode_page {
struct sbc_rdwr_error_recovery_mode_page { struct sbc_rdwr_error_recovery_mode_page {
uint8_t page_code; uint8_t page_code;
uint8_t page_length; uint8_t page_length;
#define SPC_MP_RW_ERR_RECOV_PAGE_LENGTH 0x0A #define SPC_MP_RW_ERR_RECOV_PAGE_LENGTH 0x0A
uint8_t flags1; uint8_t flags1;
#define SBC_MP_RW_ERR_RECOV_AWRE (1 << 7) #define SBC_MP_RW_ERR_RECOV_AWRE (1 << 7)
#define SBC_MP_RW_ERR_RECOV_ARRE (1 << 6) #define SBC_MP_RW_ERR_RECOV_ARRE (1 << 6)
#define SBC_MP_RW_ERR_RECOV_TB (1 << 5) #define SBC_MP_RW_ERR_RECOV_TB (1 << 5)
#define SBC_MP_RW_ERR_RECOV_RC (1 << 4) #define SBC_MP_RW_ERR_RECOV_RC (1 << 4)
#define SBC_MP_RW_ERR_RECOV_ERR (1 << 3) #define SBC_MP_RW_ERR_RECOV_ERR (1 << 3)
#define SBC_MP_RW_ERR_RECOV_PER (1 << 2) #define SBC_MP_RW_ERR_RECOV_PER (1 << 2)
#define SBC_MP_RW_ERR_RECOV_DTE (1 << 1) #define SBC_MP_RW_ERR_RECOV_DTE (1 << 1)
#define SBC_MP_RW_ERR_RECOV_DCR (1 << 0) #define SBC_MP_RW_ERR_RECOV_DCR (1 << 0)
uint8_t read_retry_count; uint8_t read_retry_count;
uint8_t correction_span; uint8_t correction_span;
uint8_t head_offset_count; uint8_t head_offset_count;

139
Marlin/src/HAL/DUE/usb/spc_protocol.h
View File

@@ -85,51 +85,51 @@ COMPILER_PACK_SET(1)
*/ */
struct scsi_inquiry_data { struct scsi_inquiry_data {
uint8_t pq_pdt; //!< Peripheral Qual / Peripheral Dev Type uint8_t pq_pdt; //!< Peripheral Qual / Peripheral Dev Type
#define SCSI_INQ_PQ_CONNECTED 0x00 //!< Peripheral connected #define SCSI_INQ_PQ_CONNECTED 0x00 //!< Peripheral connected
#define SCSI_INQ_PQ_NOT_CONN 0x20 //!< Peripheral not connected #define SCSI_INQ_PQ_NOT_CONN 0x20 //!< Peripheral not connected
#define SCSI_INQ_PQ_NOT_SUPP 0x60 //!< Peripheral not supported #define SCSI_INQ_PQ_NOT_SUPP 0x60 //!< Peripheral not supported
#define SCSI_INQ_DT_DIR_ACCESS 0x00 //!< Direct Access (SBC) #define SCSI_INQ_DT_DIR_ACCESS 0x00 //!< Direct Access (SBC)
#define SCSI_INQ_DT_SEQ_ACCESS 0x01 //!< Sequential Access #define SCSI_INQ_DT_SEQ_ACCESS 0x01 //!< Sequential Access
#define SCSI_INQ_DT_PRINTER 0x02 //!< Printer #define SCSI_INQ_DT_PRINTER 0x02 //!< Printer
#define SCSI_INQ_DT_PROCESSOR 0x03 //!< Processor device #define SCSI_INQ_DT_PROCESSOR 0x03 //!< Processor device
#define SCSI_INQ_DT_WRITE_ONCE 0x04 //!< Write-once device #define SCSI_INQ_DT_WRITE_ONCE 0x04 //!< Write-once device
#define SCSI_INQ_DT_CD_DVD 0x05 //!< CD/DVD device #define SCSI_INQ_DT_CD_DVD 0x05 //!< CD/DVD device
#define SCSI_INQ_DT_OPTICAL 0x07 //!< Optical Memory #define SCSI_INQ_DT_OPTICAL 0x07 //!< Optical Memory
#define SCSI_INQ_DT_MC 0x08 //!< Medium Changer #define SCSI_INQ_DT_MC 0x08 //!< Medium Changer
#define SCSI_INQ_DT_ARRAY 0x0C //!< Storage Array Controller #define SCSI_INQ_DT_ARRAY 0x0C //!< Storage Array Controller
#define SCSI_INQ_DT_ENCLOSURE 0x0D //!< Enclosure Services #define SCSI_INQ_DT_ENCLOSURE 0x0D //!< Enclosure Services
#define SCSI_INQ_DT_RBC 0x0E //!< Simplified Direct Access #define SCSI_INQ_DT_RBC 0x0E //!< Simplified Direct Access
#define SCSI_INQ_DT_OCRW 0x0F //!< Optical card reader/writer #define SCSI_INQ_DT_OCRW 0x0F //!< Optical card reader/writer
#define SCSI_INQ_DT_BCC 0x10 //!< Bridge Controller Commands #define SCSI_INQ_DT_BCC 0x10 //!< Bridge Controller Commands
#define SCSI_INQ_DT_OSD 0x11 //!< Object-based Storage #define SCSI_INQ_DT_OSD 0x11 //!< Object-based Storage
#define SCSI_INQ_DT_NONE 0x1F //!< No Peripheral #define SCSI_INQ_DT_NONE 0x1F //!< No Peripheral
uint8_t flags1; //!< Flags (byte 1) uint8_t flags1; //!< Flags (byte 1)
#define SCSI_INQ_RMB 0x80 //!< Removable Medium #define SCSI_INQ_RMB 0x80 //!< Removable Medium
uint8_t version; //!< Version uint8_t version; //!< Version
#define SCSI_INQ_VER_NONE 0x00 //!< No standards conformance #define SCSI_INQ_VER_NONE 0x00 //!< No standards conformance
#define SCSI_INQ_VER_SPC 0x03 //!< SCSI Primary Commands (link to SBC) #define SCSI_INQ_VER_SPC 0x03 //!< SCSI Primary Commands (link to SBC)
#define SCSI_INQ_VER_SPC2 0x04 //!< SCSI Primary Commands - 2 (link to SBC-2) #define SCSI_INQ_VER_SPC2 0x04 //!< SCSI Primary Commands - 2 (link to SBC-2)
#define SCSI_INQ_VER_SPC3 0x05 //!< SCSI Primary Commands - 3 (link to SBC-2) #define SCSI_INQ_VER_SPC3 0x05 //!< SCSI Primary Commands - 3 (link to SBC-2)
#define SCSI_INQ_VER_SPC4 0x06 //!< SCSI Primary Commands - 4 (link to SBC-3) #define SCSI_INQ_VER_SPC4 0x06 //!< SCSI Primary Commands - 4 (link to SBC-3)
uint8_t flags3; //!< Flags (byte 3) uint8_t flags3; //!< Flags (byte 3)
#define SCSI_INQ_NORMACA 0x20 //!< Normal ACA Supported #define SCSI_INQ_NORMACA 0x20 //!< Normal ACA Supported
#define SCSI_INQ_HISUP 0x10 //!< Hierarchal LUN addressing #define SCSI_INQ_HISUP 0x10 //!< Hierarchal LUN addressing
#define SCSI_INQ_RSP_SPC2 0x02 //!< SPC-2 / SPC-3 response format #define SCSI_INQ_RSP_SPC2 0x02 //!< SPC-2 / SPC-3 response format
uint8_t addl_len; //!< Additional Length (n-4) uint8_t addl_len; //!< Additional Length (n-4)
#define SCSI_INQ_ADDL_LEN(tot) ((tot)-5) //!< Total length is \a tot #define SCSI_INQ_ADDL_LEN(tot) ((tot)-5) //!< Total length is \a tot
uint8_t flags5; //!< Flags (byte 5) uint8_t flags5; //!< Flags (byte 5)
#define SCSI_INQ_SCCS 0x80 #define SCSI_INQ_SCCS 0x80
uint8_t flags6; //!< Flags (byte 6) uint8_t flags6; //!< Flags (byte 6)
#define SCSI_INQ_BQUE 0x80 #define SCSI_INQ_BQUE 0x80
#define SCSI_INQ_ENCSERV 0x40 #define SCSI_INQ_ENCSERV 0x40
#define SCSI_INQ_MULTIP 0x10 #define SCSI_INQ_MULTIP 0x10
#define SCSI_INQ_MCHGR 0x08 #define SCSI_INQ_MCHGR 0x08
#define SCSI_INQ_ADDR16 0x01 #define SCSI_INQ_ADDR16 0x01
uint8_t flags7; //!< Flags (byte 7) uint8_t flags7; //!< Flags (byte 7)
#define SCSI_INQ_WBUS16 0x20 #define SCSI_INQ_WBUS16 0x20
#define SCSI_INQ_SYNC 0x10 #define SCSI_INQ_SYNC 0x10
#define SCSI_INQ_LINKED 0x08 #define SCSI_INQ_LINKED 0x08
#define SCSI_INQ_CMDQUE 0x02 #define SCSI_INQ_CMDQUE 0x02
uint8_t vendor_id[8]; //!< T10 Vendor Identification uint8_t vendor_id[8]; //!< T10 Vendor Identification
uint8_t product_id[16]; //!< Product Identification uint8_t product_id[16]; //!< Product Identification
uint8_t product_rev[4]; //!< Product Revision Level uint8_t product_rev[4]; //!< Product Revision Level
@@ -141,28 +141,28 @@ struct scsi_inquiry_data {
struct scsi_request_sense_data { struct scsi_request_sense_data {
/* 1st byte: REQUEST SENSE response flags*/ /* 1st byte: REQUEST SENSE response flags*/
uint8_t valid_reponse_code; uint8_t valid_reponse_code;
#define SCSI_SENSE_VALID 0x80 //!< Indicates the INFORMATION field contains valid information #define SCSI_SENSE_VALID 0x80 //!< Indicates the INFORMATION field contains valid information
#define SCSI_SENSE_RESPONSE_CODE_MASK 0x7F #define SCSI_SENSE_RESPONSE_CODE_MASK 0x7F
#define SCSI_SENSE_CURRENT 0x70 //!< Response code 70h (current errors) #define SCSI_SENSE_CURRENT 0x70 //!< Response code 70h (current errors)
#define SCSI_SENSE_DEFERRED 0x71 #define SCSI_SENSE_DEFERRED 0x71
/* 2nd byte */ /* 2nd byte */
uint8_t obsolete; uint8_t obsolete;
/* 3rd byte */ /* 3rd byte */
uint8_t sense_flag_key; uint8_t sense_flag_key;
#define SCSI_SENSE_FILEMARK 0x80 //!< Indicates that the current command has read a filemark or setmark. #define SCSI_SENSE_FILEMARK 0x80 //!< Indicates that the current command has read a filemark or setmark.
#define SCSI_SENSE_EOM 0x40 //!< Indicates that an end-of-medium condition exists. #define SCSI_SENSE_EOM 0x40 //!< Indicates that an end-of-medium condition exists.
#define SCSI_SENSE_ILI 0x20 //!< Indicates that the requested logical block length did not match the logical block length of the data on the medium. #define SCSI_SENSE_ILI 0x20 //!< Indicates that the requested logical block length did not match the logical block length of the data on the medium.
#define SCSI_SENSE_RESERVED 0x10 //!< Reserved #define SCSI_SENSE_RESERVED 0x10 //!< Reserved
#define SCSI_SENSE_KEY(x) (x&0x0F) //!< Sense Key #define SCSI_SENSE_KEY(x) (x&0x0F) //!< Sense Key
/* 4th to 7th bytes - INFORMATION field */ /* 4th to 7th bytes - INFORMATION field */
uint8_t information[4]; uint8_t information[4];
/* 8th byte - ADDITIONAL SENSE LENGTH field */ /* 8th byte - ADDITIONAL SENSE LENGTH field */
uint8_t AddSenseLen; uint8_t AddSenseLen;
#define SCSI_SENSE_ADDL_LEN(total_len) ((total_len) - 8) #define SCSI_SENSE_ADDL_LEN(total_len) ((total_len) - 8)
/* 9th to 12th byte - COMMAND-SPECIFIC INFORMATION field */ /* 9th to 12th byte - COMMAND-SPECIFIC INFORMATION field */
uint8_t CmdSpecINFO[4]; uint8_t CmdSpecINFO[4];
@@ -178,7 +178,7 @@ struct scsi_request_sense_data {
/* 16th byte */ /* 16th byte */
uint8_t SenseKeySpec[3]; uint8_t SenseKeySpec[3];
#define SCSI_SENSE_SKSV 0x80 //!< Indicates the SENSE-KEY SPECIFIC field contains valid information #define SCSI_SENSE_SKSV 0x80 //!< Indicates the SENSE-KEY SPECIFIC field contains valid information
}; };
COMPILER_PACK_RESET() COMPILER_PACK_RESET()
@@ -200,7 +200,6 @@ enum scsi_vpd_page_code {
#define SCSI_VPD_ID_TYPE_T10 1 #define SCSI_VPD_ID_TYPE_T10 1
/* Sense keys */ /* Sense keys */
enum scsi_sense_key { enum scsi_sense_key {
SCSI_SK_NO_SENSE = 0x0, SCSI_SK_NO_SENSE = 0x0,
@@ -252,27 +251,26 @@ enum scsi_spc_mode {
struct spc_control_page_info_execpt { struct spc_control_page_info_execpt {
uint8_t page_code; uint8_t page_code;
uint8_t page_length; uint8_t page_length;
#define SPC_MP_INFEXP_PAGE_LENGTH 0x0A #define SPC_MP_INFEXP_PAGE_LENGTH 0x0A
uint8_t flags1; uint8_t flags1;
#define SPC_MP_INFEXP_PERF (1<<7) //!< Initiator Control #define SPC_MP_INFEXP_PERF (1<<7) //!< Initiator Control
#define SPC_MP_INFEXP_EBF (1<<5) //!< Caching Analysis Permitted #define SPC_MP_INFEXP_EBF (1<<5) //!< Caching Analysis Permitted
#define SPC_MP_INFEXP_EWASC (1<<4) //!< Discontinuity #define SPC_MP_INFEXP_EWASC (1<<4) //!< Discontinuity
#define SPC_MP_INFEXP_DEXCPT (1<<3) //!< Size enable #define SPC_MP_INFEXP_DEXCPT (1<<3) //!< Size enable
#define SPC_MP_INFEXP_TEST (1<<2) //!< Writeback Cache Enable #define SPC_MP_INFEXP_TEST (1<<2) //!< Writeback Cache Enable
#define SPC_MP_INFEXP_LOGERR (1<<0) //!< Log errors bit #define SPC_MP_INFEXP_LOGERR (1<<0) //!< Log errors bit
uint8_t mrie; uint8_t mrie;
#define SPC_MP_INFEXP_MRIE_NO_REPORT 0x00 #define SPC_MP_INFEXP_MRIE_NO_REPORT 0x00
#define SPC_MP_INFEXP_MRIE_ASYNC_EVENT 0x01 #define SPC_MP_INFEXP_MRIE_ASYNC_EVENT 0x01
#define SPC_MP_INFEXP_MRIE_GEN_UNIT 0x02 #define SPC_MP_INFEXP_MRIE_GEN_UNIT 0x02
#define SPC_MP_INFEXP_MRIE_COND_RECOV_ERROR 0x03 #define SPC_MP_INFEXP_MRIE_COND_RECOV_ERROR 0x03
#define SPC_MP_INFEXP_MRIE_UNCOND_RECOV_ERROR 0x04 #define SPC_MP_INFEXP_MRIE_UNCOND_RECOV_ERROR 0x04
#define SPC_MP_INFEXP_MRIE_NO_SENSE 0x05 #define SPC_MP_INFEXP_MRIE_NO_SENSE 0x05
#define SPC_MP_INFEXP_MRIE_ONLY_REPORT 0x06 #define SPC_MP_INFEXP_MRIE_ONLY_REPORT 0x06
be32_t interval_timer; be32_t interval_timer;
be32_t report_count; be32_t report_count;
}; };
enum scsi_spc_mode_sense_pc { enum scsi_spc_mode_sense_pc {
SCSI_MS_SENSE_PC_CURRENT = 0, SCSI_MS_SENSE_PC_CURRENT = 0,
SCSI_MS_SENSE_PC_CHANGEABLE = 1, SCSI_MS_SENSE_PC_CHANGEABLE = 1,
@@ -280,20 +278,15 @@ enum scsi_spc_mode_sense_pc {
SCSI_MS_SENSE_PC_SAVED = 3, SCSI_MS_SENSE_PC_SAVED = 3,
}; };
static inline bool scsi_mode_sense_dbd_is_set(const uint8_t * cdb) {
static inline bool scsi_mode_sense_dbd_is_set(const uint8_t * cdb)
{
return (cdb[1] >> 3) & 1; return (cdb[1] >> 3) & 1;
} }
static inline uint8_t scsi_mode_sense_get_page_code(const uint8_t * cdb) static inline uint8_t scsi_mode_sense_get_page_code(const uint8_t * cdb) {
{
return cdb[2] & 0x3F; return cdb[2] & 0x3F;
} }
static inline uint8_t scsi_mode_sense_get_pc(const uint8_t * cdb) static inline uint8_t scsi_mode_sense_get_pc(const uint8_t * cdb) {
{
return cdb[2] >> 6; return cdb[2] >> 6;
} }

8
Marlin/src/HAL/DUE/usb/sysclk.h
View File

@@ -136,7 +136,7 @@ extern "C" {
* initialization. * initialization.
*/ */
#ifndef CONFIG_SYSCLK_SOURCE #ifndef CONFIG_SYSCLK_SOURCE
# define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC
#endif #endif
/** /**
* \def CONFIG_SYSCLK_PRES * \def CONFIG_SYSCLK_PRES
@@ -149,7 +149,7 @@ extern "C" {
* after initialization. * after initialization.
*/ */
#ifndef CONFIG_SYSCLK_PRES #ifndef CONFIG_SYSCLK_PRES
# define CONFIG_SYSCLK_PRES 0 #define CONFIG_SYSCLK_PRES 0
#endif #endif
//@} //@}
@@ -197,7 +197,7 @@ extern "C" {
* USB is not required. * USB is not required.
*/ */
#ifdef __DOXYGEN__ #ifdef __DOXYGEN__
# define CONFIG_USBCLK_SOURCE #define CONFIG_USBCLK_SOURCE
#endif #endif
/** /**
@@ -209,7 +209,7 @@ extern "C" {
* defined. * defined.
*/ */
#ifdef __DOXYGEN__ #ifdef __DOXYGEN__
# define CONFIG_USBCLK_DIV #define CONFIG_USBCLK_DIV
#endif #endif

15
Marlin/src/HAL/DUE/usb/udc.h
View File

@@ -172,8 +172,7 @@ extern "C" {
} }
\endcode \endcode
*/ */
static inline bool udc_include_vbus_monitoring(void) static inline bool udc_include_vbus_monitoring(void) {
{
return udd_include_vbus_monitoring(); return udd_include_vbus_monitoring();
} }
@@ -192,32 +191,26 @@ void udc_stop(void);
* then it will attach device when an acceptable Vbus * then it will attach device when an acceptable Vbus
* level from the host is detected. * level from the host is detected.
*/ */
static inline void udc_attach(void) static inline void udc_attach(void) {
{
udd_attach(); udd_attach();
} }
/** /**
* \brief Detaches the device from the bus * \brief Detaches the device from the bus
* *
* The driver must remove pull-up on USB line D- or D+. * The driver must remove pull-up on USB line D- or D+.
*/ */
static inline void udc_detach(void) static inline void udc_detach(void) {
{
udd_detach(); udd_detach();
} }
/*! \brief The USB driver sends a resume signal called \e "Upstream Resume" /*! \brief The USB driver sends a resume signal called \e "Upstream Resume"
* This is authorized only when the remote wakeup feature is enabled by host. * This is authorized only when the remote wakeup feature is enabled by host.
*/ */
static inline void udc_remotewakeup(void) static inline void udc_remotewakeup(void) {
{
udd_send_remotewakeup(); udd_send_remotewakeup();
} }
/** /**
* \brief Returns a pointer on the current interface descriptor * \brief Returns a pointer on the current interface descriptor
* *

27
Marlin/src/HAL/DUE/usb/udc_desc.h
View File

@@ -80,19 +80,17 @@ extern "C" {
#define UDC_DESC_STORAGE #define UDC_DESC_STORAGE
// Descriptor storage in internal RAM // Descriptor storage in internal RAM
#if (defined UDC_DATA_USE_HRAM_SUPPORT) #if (defined UDC_DATA_USE_HRAM_SUPPORT)
# if defined(__GNUC__) #if defined(__GNUC__)
# define UDC_DATA(x) COMPILER_WORD_ALIGNED __attribute__((__section__(".data_hram0"))) #define UDC_DATA(x) COMPILER_WORD_ALIGNED __attribute__((__section__(".data_hram0")))
# define UDC_BSS(x) COMPILER_ALIGNED(x) __attribute__((__section__(".bss_hram0"))) #define UDC_BSS(x) COMPILER_ALIGNED(x) __attribute__((__section__(".bss_hram0")))
# elif defined(__ICCAVR32__) #elif defined(__ICCAVR32__)
# define UDC_DATA(x) COMPILER_ALIGNED(x) __data32 #define UDC_DATA(x) COMPILER_ALIGNED(x) __data32
# define UDC_BSS(x) COMPILER_ALIGNED(x) __data32 #define UDC_BSS(x) COMPILER_ALIGNED(x) __data32
# endif #endif
#else #else
# define UDC_DATA(x) COMPILER_ALIGNED(x) #define UDC_DATA(x) COMPILER_ALIGNED(x)
# define UDC_BSS(x) COMPILER_ALIGNED(x) #define UDC_BSS(x) COMPILER_ALIGNED(x)
#endif #endif
/** /**
* \brief Configuration descriptor and UDI link for one USB speed * \brief Configuration descriptor and UDI link for one USB speed
@@ -104,7 +102,6 @@ typedef struct {
udi_api_t UDC_DESC_STORAGE *UDC_DESC_STORAGE * udi_apis; udi_api_t UDC_DESC_STORAGE *UDC_DESC_STORAGE * udi_apis;
} udc_config_speed_t; } udc_config_speed_t;
/** /**
* \brief All information about the USB Device * \brief All information about the USB Device
*/ */
@@ -113,14 +110,14 @@ typedef struct {
usb_dev_desc_t UDC_DESC_STORAGE *confdev_lsfs; usb_dev_desc_t UDC_DESC_STORAGE *confdev_lsfs;
//! USB configuration descriptor and UDI API pointers for low or full speed //! USB configuration descriptor and UDI API pointers for low or full speed
udc_config_speed_t UDC_DESC_STORAGE *conf_lsfs; udc_config_speed_t UDC_DESC_STORAGE *conf_lsfs;
#ifdef USB_DEVICE_HS_SUPPORT #ifdef USB_DEVICE_HS_SUPPORT
//! USB device descriptor for high speed //! USB device descriptor for high speed
usb_dev_desc_t UDC_DESC_STORAGE *confdev_hs; usb_dev_desc_t UDC_DESC_STORAGE *confdev_hs;
//! USB device qualifier, only use in high speed mode //! USB device qualifier, only use in high speed mode
usb_dev_qual_desc_t UDC_DESC_STORAGE *qualifier; usb_dev_qual_desc_t UDC_DESC_STORAGE *qualifier;
//! USB configuration descriptor and UDI API pointers for high speed //! USB configuration descriptor and UDI API pointers for high speed
udc_config_speed_t UDC_DESC_STORAGE *conf_hs; udc_config_speed_t UDC_DESC_STORAGE *conf_hs;
#endif #endif
usb_dev_bos_desc_t UDC_DESC_STORAGE *conf_bos; usb_dev_bos_desc_t UDC_DESC_STORAGE *conf_bos;
} udc_config_t; } udc_config_t;

28
Marlin/src/HAL/DUE/usb/udd.h
View File

@@ -103,20 +103,16 @@ typedef struct {
extern udd_ctrl_request_t udd_g_ctrlreq; extern udd_ctrl_request_t udd_g_ctrlreq;
//! Return true if the setup request \a udd_g_ctrlreq indicates IN data transfer //! Return true if the setup request \a udd_g_ctrlreq indicates IN data transfer
#define Udd_setup_is_in() \ #define Udd_setup_is_in() (USB_REQ_DIR_IN == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK))
(USB_REQ_DIR_IN == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK))
//! Return true if the setup request \a udd_g_ctrlreq indicates OUT data transfer //! Return true if the setup request \a udd_g_ctrlreq indicates OUT data transfer
#define Udd_setup_is_out() \ #define Udd_setup_is_out() (USB_REQ_DIR_OUT == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK))
(USB_REQ_DIR_OUT == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK))
//! Return the type of the SETUP request \a udd_g_ctrlreq. \see usb_reqtype. //! Return the type of the SETUP request \a udd_g_ctrlreq. \see usb_reqtype.
#define Udd_setup_type() \ #define Udd_setup_type() (udd_g_ctrlreq.req.bmRequestType & USB_REQ_TYPE_MASK)
(udd_g_ctrlreq.req.bmRequestType & USB_REQ_TYPE_MASK)
//! Return the recipient of the SETUP request \a udd_g_ctrlreq. \see usb_recipient //! Return the recipient of the SETUP request \a udd_g_ctrlreq. \see usb_recipient
#define Udd_setup_recipient() \ #define Udd_setup_recipient() (udd_g_ctrlreq.req.bmRequestType & USB_REQ_RECIP_MASK)
(udd_g_ctrlreq.req.bmRequestType & USB_REQ_RECIP_MASK)
/** /**
* \brief End of halt callback function type. * \brief End of halt callback function type.
@@ -134,8 +130,7 @@ typedef void (*udd_callback_halt_cleared_t)(void);
* \param status UDD_EP_TRANSFER_ABORT, if transfer is aborted * \param status UDD_EP_TRANSFER_ABORT, if transfer is aborted
* \param n number of data transferred * \param n number of data transferred
*/ */
typedef void (*udd_callback_trans_t) (udd_ep_status_t status, typedef void (*udd_callback_trans_t) (udd_ep_status_t status, iram_size_t nb_transferred, udd_ep_id_t ep);
iram_size_t nb_transferred, udd_ep_id_t ep);
/** /**
* \brief Authorizes the VBUS event * \brief Authorizes the VBUS event
@@ -239,8 +234,7 @@ void udd_set_setup_payload( uint8_t *payload, uint16_t payload_size );
* *
* \return \c 1 if the endpoint is enabled, otherwise \c 0. * \return \c 1 if the endpoint is enabled, otherwise \c 0.
*/ */
bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes, bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes, uint16_t MaxEndpointSize);
uint16_t MaxEndpointSize);
/** /**
* \brief Disables an endpoint * \brief Disables an endpoint
@@ -294,8 +288,7 @@ bool udd_ep_clear_halt(udd_ep_id_t ep);
* *
* \return \c 1 if the register is accepted, otherwise \c 0. * \return \c 1 if the register is accepted, otherwise \c 0.
*/ */
bool udd_ep_wait_stall_clear(udd_ep_id_t ep, bool udd_ep_wait_stall_clear(udd_ep_id_t ep, udd_callback_halt_cleared_t callback);
udd_callback_halt_cleared_t callback);
/** /**
* \brief Allows to receive or send data on an endpoint * \brief Allows to receive or send data on an endpoint
@@ -321,9 +314,8 @@ bool udd_ep_wait_stall_clear(udd_ep_id_t ep,
* *
* \return \c 1 if function was successfully done, otherwise \c 0. * \return \c 1 if function was successfully done, otherwise \c 0.
*/ */
bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket, bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket, uint8_t * buf, iram_size_t buf_size, udd_callback_trans_t callback);
uint8_t * buf, iram_size_t buf_size,
udd_callback_trans_t callback);
/** /**
* \brief Aborts transfer on going on endpoint * \brief Aborts transfer on going on endpoint
* *
@@ -339,7 +331,6 @@ void udd_ep_abort(udd_ep_id_t ep);
//@} //@}
/** /**
* \name High speed test mode management * \name High speed test mode management
* *
@@ -352,7 +343,6 @@ void udd_test_mode_se0_nak(void);
void udd_test_mode_packet(void); void udd_test_mode_packet(void);
//@} //@}
/** /**
* \name UDC callbacks to provide for UDD * \name UDC callbacks to provide for UDD
* *

52
Marlin/src/HAL/DUE/usb/udi_cdc.h
View File

@@ -136,13 +136,13 @@ typedef struct {
//@{ //@{
//! By default no string associated to these interfaces //! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_0 #ifndef UDI_CDC_IAD_STRING_ID_0
#define UDI_CDC_IAD_STRING_ID_0 0 #define UDI_CDC_IAD_STRING_ID_0 0
#endif #endif
#ifndef UDI_CDC_COMM_STRING_ID_0 #ifndef UDI_CDC_COMM_STRING_ID_0
#define UDI_CDC_COMM_STRING_ID_0 0 #define UDI_CDC_COMM_STRING_ID_0 0
#endif #endif
#ifndef UDI_CDC_DATA_STRING_ID_0 #ifndef UDI_CDC_DATA_STRING_ID_0
#define UDI_CDC_DATA_STRING_ID_0 0 #define UDI_CDC_DATA_STRING_ID_0 0
#endif #endif
#define UDI_CDC_IAD_DESC_0 UDI_CDC_IAD_DESC(0) #define UDI_CDC_IAD_DESC_0 UDI_CDC_IAD_DESC(0)
#define UDI_CDC_COMM_DESC_0 UDI_CDC_COMM_DESC(0) #define UDI_CDC_COMM_DESC_0 UDI_CDC_COMM_DESC(0)
@@ -151,13 +151,13 @@ typedef struct {
//! By default no string associated to these interfaces //! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_1 #ifndef UDI_CDC_IAD_STRING_ID_1
#define UDI_CDC_IAD_STRING_ID_1 0 #define UDI_CDC_IAD_STRING_ID_1 0
#endif #endif
#ifndef UDI_CDC_COMM_STRING_ID_1 #ifndef UDI_CDC_COMM_STRING_ID_1
#define UDI_CDC_COMM_STRING_ID_1 0 #define UDI_CDC_COMM_STRING_ID_1 0
#endif #endif
#ifndef UDI_CDC_DATA_STRING_ID_1 #ifndef UDI_CDC_DATA_STRING_ID_1
#define UDI_CDC_DATA_STRING_ID_1 0 #define UDI_CDC_DATA_STRING_ID_1 0
#endif #endif
#define UDI_CDC_IAD_DESC_1 UDI_CDC_IAD_DESC(1) #define UDI_CDC_IAD_DESC_1 UDI_CDC_IAD_DESC(1)
#define UDI_CDC_COMM_DESC_1 UDI_CDC_COMM_DESC(1) #define UDI_CDC_COMM_DESC_1 UDI_CDC_COMM_DESC(1)
@@ -166,13 +166,13 @@ typedef struct {
//! By default no string associated to these interfaces //! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_2 #ifndef UDI_CDC_IAD_STRING_ID_2
#define UDI_CDC_IAD_STRING_ID_2 0 #define UDI_CDC_IAD_STRING_ID_2 0
#endif #endif
#ifndef UDI_CDC_COMM_STRING_ID_2 #ifndef UDI_CDC_COMM_STRING_ID_2
#define UDI_CDC_COMM_STRING_ID_2 0 #define UDI_CDC_COMM_STRING_ID_2 0
#endif #endif
#ifndef UDI_CDC_DATA_STRING_ID_2 #ifndef UDI_CDC_DATA_STRING_ID_2
#define UDI_CDC_DATA_STRING_ID_2 0 #define UDI_CDC_DATA_STRING_ID_2 0
#endif #endif
#define UDI_CDC_IAD_DESC_2 UDI_CDC_IAD_DESC(2) #define UDI_CDC_IAD_DESC_2 UDI_CDC_IAD_DESC(2)
#define UDI_CDC_COMM_DESC_2 UDI_CDC_COMM_DESC(2) #define UDI_CDC_COMM_DESC_2 UDI_CDC_COMM_DESC(2)
@@ -181,13 +181,13 @@ typedef struct {
//! By default no string associated to these interfaces //! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_3 #ifndef UDI_CDC_IAD_STRING_ID_3
#define UDI_CDC_IAD_STRING_ID_3 0 #define UDI_CDC_IAD_STRING_ID_3 0
#endif #endif
#ifndef UDI_CDC_COMM_STRING_ID_3 #ifndef UDI_CDC_COMM_STRING_ID_3
#define UDI_CDC_COMM_STRING_ID_3 0 #define UDI_CDC_COMM_STRING_ID_3 0
#endif #endif
#ifndef UDI_CDC_DATA_STRING_ID_3 #ifndef UDI_CDC_DATA_STRING_ID_3
#define UDI_CDC_DATA_STRING_ID_3 0 #define UDI_CDC_DATA_STRING_ID_3 0
#endif #endif
#define UDI_CDC_IAD_DESC_3 UDI_CDC_IAD_DESC(3) #define UDI_CDC_IAD_DESC_3 UDI_CDC_IAD_DESC(3)
#define UDI_CDC_COMM_DESC_3 UDI_CDC_COMM_DESC(3) #define UDI_CDC_COMM_DESC_3 UDI_CDC_COMM_DESC(3)
@@ -196,13 +196,13 @@ typedef struct {
//! By default no string associated to these interfaces //! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_4 #ifndef UDI_CDC_IAD_STRING_ID_4
#define UDI_CDC_IAD_STRING_ID_4 0 #define UDI_CDC_IAD_STRING_ID_4 0
#endif #endif
#ifndef UDI_CDC_COMM_STRING_ID_4 #ifndef UDI_CDC_COMM_STRING_ID_4
#define UDI_CDC_COMM_STRING_ID_4 0 #define UDI_CDC_COMM_STRING_ID_4 0
#endif #endif
#ifndef UDI_CDC_DATA_STRING_ID_4 #ifndef UDI_CDC_DATA_STRING_ID_4
#define UDI_CDC_DATA_STRING_ID_4 0 #define UDI_CDC_DATA_STRING_ID_4 0
#endif #endif
#define UDI_CDC_IAD_DESC_4 UDI_CDC_IAD_DESC(4) #define UDI_CDC_IAD_DESC_4 UDI_CDC_IAD_DESC(4)
#define UDI_CDC_COMM_DESC_4 UDI_CDC_COMM_DESC(4) #define UDI_CDC_COMM_DESC_4 UDI_CDC_COMM_DESC(4)
@@ -211,13 +211,13 @@ typedef struct {
//! By default no string associated to these interfaces //! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_5 #ifndef UDI_CDC_IAD_STRING_ID_5
#define UDI_CDC_IAD_STRING_ID_5 0 #define UDI_CDC_IAD_STRING_ID_5 0
#endif #endif
#ifndef UDI_CDC_COMM_STRING_ID_5 #ifndef UDI_CDC_COMM_STRING_ID_5
#define UDI_CDC_COMM_STRING_ID_5 0 #define UDI_CDC_COMM_STRING_ID_5 0
#endif #endif
#ifndef UDI_CDC_DATA_STRING_ID_5 #ifndef UDI_CDC_DATA_STRING_ID_5
#define UDI_CDC_DATA_STRING_ID_5 0 #define UDI_CDC_DATA_STRING_ID_5 0
#endif #endif
#define UDI_CDC_IAD_DESC_5 UDI_CDC_IAD_DESC(5) #define UDI_CDC_IAD_DESC_5 UDI_CDC_IAD_DESC(5)
#define UDI_CDC_COMM_DESC_5 UDI_CDC_COMM_DESC(5) #define UDI_CDC_COMM_DESC_5 UDI_CDC_COMM_DESC(5)
@@ -226,13 +226,13 @@ typedef struct {
//! By default no string associated to these interfaces //! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_6 #ifndef UDI_CDC_IAD_STRING_ID_6
#define UDI_CDC_IAD_STRING_ID_6 0 #define UDI_CDC_IAD_STRING_ID_6 0
#endif #endif
#ifndef UDI_CDC_COMM_STRING_ID_6 #ifndef UDI_CDC_COMM_STRING_ID_6
#define UDI_CDC_COMM_STRING_ID_6 0 #define UDI_CDC_COMM_STRING_ID_6 0
#endif #endif
#ifndef UDI_CDC_DATA_STRING_ID_6 #ifndef UDI_CDC_DATA_STRING_ID_6
#define UDI_CDC_DATA_STRING_ID_6 0 #define UDI_CDC_DATA_STRING_ID_6 0
#endif #endif
#define UDI_CDC_IAD_DESC_6 UDI_CDC_IAD_DESC(6) #define UDI_CDC_IAD_DESC_6 UDI_CDC_IAD_DESC(6)
#define UDI_CDC_COMM_DESC_6 UDI_CDC_COMM_DESC(6) #define UDI_CDC_COMM_DESC_6 UDI_CDC_COMM_DESC(6)
@@ -240,7 +240,6 @@ typedef struct {
#define UDI_CDC_DATA_DESC_6_HS UDI_CDC_DATA_DESC_HS(6) #define UDI_CDC_DATA_DESC_6_HS UDI_CDC_DATA_DESC_HS(6)
//@} //@}
//! Content of CDC IAD interface descriptor for all speeds //! Content of CDC IAD interface descriptor for all speeds
#define UDI_CDC_IAD_DESC(port) { \ #define UDI_CDC_IAD_DESC(port) { \
.bLength = sizeof(usb_iad_desc_t),\ .bLength = sizeof(usb_iad_desc_t),\
@@ -627,18 +626,15 @@ iram_size_t udi_cdc_multi_write_buf(uint8_t port, const void* buf, iram_size_t s
* Add to application C-file: * Add to application C-file:
* \code * \code
static bool my_flag_autorize_cdc_transfert = false; static bool my_flag_autorize_cdc_transfert = false;
bool my_callback_cdc_enable(void) bool my_callback_cdc_enable(void) {
{
my_flag_autorize_cdc_transfert = true; my_flag_autorize_cdc_transfert = true;
return true; return true;
} }
void my_callback_cdc_disable(void) void my_callback_cdc_disable(void) {
{
my_flag_autorize_cdc_transfert = false; my_flag_autorize_cdc_transfert = false;
} }
void task(void) void task(void) {
{
if (my_flag_autorize_cdc_transfert) { if (my_flag_autorize_cdc_transfert) {
udi_cdc_putc('A'); udi_cdc_putc('A');
udi_cdc_getc(); udi_cdc_getc();

142
Marlin/src/HAL/DUE/usb/udi_msc.c
View File

@@ -372,9 +372,7 @@ static void udi_msc_sbc_trans(bool b_read);
//@} //@}
bool udi_msc_enable(void) {
bool udi_msc_enable(void)
{
uint8_t lun; uint8_t lun;
udi_msc_b_trans_req = false; udi_msc_b_trans_req = false;
udi_msc_b_cbw_invalid = false; udi_msc_b_cbw_invalid = false;
@@ -397,18 +395,14 @@ bool udi_msc_enable(void)
return true; return true;
} }
void udi_msc_disable(void) {
void udi_msc_disable(void)
{
udi_msc_b_trans_req = false; udi_msc_b_trans_req = false;
udi_msc_b_ack_trans = true; udi_msc_b_ack_trans = true;
udi_msc_b_reset_trans = true; udi_msc_b_reset_trans = true;
UDI_MSC_DISABLE_EXT(); UDI_MSC_DISABLE_EXT();
} }
bool udi_msc_setup(void) {
bool udi_msc_setup(void)
{
if (Udd_setup_is_in()) { if (Udd_setup_is_in()) {
// Requests Interface GET // Requests Interface GET
if (Udd_setup_type() == USB_REQ_TYPE_CLASS) { if (Udd_setup_type() == USB_REQ_TYPE_CLASS) {
@@ -451,17 +445,14 @@ bool udi_msc_setup(void)
return false; // Not supported request return false; // Not supported request
} }
uint8_t udi_msc_getsetting(void) uint8_t udi_msc_getsetting(void) {
{
return 0; // MSC don't have multiple alternate setting return 0; // MSC don't have multiple alternate setting
} }
// ------------------------ // ------------------------
//------- Routines to process CBW packet //------- Routines to process CBW packet
static void udi_msc_cbw_invalid(void) static void udi_msc_cbw_invalid(void) {
{
if (!udi_msc_b_cbw_invalid) if (!udi_msc_b_cbw_invalid)
return; // Don't re-stall endpoint if error reset by setup return; // Don't re-stall endpoint if error reset by setup
udd_ep_set_halt(UDI_MSC_EP_OUT); udd_ep_set_halt(UDI_MSC_EP_OUT);
@@ -469,8 +460,7 @@ static void udi_msc_cbw_invalid(void)
udd_ep_wait_stall_clear(UDI_MSC_EP_OUT, udi_msc_cbw_invalid); udd_ep_wait_stall_clear(UDI_MSC_EP_OUT, udi_msc_cbw_invalid);
} }
static void udi_msc_csw_invalid(void) static void udi_msc_csw_invalid(void) {
{
if (!udi_msc_b_cbw_invalid) if (!udi_msc_b_cbw_invalid)
return; // Don't re-stall endpoint if error reset by setup return; // Don't re-stall endpoint if error reset by setup
udd_ep_set_halt(UDI_MSC_EP_IN); udd_ep_set_halt(UDI_MSC_EP_IN);
@@ -478,8 +468,7 @@ static void udi_msc_csw_invalid(void)
udd_ep_wait_stall_clear(UDI_MSC_EP_IN, udi_msc_csw_invalid); udd_ep_wait_stall_clear(UDI_MSC_EP_IN, udi_msc_csw_invalid);
} }
static void udi_msc_cbw_wait(void) static void udi_msc_cbw_wait(void) {
{
// Register buffer and callback on OUT endpoint // Register buffer and callback on OUT endpoint
if (!udd_ep_run(UDI_MSC_EP_OUT, true, if (!udd_ep_run(UDI_MSC_EP_OUT, true,
(uint8_t *) & udi_msc_cbw, (uint8_t *) & udi_msc_cbw,
@@ -490,10 +479,8 @@ static void udi_msc_cbw_wait(void)
} }
} }
static void udi_msc_cbw_received(udd_ep_status_t status, static void udi_msc_cbw_received(udd_ep_status_t status,
iram_size_t nb_received, udd_ep_id_t ep) iram_size_t nb_received, udd_ep_id_t ep) {
{
UNUSED(ep); UNUSED(ep);
// Check status of transfer // Check status of transfer
if (UDD_EP_TRANSFER_OK != status) { if (UDD_EP_TRANSFER_OK != status) {
@@ -582,9 +569,7 @@ static void udi_msc_cbw_received(udd_ep_status_t status,
} }
} }
static bool udi_msc_cbw_validate(uint32_t alloc_len, uint8_t dir_flag) {
static bool udi_msc_cbw_validate(uint32_t alloc_len, uint8_t dir_flag)
{
/* /*
* The following cases should result in a phase error: * The following cases should result in a phase error:
* - Case 2: Hn < Di * - Case 2: Hn < Di
@@ -612,12 +597,10 @@ static bool udi_msc_cbw_validate(uint32_t alloc_len, uint8_t dir_flag)
return true; return true;
} }
// ------------------------ // ------------------------
//------- Routines to process small data packet //------- Routines to process small data packet
static void udi_msc_data_send(uint8_t * buffer, uint8_t buf_size) static void udi_msc_data_send(uint8_t * buffer, uint8_t buf_size) {
{
// Sends data on IN endpoint // Sends data on IN endpoint
if (!udd_ep_run(UDI_MSC_EP_IN, true, if (!udd_ep_run(UDI_MSC_EP_IN, true,
buffer, buf_size, udi_msc_data_sent)) { buffer, buf_size, udi_msc_data_sent)) {
@@ -627,10 +610,8 @@ static void udi_msc_data_send(uint8_t * buffer, uint8_t buf_size)
} }
} }
static void udi_msc_data_sent(udd_ep_status_t status, iram_size_t nb_sent, static void udi_msc_data_sent(udd_ep_status_t status, iram_size_t nb_sent,
udd_ep_id_t ep) udd_ep_id_t ep) {
{
UNUSED(ep); UNUSED(ep);
if (UDD_EP_TRANSFER_OK != status) { if (UDD_EP_TRANSFER_OK != status) {
// Error protocol // Error protocol
@@ -644,12 +625,10 @@ static void udi_msc_data_sent(udd_ep_status_t status, iram_size_t nb_sent,
udi_msc_csw_process(); udi_msc_csw_process();
} }
// ------------------------ // ------------------------
//------- Routines to process CSW packet //------- Routines to process CSW packet
static void udi_msc_csw_process(void) static void udi_msc_csw_process(void) {
{
if (0 != udi_msc_csw.dCSWDataResidue) { if (0 != udi_msc_csw.dCSWDataResidue) {
// Residue not NULL // Residue not NULL
// then STALL next request from USB host on corresponding endpoint // then STALL next request from USB host on corresponding endpoint
@@ -664,9 +643,7 @@ static void udi_msc_csw_process(void)
udi_msc_csw_send(); udi_msc_csw_send();
} }
void udi_msc_csw_send(void) {
void udi_msc_csw_send(void)
{
// Sends CSW on IN endpoint // Sends CSW on IN endpoint
if (!udd_ep_run(UDI_MSC_EP_IN, false, if (!udd_ep_run(UDI_MSC_EP_IN, false,
(uint8_t *) & udi_msc_csw, (uint8_t *) & udi_msc_csw,
@@ -678,10 +655,8 @@ void udi_msc_csw_send(void)
} }
} }
static void udi_msc_csw_sent(udd_ep_status_t status, iram_size_t nb_sent, static void udi_msc_csw_sent(udd_ep_status_t status, iram_size_t nb_sent,
udd_ep_id_t ep) udd_ep_id_t ep) {
{
UNUSED(ep); UNUSED(ep);
UNUSED(status); UNUSED(status);
UNUSED(nb_sent); UNUSED(nb_sent);
@@ -690,20 +665,17 @@ static void udi_msc_csw_sent(udd_ep_status_t status, iram_size_t nb_sent,
udi_msc_cbw_wait(); udi_msc_cbw_wait();
} }
// ------------------------ // ------------------------
//------- Routines manage sense data //------- Routines manage sense data
static void udi_msc_clear_sense(void) static void udi_msc_clear_sense(void) {
{
memset((uint8_t*)&udi_msc_sense, 0, sizeof(struct scsi_request_sense_data)); memset((uint8_t*)&udi_msc_sense, 0, sizeof(struct scsi_request_sense_data));
udi_msc_sense.valid_reponse_code = SCSI_SENSE_VALID | SCSI_SENSE_CURRENT; udi_msc_sense.valid_reponse_code = SCSI_SENSE_VALID | SCSI_SENSE_CURRENT;
udi_msc_sense.AddSenseLen = SCSI_SENSE_ADDL_LEN(sizeof(udi_msc_sense)); udi_msc_sense.AddSenseLen = SCSI_SENSE_ADDL_LEN(sizeof(udi_msc_sense));
} }
static void udi_msc_sense_fail(uint8_t sense_key, uint16_t add_sense, static void udi_msc_sense_fail(uint8_t sense_key, uint16_t add_sense,
uint32_t lba) uint32_t lba) {
{
udi_msc_clear_sense(); udi_msc_clear_sense();
udi_msc_csw.bCSWStatus = USB_CSW_STATUS_FAIL; udi_msc_csw.bCSWStatus = USB_CSW_STATUS_FAIL;
udi_msc_sense.sense_flag_key = sense_key; udi_msc_sense.sense_flag_key = sense_key;
@@ -715,53 +687,39 @@ static void udi_msc_sense_fail(uint8_t sense_key, uint16_t add_sense,
udi_msc_sense.AddSnsCodeQlfr = add_sense; udi_msc_sense.AddSnsCodeQlfr = add_sense;
} }
static void udi_msc_sense_pass(void) static void udi_msc_sense_pass(void) {
{
udi_msc_clear_sense(); udi_msc_clear_sense();
udi_msc_csw.bCSWStatus = USB_CSW_STATUS_PASS; udi_msc_csw.bCSWStatus = USB_CSW_STATUS_PASS;
} }
static void udi_msc_sense_fail_not_present(void) {
static void udi_msc_sense_fail_not_present(void)
{
udi_msc_sense_fail(SCSI_SK_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT, 0); udi_msc_sense_fail(SCSI_SK_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
} }
static void udi_msc_sense_fail_busy_or_change(void) static void udi_msc_sense_fail_busy_or_change(void) {
{ udi_msc_sense_fail(SCSI_SK_UNIT_ATTENTION, SCSI_ASC_NOT_READY_TO_READY_CHANGE, 0);
udi_msc_sense_fail(SCSI_SK_UNIT_ATTENTION,
SCSI_ASC_NOT_READY_TO_READY_CHANGE, 0);
} }
static void udi_msc_sense_fail_hardware(void) static void udi_msc_sense_fail_hardware(void) {
{ udi_msc_sense_fail(SCSI_SK_HARDWARE_ERROR, SCSI_ASC_NO_ADDITIONAL_SENSE_INFO, 0);
udi_msc_sense_fail(SCSI_SK_HARDWARE_ERROR,
SCSI_ASC_NO_ADDITIONAL_SENSE_INFO, 0);
} }
static void udi_msc_sense_fail_protected(void) static void udi_msc_sense_fail_protected(void) {
{
udi_msc_sense_fail(SCSI_SK_DATA_PROTECT, SCSI_ASC_WRITE_PROTECTED, 0); udi_msc_sense_fail(SCSI_SK_DATA_PROTECT, SCSI_ASC_WRITE_PROTECTED, 0);
} }
static void udi_msc_sense_fail_cdb_invalid(void) static void udi_msc_sense_fail_cdb_invalid(void) {
{ udi_msc_sense_fail(SCSI_SK_ILLEGAL_REQUEST, SCSI_ASC_INVALID_FIELD_IN_CDB, 0);
udi_msc_sense_fail(SCSI_SK_ILLEGAL_REQUEST,
SCSI_ASC_INVALID_FIELD_IN_CDB, 0);
} }
static void udi_msc_sense_command_invalid(void) static void udi_msc_sense_command_invalid(void) {
{ udi_msc_sense_fail(SCSI_SK_ILLEGAL_REQUEST, SCSI_ASC_INVALID_COMMAND_OPERATION_CODE, 0);
udi_msc_sense_fail(SCSI_SK_ILLEGAL_REQUEST,
SCSI_ASC_INVALID_COMMAND_OPERATION_CODE, 0);
} }
// ------------------------ // ------------------------
//------- Routines manage SCSI Commands //------- Routines manage SCSI Commands
static void udi_msc_spc_requestsense(void) static void udi_msc_spc_requestsense(void) {
{
uint8_t length = udi_msc_cbw.CDB[4]; uint8_t length = udi_msc_cbw.CDB[4];
// Can't send more than sense data length // Can't send more than sense data length
@@ -774,9 +732,7 @@ static void udi_msc_spc_requestsense(void)
udi_msc_data_send((uint8_t*)&udi_msc_sense, length); udi_msc_data_send((uint8_t*)&udi_msc_sense, length);
} }
static void udi_msc_spc_inquiry(void) {
static void udi_msc_spc_inquiry(void)
{
uint8_t length, i; uint8_t length, i;
UDC_DATA(4) UDC_DATA(4)
// Constant inquiry data for all LUNs // Constant inquiry data for all LUNs
@@ -835,9 +791,7 @@ static void udi_msc_spc_inquiry(void)
udi_msc_data_send((uint8_t *) & udi_msc_inquiry_data, length); udi_msc_data_send((uint8_t *) & udi_msc_inquiry_data, length);
} }
static bool udi_msc_spc_testunitready_global(void) {
static bool udi_msc_spc_testunitready_global(void)
{
switch (mem_test_unit_ready(udi_msc_cbw.bCBWLUN)) { switch (mem_test_unit_ready(udi_msc_cbw.bCBWLUN)) {
case CTRL_GOOD: case CTRL_GOOD:
return true; // Don't change sense data return true; // Don't change sense data
@@ -855,9 +809,7 @@ static bool udi_msc_spc_testunitready_global(void)
return false; return false;
} }
static void udi_msc_spc_testunitready(void) {
static void udi_msc_spc_testunitready(void)
{
if (udi_msc_spc_testunitready_global()) { if (udi_msc_spc_testunitready_global()) {
// LUN ready, then update sense data with status pass // LUN ready, then update sense data with status pass
udi_msc_sense_pass(); udi_msc_sense_pass();
@@ -866,9 +818,7 @@ static void udi_msc_spc_testunitready(void)
udi_msc_csw_process(); udi_msc_csw_process();
} }
static void udi_msc_spc_mode_sense(bool b_sense10) {
static void udi_msc_spc_mode_sense(bool b_sense10)
{
// Union of all mode sense structures // Union of all mode sense structures
union sense_6_10 { union sense_6_10 {
struct { struct {
@@ -943,9 +893,7 @@ static void udi_msc_spc_mode_sense(bool b_sense10)
udi_msc_data_send((uint8_t *) & sense, request_lgt); udi_msc_data_send((uint8_t *) & sense, request_lgt);
} }
static void udi_msc_spc_prevent_allow_medium_removal(void) {
static void udi_msc_spc_prevent_allow_medium_removal(void)
{
uint8_t prevent = udi_msc_cbw.CDB[4]; uint8_t prevent = udi_msc_cbw.CDB[4];
if (0 == prevent) { if (0 == prevent) {
udi_msc_sense_pass(); udi_msc_sense_pass();
@@ -955,9 +903,7 @@ static void udi_msc_spc_prevent_allow_medium_removal(void)
udi_msc_csw_process(); udi_msc_csw_process();
} }
static void udi_msc_sbc_start_stop(void) {
static void udi_msc_sbc_start_stop(void)
{
bool start = 0x1 & udi_msc_cbw.CDB[4]; bool start = 0x1 & udi_msc_cbw.CDB[4];
bool loej = 0x2 & udi_msc_cbw.CDB[4]; bool loej = 0x2 & udi_msc_cbw.CDB[4];
if (loej) { if (loej) {
@@ -967,9 +913,7 @@ static void udi_msc_sbc_start_stop(void)
udi_msc_csw_process(); udi_msc_csw_process();
} }
static void udi_msc_sbc_read_capacity(void) {
static void udi_msc_sbc_read_capacity(void)
{
UDC_BSS(4) static struct sbc_read_capacity10_data udi_msc_capacity; UDC_BSS(4) static struct sbc_read_capacity10_data udi_msc_capacity;
if (!udi_msc_cbw_validate(sizeof(udi_msc_capacity), if (!udi_msc_cbw_validate(sizeof(udi_msc_capacity),
@@ -1003,9 +947,7 @@ static void udi_msc_sbc_read_capacity(void)
sizeof(udi_msc_capacity)); sizeof(udi_msc_capacity));
} }
static void udi_msc_sbc_trans(bool b_read) {
static void udi_msc_sbc_trans(bool b_read)
{
uint32_t trans_size; uint32_t trans_size;
if (!b_read) { if (!b_read) {
@@ -1038,9 +980,7 @@ static void udi_msc_sbc_trans(bool b_read)
UDI_MSC_NOTIFY_TRANS_EXT(); UDI_MSC_NOTIFY_TRANS_EXT();
} }
bool udi_msc_process_trans(void) {
bool udi_msc_process_trans(void)
{
Ctrl_status status; Ctrl_status status;
if (!udi_msc_b_trans_req) if (!udi_msc_b_trans_req)
@@ -1084,10 +1024,8 @@ bool udi_msc_process_trans(void)
return true; return true;
} }
static void udi_msc_trans_ack(udd_ep_status_t status, iram_size_t n, static void udi_msc_trans_ack(udd_ep_status_t status, iram_size_t n,
udd_ep_id_t ep) udd_ep_id_t ep) {
{
UNUSED(ep); UNUSED(ep);
UNUSED(n); UNUSED(n);
// Update variable to signal the end of transfer // Update variable to signal the end of transfer
@@ -1095,10 +1033,8 @@ static void udi_msc_trans_ack(udd_ep_status_t status, iram_size_t n,
udi_msc_b_ack_trans = true; udi_msc_b_ack_trans = true;
} }
bool udi_msc_trans_block(bool b_read, uint8_t * block, iram_size_t block_size, bool udi_msc_trans_block(bool b_read, uint8_t * block, iram_size_t block_size,
void (*callback) (udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep)) void (*callback) (udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep)) {
{
if (!udi_msc_b_ack_trans) if (!udi_msc_b_ack_trans)
return false; // No possible, transfer on going return false; // No possible, transfer on going

11
Marlin/src/HAL/DUE/usb/udi_msc.h
View File

@@ -129,7 +129,6 @@ typedef struct {
} }
//@} //@}
/** /**
* \ingroup udi_group * \ingroup udi_group
* \defgroup udi_msc_group USB Device Interface (UDI) for Mass Storage Class (MSC) * \defgroup udi_msc_group USB Device Interface (UDI) for Mass Storage Class (MSC)
@@ -170,7 +169,6 @@ bool udi_msc_trans_block(bool b_read, uint8_t * block, iram_size_t block_size,
} }
#endif #endif
/** /**
* \page udi_msc_quickstart Quick start guide for USB device Mass Storage module (UDI MSC) * \page udi_msc_quickstart Quick start guide for USB device Mass Storage module (UDI MSC)
* *
@@ -215,18 +213,15 @@ bool udi_msc_trans_block(bool b_read, uint8_t * block, iram_size_t block_size,
* Add to application C-file: * Add to application C-file:
* \code * \code
static bool my_flag_autorize_msc_transfert = false; static bool my_flag_autorize_msc_transfert = false;
bool my_callback_msc_enable(void) bool my_callback_msc_enable(void) {
{
my_flag_autorize_msc_transfert = true; my_flag_autorize_msc_transfert = true;
return true; return true;
} }
void my_callback_msc_disable(void) void my_callback_msc_disable(void) {
{
my_flag_autorize_msc_transfert = false; my_flag_autorize_msc_transfert = false;
} }
void task(void) void task(void) {
{
udi_msc_process_trans(); udi_msc_process_trans();
} }
\endcode \endcode

5
Marlin/src/HAL/DUE/usb/uotghs_otg.h
View File

@@ -130,8 +130,8 @@ void otg_dual_disable(void);
#define otg_reset() \ #define otg_reset() \
do { \ do { \
UOTGHS->UOTGHS_CTRL = 0; \ UOTGHS->UOTGHS_CTRL = 0; \
while( UOTGHS->UOTGHS_SR & 0x3FFF) {\ while( UOTGHS->UOTGHS_SR & 0x3FFF) { \
UOTGHS->UOTGHS_SCR = 0xFFFFFFFF;\ UOTGHS->UOTGHS_SCR = 0xFFFFFFFF; \
} \ } \
} while (0) } while (0)
//! Enable USB macro //! Enable USB macro
@@ -166,7 +166,6 @@ void otg_dual_disable(void);
Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK),\ Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK),\
Rd_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMVALUE_Msk)) Rd_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMVALUE_Msk))
//! Get the dual-role device state of the internal USB finite state machine of the UOTGHS controller //! Get the dual-role device state of the internal USB finite state machine of the UOTGHS controller
#define otg_get_fsm_drd_state() (Rd_bitfield(UOTGHS->UOTGHS_FSM, UOTGHS_FSM_DRDSTATE_Msk)) #define otg_get_fsm_drd_state() (Rd_bitfield(UOTGHS->UOTGHS_FSM, UOTGHS_FSM_DRDSTATE_Msk))
#define Is_otg_a_suspend() (4==otg_get_fsm_drd_state()) #define Is_otg_a_suspend() (4==otg_get_fsm_drd_state())