diff --git a/PKGBUILD b/PKGBUILD
index 48e5bea..3d5eb2d 100644
--- a/PKGBUILD
+++ b/PKGBUILD
@@ -59,7 +59,7 @@ else
 fi
 pkgname=("${pkgbase}" "${pkgbase}-headers")
 pkgver="${_basekernel}"."${_sub}"
-pkgrel=224
+pkgrel=225
 pkgdesc='Linux-tkg'
 arch=('x86_64') # no i686 in here
 url="http://www.kernel.org/"
@@ -102,7 +102,7 @@ case $_basever in
         	0012-linux-hardened.patch
 	)
 	sha256sums=('bf338980b1670bca287f9994b7441c2361907635879169c64ae78364efc5f491'
-            'fda82c324c5bfa499f3e86489041fd82c9760b97cf7dffc85409f9cd2faf60d0'
+            '50e4719eb877720934c18f8ba3044a81650709d8cbcb356bcca87fd41609daf3'
             #'SKIP'
             'b0c4c60669f47ba4d3d1388368a5f9790aa697af42c917ed2ef177f111336d8b'
             '1f4a20d6eaaa0d969af93152a65191492400c6aa838fc1c290b0dd29bb6019d8'
@@ -318,7 +318,7 @@ case $_basever in
         0012-misc-additions.patch
     )
     sha256sums=('dcdf99e43e98330d925016985bfbc7b83c66d367b714b2de0cbbfcbf83d8ca43'
-            'c46f7ee8d945c28cf4a5c972a13eadf971f8c532bdedadccb8eaaf88be96e20f'
+            'b8dc24276c5ceac17afbd67bd472e1e0dc55436bb4ad7855039f2fa798d0e99d'
             'SKIP'
             'f2d15531096e97239a67f7642d85666a2f27c5e053b38ff9a2aa704dfc388f8a'
             'eb1da1a028a1c967222b5bdac1db2b2c4d8285bafd714892f6fc821c10416341'
@@ -635,7 +635,7 @@ case $_basever in
         0002-mm-Support-soft-dirty-flag-read-with-reset.patch
     )
     sha256sums=('57b2cf6991910e3b67a1b3490022e8a0674b6965c74c12da1e99d138d1991ee8'
-            '8fdc0ef34a877379bcb9b617006edafba66f9213fc2c1df7451b578ae33b5496'
+            '23f5753121e2f18ef757449f94728d18ba70a20728dd217a53d4fa0a1cde621e'
             'SKIP'
             '011d94a86f16c66772bdf0540ab9add74f2ccaa7d51dd2074492f70a663aa4a2'
             '1e15fc2ef3fa770217ecc63a220e5df2ddbcf3295eb4a021171e7edd4c6cc898'
@@ -655,7 +655,7 @@ case $_basever in
             '9fad4a40449e09522899955762c8928ae17f4cdaa16e01239fd12592e9d58177'
             '978b197efa56781a1d5651a3649c3d8b926d55748b4b9063788dfe1a861fc1bc'
             '768239d739180c0199545b5c5cf2d78de6261aec769008e6a2b7e97c7477b756'
-            '4cd39ae0f0cd218c32bc3d0ad14ff35a34851da71f0cf0116385ac501354ed16'
+            '434e4707efc1bc3919597c87d44fa537f7563ae04236479bbf1adb5f410ab69d'
             '1b656ad96004f27e9dc63d7f430b50d5c48510d6d4cd595a81c24b21adb70313'
             'b0319a7dff9c48b2f3e3d3597ee154bf92223149a633a8b7ce4026252db86da6')
 	;;
diff --git a/linux-tkg-config/prepare b/linux-tkg-config/prepare
index d35630f..a53b371 100644
--- a/linux-tkg-config/prepare
+++ b/linux-tkg-config/prepare
@@ -5,16 +5,16 @@ _supported_kernels=("5.16" "5.15" "5.14" "5.13" "5.12" "5.11" "5.10" "5.9" "5.8"
 
 typeset -A _kver_subver_map
 _kver_subver_map=(
-  ["5.4"]="160"
+  ["5.4"]="163"
   ["5.7"]="19"
   ["5.8"]="18"
   ["5.9"]="16"
-  ["5.10"]="81"
+  ["5.10"]="83"
   ["5.11"]="22"
   ["5.12"]="19"
   ["5.13"]="19"
   ["5.14"]="21"
-  ["5.15"]="5"
+  ["5.15"]="6"
   ["5.16"]="rc3"
 )
 
diff --git a/linux-tkg-patches/5.15/0012-misc-additions.patch b/linux-tkg-patches/5.15/0012-misc-additions.patch
index 8ecbaf5..a7f9319 100644
--- a/linux-tkg-patches/5.15/0012-misc-additions.patch
+++ b/linux-tkg-patches/5.15/0012-misc-additions.patch
@@ -318,540 +318,3 @@ index db2ca49a36e1a316af7790b26301370200cc0d48..5d3679bd6b29b837c4ffb17c92416dca
  		    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
  		    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
 
-From 42791d8ca2eb407d178d3f269485b6eb6f119fba Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 23 Nov 2021 11:36:01 -0500
-Subject: [PATCH] drm/amdgpu/pm: fix powerplay OD interface
-
-The overclocking interface currently appends data to a
-string.  Revert back to using sprintf().
-
-Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1774
-Fixes: 6db0c87a0a8ee1 ("amdgpu/pm: Replace hwmgr smu usage of sprintf with sysfs_emit")
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c  | 20 +++----
- .../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c   | 24 ++++----
- .../drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c   |  6 +-
- .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 28 +++++----
- .../drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c | 10 ++--
- .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 58 +++++++++----------
- 6 files changed, 67 insertions(+), 79 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
-index 258c573acc97..1f406f21b452 100644
---- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
-@@ -1024,8 +1024,6 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
- 	uint32_t min_freq, max_freq = 0;
- 	uint32_t ret = 0;
-
--	phm_get_sysfs_buf(&buf, &size);
--
- 	switch (type) {
- 	case PP_SCLK:
- 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &now);
-@@ -1038,13 +1036,13 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
- 		else
- 			i = 1;
-
--		size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
-+		size += sprintf(buf + size, "0: %uMhz %s\n",
- 					data->gfx_min_freq_limit/100,
- 					i == 0 ? "*" : "");
--		size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
-+		size += sprintf(buf + size, "1: %uMhz %s\n",
- 					i == 1 ? now : SMU10_UMD_PSTATE_GFXCLK,
- 					i == 1 ? "*" : "");
--		size += sysfs_emit_at(buf, size, "2: %uMhz %s\n",
-+		size += sprintf(buf + size, "2: %uMhz %s\n",
- 					data->gfx_max_freq_limit/100,
- 					i == 2 ? "*" : "");
- 		break;
-@@ -1052,7 +1050,7 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
- 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &now);
-
- 		for (i = 0; i < mclk_table->count; i++)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 					i,
- 					mclk_table->entries[i].clk / 100,
- 					((mclk_table->entries[i].clk / 100)
-@@ -1067,10 +1065,10 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
- 			if (ret)
- 				return ret;
-
--			size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
--			size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
-+			size += sprintf(buf + size, "%s:\n", "OD_SCLK");
-+			size += sprintf(buf + size, "0: %10uMhz\n",
- 			(data->gfx_actual_soft_min_freq > 0) ? data->gfx_actual_soft_min_freq : min_freq);
--			size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
-+			size += sprintf(buf + size, "1: %10uMhz\n",
- 			(data->gfx_actual_soft_max_freq > 0) ? data->gfx_actual_soft_max_freq : max_freq);
- 		}
- 		break;
-@@ -1083,8 +1081,8 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
- 			if (ret)
- 				return ret;
-
--			size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
--			size += sysfs_emit_at(buf, size, "SCLK: %7uMHz %10uMHz\n",
-+			size += sprintf(buf + size, "%s:\n", "OD_RANGE");
-+			size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
- 				min_freq, max_freq);
- 		}
- 		break;
-diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
-index aceebf584225..611969bf4520 100644
---- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
-+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
-@@ -4914,8 +4914,6 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
- 	int size = 0;
- 	uint32_t i, now, clock, pcie_speed;
-
--	phm_get_sysfs_buf(&buf, &size);
--
- 	switch (type) {
- 	case PP_SCLK:
- 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &clock);
-@@ -4928,7 +4926,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
- 		now = i;
-
- 		for (i = 0; i < sclk_table->count; i++)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 					i, sclk_table->dpm_levels[i].value / 100,
- 					(i == now) ? "*" : "");
- 		break;
-@@ -4943,7 +4941,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
- 		now = i;
-
- 		for (i = 0; i < mclk_table->count; i++)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 					i, mclk_table->dpm_levels[i].value / 100,
- 					(i == now) ? "*" : "");
- 		break;
-@@ -4957,7 +4955,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
- 		now = i;
-
- 		for (i = 0; i < pcie_table->count; i++)
--			size += sysfs_emit_at(buf, size, "%d: %s %s\n", i,
-+			size += sprintf(buf + size, "%d: %s %s\n", i,
- 					(pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" :
- 					(pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" :
- 					(pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
-@@ -4965,32 +4963,32 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
- 		break;
- 	case OD_SCLK:
- 		if (hwmgr->od_enabled) {
--			size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
-+			size += sprintf(buf + size, "%s:\n", "OD_SCLK");
- 			for (i = 0; i < odn_sclk_table->num_of_pl; i++)
--				size += sysfs_emit_at(buf, size, "%d: %10uMHz %10umV\n",
-+				size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
- 					i, odn_sclk_table->entries[i].clock/100,
- 					odn_sclk_table->entries[i].vddc);
- 		}
- 		break;
- 	case OD_MCLK:
- 		if (hwmgr->od_enabled) {
--			size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK");
-+			size += sprintf(buf + size, "%s:\n", "OD_MCLK");
- 			for (i = 0; i < odn_mclk_table->num_of_pl; i++)
--				size += sysfs_emit_at(buf, size, "%d: %10uMHz %10umV\n",
-+				size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
- 					i, odn_mclk_table->entries[i].clock/100,
- 					odn_mclk_table->entries[i].vddc);
- 		}
- 		break;
- 	case OD_RANGE:
- 		if (hwmgr->od_enabled) {
--			size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
--			size += sysfs_emit_at(buf, size, "SCLK: %7uMHz %10uMHz\n",
-+			size += sprintf(buf + size, "%s:\n", "OD_RANGE");
-+			size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
- 				data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,
- 				hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
--			size += sysfs_emit_at(buf, size, "MCLK: %7uMHz %10uMHz\n",
-+			size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
- 				data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,
- 				hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
--			size += sysfs_emit_at(buf, size, "VDDC: %7umV %11umV\n",
-+			size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
- 				data->odn_dpm_table.min_vddc,
- 				data->odn_dpm_table.max_vddc);
- 		}
-diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
-index 8e28a8eecefc..03bf8f069222 100644
---- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
-+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
-@@ -1550,8 +1550,6 @@ static int smu8_print_clock_levels(struct pp_hwmgr *hwmgr,
- 	uint32_t i, now;
- 	int size = 0;
-
--	phm_get_sysfs_buf(&buf, &size);
--
- 	switch (type) {
- 	case PP_SCLK:
- 		now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
-@@ -1561,7 +1559,7 @@ static int smu8_print_clock_levels(struct pp_hwmgr *hwmgr,
- 				CURR_SCLK_INDEX);
-
- 		for (i = 0; i < sclk_table->count; i++)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 					i, sclk_table->entries[i].clk / 100,
- 					(i == now) ? "*" : "");
- 		break;
-@@ -1573,7 +1571,7 @@ static int smu8_print_clock_levels(struct pp_hwmgr *hwmgr,
- 				CURR_MCLK_INDEX);
-
- 		for (i = SMU8_NUM_NBPMEMORYCLOCK; i > 0; i--)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 					SMU8_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100,
- 					(SMU8_NUM_NBPMEMORYCLOCK-i == now) ? "*" : "");
- 		break;
-diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
-index c981fc2882f0..e6336654c565 100644
---- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
-+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
-@@ -4639,8 +4639,6 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
-
- 	int i, now, size = 0, count = 0;
-
--	phm_get_sysfs_buf(&buf, &size);
--
- 	switch (type) {
- 	case PP_SCLK:
- 		if (data->registry_data.sclk_dpm_key_disabled)
-@@ -4654,7 +4652,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
- 		else
- 			count = sclk_table->count;
- 		for (i = 0; i < count; i++)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 					i, sclk_table->dpm_levels[i].value / 100,
- 					(i == now) ? "*" : "");
- 		break;
-@@ -4665,7 +4663,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
- 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now);
-
- 		for (i = 0; i < mclk_table->count; i++)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 					i, mclk_table->dpm_levels[i].value / 100,
- 					(i == now) ? "*" : "");
- 		break;
-@@ -4676,7 +4674,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
- 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now);
-
- 		for (i = 0; i < soc_table->count; i++)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 					i, soc_table->dpm_levels[i].value / 100,
- 					(i == now) ? "*" : "");
- 		break;
-@@ -4688,7 +4686,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
- 				PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK, &now);
-
- 		for (i = 0; i < dcef_table->count; i++)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 					i, dcef_table->dpm_levels[i].value / 100,
- 					(dcef_table->dpm_levels[i].value / 100 == now) ?
- 					"*" : "");
-@@ -4702,7 +4700,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
- 			gen_speed = pptable->PcieGenSpeed[i];
- 			lane_width = pptable->PcieLaneCount[i];
-
--			size += sysfs_emit_at(buf, size, "%d: %s %s %s\n", i,
-+			size += sprintf(buf + size, "%d: %s %s %s\n", i,
- 					(gen_speed == 0) ? "2.5GT/s," :
- 					(gen_speed == 1) ? "5.0GT/s," :
- 					(gen_speed == 2) ? "8.0GT/s," :
-@@ -4721,34 +4719,34 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
-
- 	case OD_SCLK:
- 		if (hwmgr->od_enabled) {
--			size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
-+			size += sprintf(buf + size, "%s:\n", "OD_SCLK");
- 			podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
- 			for (i = 0; i < podn_vdd_dep->count; i++)
--				size += sysfs_emit_at(buf, size, "%d: %10uMhz %10umV\n",
-+				size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
- 					i, podn_vdd_dep->entries[i].clk / 100,
- 						podn_vdd_dep->entries[i].vddc);
- 		}
- 		break;
- 	case OD_MCLK:
- 		if (hwmgr->od_enabled) {
--			size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK");
-+			size += sprintf(buf + size, "%s:\n", "OD_MCLK");
- 			podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
- 			for (i = 0; i < podn_vdd_dep->count; i++)
--				size += sysfs_emit_at(buf, size, "%d: %10uMhz %10umV\n",
-+				size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
- 					i, podn_vdd_dep->entries[i].clk/100,
- 						podn_vdd_dep->entries[i].vddc);
- 		}
- 		break;
- 	case OD_RANGE:
- 		if (hwmgr->od_enabled) {
--			size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
--			size += sysfs_emit_at(buf, size, "SCLK: %7uMHz %10uMHz\n",
-+			size += sprintf(buf + size, "%s:\n", "OD_RANGE");
-+			size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
- 				data->golden_dpm_table.gfx_table.dpm_levels[0].value/100,
- 				hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
--			size += sysfs_emit_at(buf, size, "MCLK: %7uMHz %10uMHz\n",
-+			size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
- 				data->golden_dpm_table.mem_table.dpm_levels[0].value/100,
- 				hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
--			size += sysfs_emit_at(buf, size, "VDDC: %7umV %11umV\n",
-+			size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
- 				data->odn_dpm_table.min_vddc,
- 				data->odn_dpm_table.max_vddc);
- 		}
-diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
-index f7e783e1c888..a2f4d6773d45 100644
---- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
-+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
-@@ -2246,8 +2246,6 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
- 	int i, now, size = 0;
- 	struct pp_clock_levels_with_latency clocks;
-
--	phm_get_sysfs_buf(&buf, &size);
--
- 	switch (type) {
- 	case PP_SCLK:
- 		PP_ASSERT_WITH_CODE(
-@@ -2260,7 +2258,7 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
- 				"Attempt to get gfx clk levels Failed!",
- 				return -1);
- 		for (i = 0; i < clocks.num_levels; i++)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 				i, clocks.data[i].clocks_in_khz / 1000,
- 				(clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
- 		break;
-@@ -2276,7 +2274,7 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
- 				"Attempt to get memory clk levels Failed!",
- 				return -1);
- 		for (i = 0; i < clocks.num_levels; i++)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 				i, clocks.data[i].clocks_in_khz / 1000,
- 				(clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
- 		break;
-@@ -2294,7 +2292,7 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
- 				"Attempt to get soc clk levels Failed!",
- 				return -1);
- 		for (i = 0; i < clocks.num_levels; i++)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 				i, clocks.data[i].clocks_in_khz / 1000,
- 				(clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
- 		break;
-@@ -2312,7 +2310,7 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
- 				"Attempt to get dcef clk levels Failed!",
- 				return -1);
- 		for (i = 0; i < clocks.num_levels; i++)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 				i, clocks.data[i].clocks_in_khz / 1000,
- 				(clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
- 		break;
-diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
-index 03e63be4ee27..85d55ab4e369 100644
---- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
-+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
-@@ -3366,8 +3366,6 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
- 	int ret = 0;
- 	uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
-
--	phm_get_sysfs_buf(&buf, &size);
--
- 	switch (type) {
- 	case PP_SCLK:
- 		ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
-@@ -3376,13 +3374,13 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
- 				return ret);
-
- 		if (vega20_get_sclks(hwmgr, &clocks)) {
--			size += sysfs_emit_at(buf, size, "0: %uMhz * (DPM disabled)\n",
-+			size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
- 				now / 100);
- 			break;
- 		}
-
- 		for (i = 0; i < clocks.num_levels; i++)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 				i, clocks.data[i].clocks_in_khz / 1000,
- 				(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
- 		break;
-@@ -3394,13 +3392,13 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
- 				return ret);
-
- 		if (vega20_get_memclocks(hwmgr, &clocks)) {
--			size += sysfs_emit_at(buf, size, "0: %uMhz * (DPM disabled)\n",
-+			size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
- 				now / 100);
- 			break;
- 		}
-
- 		for (i = 0; i < clocks.num_levels; i++)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 				i, clocks.data[i].clocks_in_khz / 1000,
- 				(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
- 		break;
-@@ -3412,13 +3410,13 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
- 				return ret);
-
- 		if (vega20_get_socclocks(hwmgr, &clocks)) {
--			size += sysfs_emit_at(buf, size, "0: %uMhz * (DPM disabled)\n",
-+			size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
- 				now / 100);
- 			break;
- 		}
-
- 		for (i = 0; i < clocks.num_levels; i++)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 				i, clocks.data[i].clocks_in_khz / 1000,
- 				(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
- 		break;
-@@ -3430,7 +3428,7 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
- 				return ret);
-
- 		for (i = 0; i < fclk_dpm_table->count; i++)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 				i, fclk_dpm_table->dpm_levels[i].value,
- 				fclk_dpm_table->dpm_levels[i].value == (now / 100) ? "*" : "");
- 		break;
-@@ -3442,13 +3440,13 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
- 				return ret);
-
- 		if (vega20_get_dcefclocks(hwmgr, &clocks)) {
--			size += sysfs_emit_at(buf, size, "0: %uMhz * (DPM disabled)\n",
-+			size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
- 				now / 100);
- 			break;
- 		}
-
- 		for (i = 0; i < clocks.num_levels; i++)
--			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
- 				i, clocks.data[i].clocks_in_khz / 1000,
- 				(clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
- 		break;
-@@ -3462,7 +3460,7 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
- 			gen_speed = pptable->PcieGenSpeed[i];
- 			lane_width = pptable->PcieLaneCount[i];
-
--			size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
-+			size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
- 					(gen_speed == 0) ? "2.5GT/s," :
- 					(gen_speed == 1) ? "5.0GT/s," :
- 					(gen_speed == 2) ? "8.0GT/s," :
-@@ -3483,18 +3481,18 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
- 	case OD_SCLK:
- 		if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
- 		    od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
--			size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
--			size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
-+			size += sprintf(buf + size, "%s:\n", "OD_SCLK");
-+			size += sprintf(buf + size, "0: %10uMhz\n",
- 				od_table->GfxclkFmin);
--			size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
-+			size += sprintf(buf + size, "1: %10uMhz\n",
- 				od_table->GfxclkFmax);
- 		}
- 		break;
-
- 	case OD_MCLK:
- 		if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
--			size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK");
--			size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
-+			size += sprintf(buf + size, "%s:\n", "OD_MCLK");
-+			size += sprintf(buf + size, "1: %10uMhz\n",
- 				od_table->UclkFmax);
- 		}
-
-@@ -3507,14 +3505,14 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
- 		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
- 		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
- 		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
--			size += sysfs_emit_at(buf, size, "%s:\n", "OD_VDDC_CURVE");
--			size += sysfs_emit_at(buf, size, "0: %10uMhz %10dmV\n",
-+			size += sprintf(buf + size, "%s:\n", "OD_VDDC_CURVE");
-+			size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
- 				od_table->GfxclkFreq1,
- 				od_table->GfxclkVolt1 / VOLTAGE_SCALE);
--			size += sysfs_emit_at(buf, size, "1: %10uMhz %10dmV\n",
-+			size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
- 				od_table->GfxclkFreq2,
- 				od_table->GfxclkVolt2 / VOLTAGE_SCALE);
--			size += sysfs_emit_at(buf, size, "2: %10uMhz %10dmV\n",
-+			size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
- 				od_table->GfxclkFreq3,
- 				od_table->GfxclkVolt3 / VOLTAGE_SCALE);
- 		}
-@@ -3522,17 +3520,17 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
- 		break;
-
- 	case OD_RANGE:
--		size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
-+		size += sprintf(buf + size, "%s:\n", "OD_RANGE");
-
- 		if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
- 		    od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
--			size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
-+			size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
- 				od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
- 				od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
- 		}
-
- 		if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
--			size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
-+			size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
- 				od8_settings[OD8_SETTING_UCLK_FMAX].min_value,
- 				od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
- 		}
-@@ -3543,22 +3541,22 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
- 		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
- 		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
- 		    od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
--			size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
-+			size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
- 				od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
- 				od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
--			size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
-+			size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
- 				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
- 				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
--			size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
-+			size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
- 				od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
- 				od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
--			size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
-+			size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
- 				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
- 				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
--			size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
-+			size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
- 				od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
- 				od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
--			size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
-+			size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
- 				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
- 				od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
- 		}
---
-2.31.1
-