diff --git a/linux-tkg-patches/6.1/0012-misc-additions.patch b/linux-tkg-patches/6.1/0012-misc-additions.patch
index 2bc1e18..36cdf93 100644
--- a/linux-tkg-patches/6.1/0012-misc-additions.patch
+++ b/linux-tkg-patches/6.1/0012-misc-additions.patch
@@ -426,99 +426,3 @@ index 4bf4ea6cbb5eee..4850dafbaa05fb 100644
  }
 
  /* ---- Socket functions ---- */
-From 50e6a66675f6c9835d4f1d4f8c947d1699ce8e24 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 7 Oct 2022 09:51:13 +0200
-Subject: [PATCH 4/5] drm/sched: add DRM_SCHED_FENCE_DONT_PIPELINE flag
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Setting this flag on a scheduler fence prevents pipelining of jobs
-depending on this fence. In other words we always insert a full CPU
-round trip before dependen jobs are pushed to the pipeline.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/scheduler/sched_entity.c | 3 ++-
- include/drm/gpu_scheduler.h              | 9 +++++++++
- 2 files changed, 11 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c
-index 6b25b2f4f5a3..6137537aaea4 100644
---- a/drivers/gpu/drm/scheduler/sched_entity.c
-+++ b/drivers/gpu/drm/scheduler/sched_entity.c
-@@ -385,7 +385,8 @@ static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity)
- 	}
-
- 	s_fence = to_drm_sched_fence(fence);
--	if (s_fence && s_fence->sched == sched) {
-+	if (s_fence && s_fence->sched == sched &&
-+	    !test_bit(DRM_SCHED_FENCE_DONT_PIPELINE, &fence->flags)) {
-
- 		/*
- 		 * Fence is from the same scheduler, only need to wait for
-diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
-index addb135eeea6..289a33e80639 100644
---- a/include/drm/gpu_scheduler.h
-+++ b/include/drm/gpu_scheduler.h
-@@ -32,6 +32,15 @@
-
- #define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000)
-
-+/**
-+ * DRM_SCHED_FENCE_DONT_PIPELINE - Prefent dependency pipelining
-+ *
-+ * Setting this flag on a scheduler fence prevents pipelining of jobs depending
-+ * on this fence. In other words we always insert a full CPU round trip before
-+ * dependen jobs are pushed to the hw queue.
-+ */
-+#define DRM_SCHED_FENCE_DONT_PIPELINE	DMA_FENCE_FLAG_USER_BITS
-+
- struct drm_gem_object;
-
- struct drm_gpu_scheduler;
---
-2.25.1
-
-From e15e1601fba660124acd7ad41b6f61d46a1c4835 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 7 Oct 2022 10:59:58 +0200
-Subject: [PATCH 5/5] drm/amdgpu: use DRM_SCHED_FENCE_DONT_PIPELINE for VM
- updates
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Make sure that we always have a CPU round trip to let the submission
-code correctly decide if a TLB flush is necessary or not.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
-index 1fd3cbca20a2..c7bf189d50de 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
-@@ -115,8 +115,15 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,
- 		amdgpu_bo_fence(p->vm->root.bo, f, true);
- 	}
-
--	if (fence && !p->immediate)
-+	if (fence && !p->immediate) {
-+		/*
-+		 * Most hw generations now have a separate queue for page table
-+		 * updates, but when the queue is shared with userspace we need
-+		 * the extra CPU round trip to correctly flush the TLB.
-+		 */
-+		set_bit(DRM_SCHED_FENCE_DONT_PIPELINE, &f->flags);
- 		swap(*fence, f);
-+	}
- 	dma_fence_put(f);
- 	return 0;
-
---
-2.25.1
-