From 2405876c0b4201a264e465e675a74408a0ed8995 Mon Sep 17 00:00:00 2001
From: Tk-Glitch <ti3nou@gmail.com>
Date: Sat, 26 Jun 2021 14:24:32 +0200
Subject: [PATCH] linux512-tkg: While we wait for 5.12.14 to hopefully revert
 those, let's do it on our end.

https://lists.freedesktop.org/archives/amd-gfx/2021-June/065575.html
https://bugzilla.kernel.org/show_bug.cgi?id=213561
https://gitlab.freedesktop.org/drm/amd/-/issues/1632
---
 PKGBUILD                                      |  4 +-
 .../5.12/0012-misc-additions.patch            | 54 +++++++++++++++++++
 2 files changed, 56 insertions(+), 2 deletions(-)

diff --git a/PKGBUILD b/PKGBUILD
index adc76c6..3cc5861 100644
--- a/PKGBUILD
+++ b/PKGBUILD
@@ -59,7 +59,7 @@ else
 fi
 pkgname=("${pkgbase}" "${pkgbase}-headers")
 pkgver="${_basekernel}"."${_sub}"
-pkgrel=170
+pkgrel=171
 pkgdesc='Linux-tkg'
 arch=('x86_64') # no i686 in here
 url="http://www.kernel.org/"
@@ -473,7 +473,7 @@ case $_basever in
             '9fad4a40449e09522899955762c8928ae17f4cdaa16e01239fd12592e9d58177'
             'a557b342111849a5f920bbe1c129f3ff1fc1eff62c6bd6685e0972fc88e39911'
             '6325b3d6972725e41adbaf5e2db19a040dbf0856046cecc1c4d6786a064d04ff'
-            '7fb1104c167edb79ec8fbdcde97940ed0f806aa978bdd14d0c665a1d76d25c24'
+            'f080c23c3888ab1d952863417f5697d7dd3ab29e274a5df8ec75aaa20b228744'
             'b1c6599d0e1ac9b66898d652ed99dae3fb8676d840a43ffa920a78d96e0521be'
             'b0319a7dff9c48b2f3e3d3597ee154bf92223149a633a8b7ce4026252db86da6')
 	;;
diff --git a/linux-tkg-patches/5.12/0012-misc-additions.patch b/linux-tkg-patches/5.12/0012-misc-additions.patch
index 2e058a6..68a2659 100644
--- a/linux-tkg-patches/5.12/0012-misc-additions.patch
+++ b/linux-tkg-patches/5.12/0012-misc-additions.patch
@@ -131,3 +131,57 @@ index 2c7171e0b0010..85de313ddec29 100644
  	select CPU_FREQ_GOV_CONSERVATIVE
  	select CPU_FREQ_GOV_PERFORMANCE
  	help
+Revert "drm/amdgpu/gfx9: fix the doorbell missing when in CGPG issue."
+Revert "drm/amdgpu/gfx10: enlarge CP_MEC_DOORBELL_RANGE_UPPER to cover full doorbell."
+
+This revert commits:
+a3b4cfb09aa9e73cc48caff77efc161a396aeddb.
+feae47198886d0df7b43876916a0e4366f159b45
+
+Reason for revert: side effect of enlarging CP_MEC_DOORBELL_RANGE may
+cause some APUs fail to enter gfxoff in certain user cases.
+
+Signed-off-by: Yifan Zhang <yifan1.zhang at amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +-----
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 6 +-----
+ 2 files changed, 2 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 7bfe6f9d3a52..15ae9e33b925 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -6974,12 +6974,8 @@ static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
+ 	if (ring->use_doorbell) {
+ 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
+ 			(adev->doorbell_index.kiq * 2) << 2);
+-		/* If GC has entered CGPG, ringing doorbell > first page doesn't
+-		 * wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround
+-		 * this issue.
+-		 */
+ 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
+-			(adev->doorbell.size - 4));
++			(adev->doorbell_index.userqueue_end * 2) << 2);
+ 	}
+ 
+ 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 922420a2c102..044076ec1d03 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -3675,12 +3675,8 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
+ 	if (ring->use_doorbell) {
+ 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
+ 					(adev->doorbell_index.kiq * 2) << 2);
+-		/* If GC has entered CGPG, ringing doorbell > first page doesn't
+-		 * wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround
+-		 * this issue.
+-		 */
+ 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
+-					(adev->doorbell.size - 4));
++					(adev->doorbell_index.userqueue_end * 2) << 2);
+ 	}
+ 
+ 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
+-- 
+2.25.1