diff --git a/PKGBUILD b/PKGBUILD index 0179b1e..cd04d11 100644 --- a/PKGBUILD +++ b/PKGBUILD @@ -835,7 +835,7 @@ case $_basever in #'9fad4a40449e09522899955762c8928ae17f4cdaa16e01239fd12592e9d58177' #'a557b342111849a5f920bbe1c129f3ff1fc1eff62c6bd6685e0972fc88e39911' #'766658d5ec9cf204635f735a8927854991d0133b2e34bdcd9ca36d7e34817e27' - '7b487db1dda2e7b9fd2465118b4086cbe86efc695f70a4dce13c09fbe8e7f946' + '213ecf1ba59dc87ed1844c3473d575b85ffe3a567f86735e8c6239c92dbbb493' '1b656ad96004f27e9dc63d7f430b50d5c48510d6d4cd595a81c24b21adb70313' 'b0319a7dff9c48b2f3e3d3597ee154bf92223149a633a8b7ce4026252db86da6') ;; diff --git a/linux-tkg-patches/5.19/0012-misc-additions.patch b/linux-tkg-patches/5.19/0012-misc-additions.patch index 244caec..6591434 100644 --- a/linux-tkg-patches/5.19/0012-misc-additions.patch +++ b/linux-tkg-patches/5.19/0012-misc-additions.patch @@ -34,74 +34,6 @@ index bf7ecab5d9e5..142e9dae2837 100644 -- cgit v1.2.3-1-gf6bb5 -From e437ac931e89629f952ce9f3f9dfe45ac505cd0d Mon Sep 17 00:00:00 2001 -From: Joshua Ashton -Date: Tue, 5 Jan 2021 19:46:01 +0000 -Subject: [PATCH] drm/amdgpu: don't limit gtt size on apus - -Since commit 24562523688b ("Revert "drm/amd/amdgpu: set gtt size -according to system memory size only""), the GTT size was limited by -3GiB or VRAM size. - -This is problematic on APU systems with a small carveout -(notably, those that ship with dGPUs where this is unconfigurable), -where the carveout size can be as low as 128MiB. - -This makes it so the GTT size heuristic always uses 3/4ths of -the system memory size on APUs (limiting the size by 3GiB/VRAM size -only on devices with dedicated video memory). - -Fixes: 24562523688b ("Revert drm/amd/amdgpu: set gtt size according to -system memory size only") - -Signed-off-by: Joshua Ashton ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +++-- - drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 12 +++++++++--- - 2 files changed, 12 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c -index 72efd579ec5e..a5a41e9272d6 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c -@@ -192,8 +192,9 @@ module_param_named(gartsize, amdgpu_gart_size, uint, 0600); - - /** - * DOC: gttsize (int) -- * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, -- * otherwise 3/4 RAM size). -+ * Restrict the size of GTT domain in MiB for testing. The default is -1 (On APUs this is 3/4th -+ * of the system memory; on dGPUs this is 3GiB or VRAM sized, whichever is bigger, -+ * with an upper bound of 3/4th of system memory. - */ - MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); - module_param_named(gttsize, amdgpu_gtt_size, int, 0600); -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c -index 4d8f19ab1014..294f26f4f310 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c -@@ -1865,9 +1865,15 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) - struct sysinfo si; - - si_meminfo(&si); -- gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), -- adev->gmc.mc_vram_size), -- ((uint64_t)si.totalram * si.mem_unit * 3/4)); -+ gtt_size = (uint64_t)si.totalram * si.mem_unit * 3/4; -+ /* If we have dedicated memory, limit our GTT size to -+ * 3GiB or VRAM size, whichever is bigger -+ */ -+ if (!(adev->flags & AMD_IS_APU)) { -+ gtt_size = min(max(AMDGPU_DEFAULT_GTT_SIZE_MB << 20, -+ adev->gmc.mc_vram_size), -+ gtt_size); -+ } - } - else - gtt_size = (uint64_t)amdgpu_gtt_size << 20; --- -2.30.0 - From f7f49141a5dbe9c99d78196b58c44307fb2e6be3 Mon Sep 17 00:00:00 2001 From: Tk-Glitch Date: Wed, 3 Feb 2021 11:20:12 +0200 @@ -132,107 +64,3 @@ index 2c7171e0b0010..85de313ddec29 100644 select CPU_FREQ_GOV_PERFORMANCE help -https://lore.kernel.org/lkml/20210819004305.20203-1-deepak.sharma@amd.com/ - -From: Deepak Sharma -To: -Cc: "Rafael J. Wysocki" , - Len Brown , Pavel Machek , - Thomas Gleixner , - "Ingo Molnar" , Borislav Petkov , - "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" - , "H. Peter Anvin" , - "open list:SUSPEND TO RAM" , - "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" - -Subject: [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs -Date: Wed, 18 Aug 2021 17:43:05 -0700 -Message-ID: <20210819004305.20203-1-deepak.sharma@amd.com> (raw) - -AMD CPU which support C3 shares cache. Its not necessary to flush the -caches in software before entering C3. This will cause performance drop -for the cores which share some caches. ARB_DIS is not used with current -AMD C state implementation. So set related flags correctly. - -Signed-off-by: Deepak Sharma ---- - arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - -diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c -index 7de599eba7f0..62a5986d625a 100644 ---- a/arch/x86/kernel/acpi/cstate.c -+++ b/arch/x86/kernel/acpi/cstate.c -@@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, - */ - flags->bm_control = 0; - } -+ if (c->x86_vendor == X86_VENDOR_AMD) { -+ /* -+ * For all AMD CPUs that support C3, caches should not be -+ * flushed by software while entering C3 type state. Set -+ * bm->check to 1 so that kernel doesn't need to execute -+ * cache flush operation. -+ */ -+ flags->bm_check = 1; -+ /* -+ * In current AMD C state implementation ARB_DIS is no longer -+ * used. So set bm_control to zero to indicate ARB_DIS is not -+ * required while entering C3 type state. -+ */ -+ flags->bm_control = 0; -+ } - } - EXPORT_SYMBOL(acpi_processor_power_init_bm_check); - --- -2.25.1 - -diff --git a/fs/f2fs/namei.c b/fs/f2fs/namei.c -index c549acb52ac4..a841abe6a071 100644 ---- a/fs/f2fs/namei.c -+++ b/fs/f2fs/namei.c -@@ -89,8 +89,6 @@ static struct inode *f2fs_new_inode(struct user_namespace *mnt_userns, - if (test_opt(sbi, INLINE_XATTR)) - set_inode_flag(inode, FI_INLINE_XATTR); - -- if (test_opt(sbi, INLINE_DATA) && f2fs_may_inline_data(inode)) -- set_inode_flag(inode, FI_INLINE_DATA); - if (f2fs_may_inline_dentry(inode)) - set_inode_flag(inode, FI_INLINE_DENTRY); - -@@ -107,10 +105,6 @@ static struct inode *f2fs_new_inode(struct user_namespace *mnt_userns, - - f2fs_init_extent_tree(inode, NULL); - -- stat_inc_inline_xattr(inode); -- stat_inc_inline_inode(inode); -- stat_inc_inline_dir(inode); -- - F2FS_I(inode)->i_flags = - f2fs_mask_flags(mode, F2FS_I(dir)->i_flags & F2FS_FL_INHERITED); - -@@ -127,6 +121,14 @@ static struct inode *f2fs_new_inode(struct user_namespace *mnt_userns, - set_compress_context(inode); - } - -+ /* Should enable inline_data after compression set */ -+ if (test_opt(sbi, INLINE_DATA) && f2fs_may_inline_data(inode)) -+ set_inode_flag(inode, FI_INLINE_DATA); -+ -+ stat_inc_inline_xattr(inode); -+ stat_inc_inline_inode(inode); -+ stat_inc_inline_dir(inode); -+ - f2fs_set_inode_flags(inode); - - trace_f2fs_new_inode(inode, 0); -@@ -325,6 +327,8 @@ static void set_compress_inode(struct f2fs_sb_info *sbi, struct inode *inode, - if (!is_extension_exist(name, ext[i], false)) - continue; - -+ /* Do not use inline_data with compression */ -+ clear_inode_flag(inode, FI_INLINE_DATA); - set_compress_context(inode); - return; - }