diff --git a/linux-tkg-patches/6.7/0012-misc-additions.patch b/linux-tkg-patches/6.7/0012-misc-additions.patch index eb65852..b8044e0 100644 --- a/linux-tkg-patches/6.7/0012-misc-additions.patch +++ b/linux-tkg-patches/6.7/0012-misc-additions.patch @@ -258,3 +258,322 @@ index 7f7b3981777377..6acf11fafb22e5 100644 .sta_add_debugfs = ath11k_debugfs_sta_op_add, #endif +From 431ea67ac560bcd521c0ef8901039ba3bf278c84 Mon Sep 17 00:00:00 2001 +From: Evan Quan +Date: Tue, 13 Jun 2023 10:50:58 +0800 +Subject: [PATCH] drm/amd/pm: fix the power limit setting for SMU13.0.0 + +Prototype for test purpose only. + +Signed-off-by: Evan Quan +--- + .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 50 ++++++++++++++++++- + 1 file changed, 49 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +index dbe9b29a287e..a15bb4de4e70 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +@@ -2024,6 +2024,54 @@ static int smu_v13_0_0_get_power_limit(struct smu_context *smu, + return 0; + } + ++static int smu_v13_0_0_set_power_limit(struct smu_context *smu, ++ enum smu_ppt_limit_type limit_type, ++ uint32_t limit) ++{ ++ PPTable_t *pptable = smu->smu_table.driver_pptable; ++ SkuTable_t *skutable = &pptable->SkuTable; ++ uint32_t msg_limt = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC]; ++ struct smu_table_context *table_context = &smu->smu_table; ++ OverDriveTableExternal_t *od_table = ++ (OverDriveTableExternal_t *)table_context->overdrive_table; ++ int ret = 0; ++ ++ if (limit_type != SMU_DEFAULT_PPT_LIMIT) ++ return -EINVAL; ++ ++ if (limit <= msg_limt) { ++ if (smu->current_power_limit > msg_limt) { ++ /* revert previous OD settings */ ++ od_table->OverDriveTable.Ppt = 0; ++ od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT; ++ ++ ret = smu_v13_0_0_upload_overdrive_table(smu, od_table); ++ if (ret) { ++ dev_err(smu->adev->dev, "Failed to upload overdrive table!\n"); ++ return ret; ++ } ++ } ++ return smu_v13_0_set_power_limit(smu, limit_type, limit); ++ } ++ ++ ret = smu_v13_0_set_power_limit(smu, limit_type, smu->default_power_limit); ++ if (ret) ++ return ret; ++ ++ od_table->OverDriveTable.Ppt = (limit * 100) / smu->default_power_limit - 100; ++ od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT; ++ ++ ret = smu_v13_0_0_upload_overdrive_table(smu, od_table); ++ if (ret) { ++ dev_err(smu->adev->dev, "Failed to upload overdrive table!\n"); ++ return ret; ++ } ++ ++ smu->current_power_limit = limit; ++ ++ return 0; ++} ++ + static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu, + char *buf) + { +@@ -2702,7 +2750,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { + .set_fan_control_mode = smu_v13_0_set_fan_control_mode, + .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost, + .get_power_limit = smu_v13_0_0_get_power_limit, +- .set_power_limit = smu_v13_0_set_power_limit, ++ .set_power_limit = smu_v13_0_0_set_power_limit, + .set_power_source = smu_v13_0_set_power_source, + .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode, + .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode, +-- +2.34.1 + +From 3cfb591e23181791195a74efe2e9065e0d4bd201 Mon Sep 17 00:00:00 2001 +From: Etienne JUVIGNY +Date: Mon, 15 Jan 2024 19:09:39 +0100 +Subject: Revert: drm/amd/pm: fix the high voltage and temperature issue + +This was supposed to fix the high voltage and temperature issue after the driver is unloaded on smu 13.0.0, +smu 13.0.7 and smu 13.0.10, but introduced an arguably more annoying issue. Let's revert it until a proper fix is offered. + +Fixes rdna3 shutdown/reboot hang. + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index 93cf73d6f..960966f4b 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -4050,23 +4050,13 @@ int amdgpu_device_init(struct amdgpu_device *adev, + } + } + } else { +- switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { +- case IP_VERSION(13, 0, 0): +- case IP_VERSION(13, 0, 7): +- case IP_VERSION(13, 0, 10): +- r = psp_gpu_reset(adev); +- break; +- default: +- tmp = amdgpu_reset_method; +- /* It should do a default reset when loading or reloading the driver, +- * regardless of the module parameter reset_method. +- */ +- amdgpu_reset_method = AMD_RESET_METHOD_NONE; +- r = amdgpu_asic_reset(adev); +- amdgpu_reset_method = tmp; +- break; +- } +- ++ tmp = amdgpu_reset_method; ++ /* It should do a default reset when loading or reloading the driver, ++ * regardless of the module parameter reset_method. ++ */ ++ amdgpu_reset_method = AMD_RESET_METHOD_NONE; ++ r = amdgpu_asic_reset(adev); ++ amdgpu_reset_method = tmp; + if (r) { + dev_err(adev->dev, "asic reset on init failed\n"); + goto failed; +diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +index e1a5ee911..308ebeb43 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +@@ -733,7 +733,7 @@ static int smu_early_init(void *handle) + smu->adev = adev; + smu->pm_enabled = !!amdgpu_dpm; + smu->is_apu = false; +- smu->smu_baco.state = SMU_BACO_STATE_NONE; ++ smu->smu_baco.state = SMU_BACO_STATE_EXIT; + smu->smu_baco.platform_support = false; + smu->user_dpm_profile.fan_mode = -1; + +@@ -1753,31 +1753,10 @@ static int smu_smc_hw_cleanup(struct smu_context *smu) + return 0; + } + +-static int smu_reset_mp1_state(struct smu_context *smu) +-{ +- struct amdgpu_device *adev = smu->adev; +- int ret = 0; +- +- if ((!adev->in_runpm) && (!adev->in_suspend) && +- (!amdgpu_in_reset(adev))) +- switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { +- case IP_VERSION(13, 0, 0): +- case IP_VERSION(13, 0, 7): +- case IP_VERSION(13, 0, 10): +- ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); +- break; +- default: +- break; +- } +- +- return ret; +-} +- + static int smu_hw_fini(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct smu_context *smu = adev->powerplay.pp_handle; +- int ret; + + if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) + return 0; +@@ -1795,15 +1774,7 @@ static int smu_hw_fini(void *handle) + + adev->pm.dpm_enabled = false; + +- ret = smu_smc_hw_cleanup(smu); +- if (ret) +- return ret; +- +- ret = smu_reset_mp1_state(smu); +- if (ret) +- return ret; +- +- return 0; ++ return smu_smc_hw_cleanup(smu); + } + + static void smu_late_fini(void *handle) +diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +index f8b2e6cc2..e8329d157 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h ++++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +@@ -419,7 +419,6 @@ enum smu_reset_mode { + enum smu_baco_state { + SMU_BACO_STATE_ENTER = 0, + SMU_BACO_STATE_EXIT, +- SMU_BACO_STATE_NONE, + }; + + struct smu_baco_context { +diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +index 95cb91971..cc02f979e 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h ++++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +@@ -299,7 +299,5 @@ int smu_v13_0_update_pcie_parameters(struct smu_context *smu, + uint8_t pcie_gen_cap, + uint8_t pcie_width_cap); + +-int smu_v13_0_disable_pmfw_state(struct smu_context *smu); +- + #endif + #endif +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +index cf1b84060..a49e5adf7 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +@@ -2477,16 +2477,3 @@ int smu_v13_0_update_pcie_parameters(struct smu_context *smu, + + return 0; + } +- +-int smu_v13_0_disable_pmfw_state(struct smu_context *smu) +-{ +- int ret; +- struct amdgpu_device *adev = smu->adev; +- +- WREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff), 0); +- +- ret = RREG32_PCIE(MP1_Public | +- (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); +- +- return ret == 0 ? 0 : -EINVAL; +-} +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +index 82c4e1f1c..2ba77b1d1 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +@@ -2574,20 +2574,14 @@ static int smu_v13_0_0_baco_enter(struct smu_context *smu) + static int smu_v13_0_0_baco_exit(struct smu_context *smu) + { + struct amdgpu_device *adev = smu->adev; +- int ret; + + if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { + /* Wait for PMFW handling for the Dstate change */ + usleep_range(10000, 11000); +- ret = smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); ++ return smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); + } else { +- ret = smu_v13_0_baco_exit(smu); ++ return smu_v13_0_baco_exit(smu); + } +- +- if (!ret) +- adev->gfx.is_poweron = false; +- +- return ret; + } + + static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu) +@@ -2772,13 +2766,7 @@ static int smu_v13_0_0_set_mp1_state(struct smu_context *smu, + + switch (mp1_state) { + case PP_MP1_STATE_UNLOAD: +- ret = smu_cmn_send_smc_msg_with_param(smu, +- SMU_MSG_PrepareMp1ForUnload, +- 0x55, NULL); +- +- if (!ret && smu->smu_baco.state == SMU_BACO_STATE_EXIT) +- ret = smu_v13_0_disable_pmfw_state(smu); +- ++ ret = smu_cmn_set_mp1_state(smu, mp1_state); + break; + default: + /* Ignore others */ +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +index 81eafed76..19c1289d0 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +@@ -2499,13 +2499,7 @@ static int smu_v13_0_7_set_mp1_state(struct smu_context *smu, + + switch (mp1_state) { + case PP_MP1_STATE_UNLOAD: +- ret = smu_cmn_send_smc_msg_with_param(smu, +- SMU_MSG_PrepareMp1ForUnload, +- 0x55, NULL); +- +- if (!ret && smu->smu_baco.state == SMU_BACO_STATE_EXIT) +- ret = smu_v13_0_disable_pmfw_state(smu); +- ++ ret = smu_cmn_set_mp1_state(smu, mp1_state); + break; + default: + /* Ignore others */ +@@ -2531,20 +2525,14 @@ static int smu_v13_0_7_baco_enter(struct smu_context *smu) + static int smu_v13_0_7_baco_exit(struct smu_context *smu) + { + struct amdgpu_device *adev = smu->adev; +- int ret; + + if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { + /* Wait for PMFW handling for the Dstate change */ + usleep_range(10000, 11000); +- ret = smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); ++ return smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); + } else { +- ret = smu_v13_0_baco_exit(smu); ++ return smu_v13_0_baco_exit(smu); + } +- +- if (!ret) +- adev->gfx.is_poweron = false; +- +- return ret; + } + + static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu)