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linux514: Update Project C patchset to v5.14-r1 - https://gitlab.com/alfredchen/projectc/-/blob/master/5.14/prjc_v5.14-r1.patch

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- Update defconfig to 5.14.1.arch1-1 - https://github.com/archlinux/svntogit-packages/commits/packages/linux/trunk/config

 - Add `x86/ACPI/State: Optimize C3 entry on AMD CPUs` patch to misc-additions - https://lore.kernel.org/lkml/20210819004305.20203-1-deepak.sharma@amd.com/
This commit is contained in:
Tk-Glitch
2021-09-08 13:09:47 +02:00
parent 0eaf5ba619
commit ffa5efada2
5 changed files with 210 additions and 80 deletions
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85
linux-tkg-patches/5.14/0009-prjc_v5.14-r0.patch → linux-tkg-patches/5.14/0009-prjc_v5.14-r1.patch
View File

@@ -463,6 +463,19 @@ index 562f2ef8d157..177b63db4ce0 100644
.tasks = LIST_HEAD_INIT(init_task.tasks),
#ifdef CONFIG_SMP
.pushable_tasks = PLIST_NODE_INIT(init_task.pushable_tasks, MAX_PRIO),
diff --git a/kernel/Kconfig.preempt b/kernel/Kconfig.preempt
index 5876e30c5740..7594d0a31869 100644
--- a/kernel/Kconfig.preempt
+++ b/kernel/Kconfig.preempt
@@ -102,7 +102,7 @@ config PREEMPT_DYNAMIC
config SCHED_CORE
bool "Core Scheduling for SMT"
- depends on SCHED_SMT
+ depends on SCHED_SMT && !SCHED_ALT
help
This option permits Core Scheduling, a means of coordinated task
selection across SMT siblings. When enabled -- see
diff --git a/kernel/cgroup/cpuset.c b/kernel/cgroup/cpuset.c
index adb5190c4429..8c02bce63146 100644
--- a/kernel/cgroup/cpuset.c
@@ -646,10 +659,10 @@ index 978fcfca5871..0425ee149b4d 100644
obj-$(CONFIG_CPU_FREQ_GOV_SCHEDUTIL) += cpufreq_schedutil.o
diff --git a/kernel/sched/alt_core.c b/kernel/sched/alt_core.c
new file mode 100644
index 000000000000..5df1157a597c
index 000000000000..900889c838ea
--- /dev/null
+++ b/kernel/sched/alt_core.c
@@ -0,0 +1,7224 @@
@@ -0,0 +1,7248 @@
+/*
+ * kernel/sched/alt_core.c
+ *
@@ -719,7 +732,7 @@ index 000000000000..5df1157a597c
+#define sched_feat(x) (0)
+#endif /* CONFIG_SCHED_DEBUG */
+
+#define ALT_SCHED_VERSION "v5.14-r0"
+#define ALT_SCHED_VERSION "v5.14-r1"
+
+/* rt_prio(prio) defined in include/linux/sched/rt.h */
+#define rt_task(p) rt_prio((p)->prio)
@@ -1144,6 +1157,30 @@ index 000000000000..5df1157a597c
+ raw_spin_unlock_irqrestore(&rq->lock, rf->flags);
+}
+
+void raw_spin_rq_lock_nested(struct rq *rq, int subclass)
+{
+ raw_spinlock_t *lock;
+
+ /* Matches synchronize_rcu() in __sched_core_enable() */
+ preempt_disable();
+
+ for (;;) {
+ lock = __rq_lockp(rq);
+ raw_spin_lock_nested(lock, subclass);
+ if (likely(lock == __rq_lockp(rq))) {
+ /* preempt_count *MUST* be > 1 */
+ preempt_enable_no_resched();
+ return;
+ }
+ raw_spin_unlock(lock);
+ }
+}
+
+void raw_spin_rq_unlock(struct rq *rq)
+{
+ raw_spin_unlock(rq_lockp(rq));
+}
+
+/*
+ * RQ-clock updating methods:
+ */
@@ -1768,10 +1805,10 @@ index 000000000000..5df1157a597c
+}
+#endif /* CONFIG_SCHED_HRTICK */
+
+static inline int __normal_prio(int policy, int rt_prio, int nice)
+static inline int __normal_prio(int policy, int rt_prio, int static_prio)
+{
+ return rt_policy(policy) ? (MAX_RT_PRIO - 1 - rt_prio) :
+ NICE_TO_PRIO(nice) + MAX_PRIORITY_ADJ;
+ static_prio + MAX_PRIORITY_ADJ;
+}
+
+/*
@@ -1783,7 +1820,7 @@ index 000000000000..5df1157a597c
+ */
+static inline int normal_prio(struct task_struct *p)
+{
+ return __normal_prio(p->policy, p->rt_priority, PRIO_TO_NICE(p->static_prio));
+ return __normal_prio(p->policy, p->rt_priority, p->static_prio);
+}
+
+/*
@@ -5707,7 +5744,7 @@ index 000000000000..5df1157a597c
+
+ p->sched_reset_on_fork = reset_on_fork;
+
+ newprio = __normal_prio(policy, attr->sched_priority, attr->sched_nice);
+ newprio = __normal_prio(policy, attr->sched_priority, NICE_TO_PRIO(attr->sched_nice));
+ if (pi) {
+ /*
+ * Take priority boosted tasks into account. If the new
@@ -7913,10 +7950,10 @@ index 000000000000..1212a031700e
+{}
diff --git a/kernel/sched/alt_sched.h b/kernel/sched/alt_sched.h
new file mode 100644
index 000000000000..7a48809550bf
index 000000000000..f03af9ab9123
--- /dev/null
+++ b/kernel/sched/alt_sched.h
@@ -0,0 +1,662 @@
@@ -0,0 +1,692 @@
+#ifndef ALT_SCHED_H
+#define ALT_SCHED_H
+
@@ -8362,6 +8399,36 @@ index 000000000000..7a48809550bf
+ return rq;
+}
+
+extern void raw_spin_rq_lock_nested(struct rq *rq, int subclass);
+extern void raw_spin_rq_unlock(struct rq *rq);
+
+static inline raw_spinlock_t *__rq_lockp(struct rq *rq)
+{
+ return &rq->lock;
+}
+
+static inline raw_spinlock_t *rq_lockp(struct rq *rq)
+{
+ return __rq_lockp(rq);
+}
+
+static inline void raw_spin_rq_lock(struct rq *rq)
+{
+ raw_spin_rq_lock_nested(rq, 0);
+}
+
+static inline void raw_spin_rq_lock_irq(struct rq *rq)
+{
+ local_irq_disable();
+ raw_spin_rq_lock(rq);
+}
+
+static inline void raw_spin_rq_unlock_irq(struct rq *rq)
+{
+ raw_spin_rq_unlock(rq);
+ local_irq_enable();
+}
+
+static inline int task_current(struct rq *rq, struct task_struct *p)
+{
+ return rq->curr == p;

56
linux-tkg-patches/5.14/0012-misc-additions.patch
View File

@@ -131,3 +131,59 @@ index 2c7171e0b0010..85de313ddec29 100644
select CPU_FREQ_GOV_CONSERVATIVE
select CPU_FREQ_GOV_PERFORMANCE
help
https://lore.kernel.org/lkml/20210819004305.20203-1-deepak.sharma@amd.com/
From: Deepak Sharma <deepak.sharma@amd.com>
To: <deepak.sharma@amd.com>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>,
Len Brown <len.brown@intel.com>, Pavel Machek <pavel@ucw.cz>,
Thomas Gleixner <tglx@linutronix.de>,
"Ingo Molnar" <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)"
<x86@kernel.org>, "H. Peter Anvin" <hpa@zytor.com>,
"open list:SUSPEND TO RAM" <linux-pm@vger.kernel.org>,
"open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)"
<linux-kernel@vger.kernel.org>
Subject: [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs
Date: Wed, 18 Aug 2021 17:43:05 -0700
Message-ID: <20210819004305.20203-1-deepak.sharma@amd.com> (raw)
AMD CPU which support C3 shares cache. Its not necessary to flush the
caches in software before entering C3. This will cause performance drop
for the cores which share some caches. ARB_DIS is not used with current
AMD C state implementation. So set related flags correctly.
Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
---
arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index 7de599eba7f0..62a5986d625a 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
*/
flags->bm_control = 0;
}
+ if (c->x86_vendor == X86_VENDOR_AMD) {
+ /*
+ * For all AMD CPUs that support C3, caches should not be
+ * flushed by software while entering C3 type state. Set
+ * bm->check to 1 so that kernel doesn't need to execute
+ * cache flush operation.
+ */
+ flags->bm_check = 1;
+ /*
+ * In current AMD C state implementation ARB_DIS is no longer
+ * used. So set bm_control to zero to indicate ARB_DIS is not
+ * required while entering C3 type state.
+ */
+ flags->bm_control = 0;
+ }
}
EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
--
2.25.1