190 lines
7.2 KiB
Diff
190 lines
7.2 KiB
Diff
From e5e77ad2223f662e1615266d8ef39a8db7e65a70 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Felix=20H=C3=A4dicke?= <felixhaedicke@web.de>
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Date: Thu, 19 Nov 2020 09:22:32 +0100
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Subject: HID: quirks: Add Apple Magic Trackpad 2 to hid_have_special_driver
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list
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The Apple Magic Trackpad 2 is handled by the magicmouse driver. And
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there were severe stability issues when both drivers (hid-generic and
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hid-magicmouse) were loaded for this device.
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Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=210241
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Signed-off-by: Felix Hädicke <felixhaedicke@web.de>
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---
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drivers/hid/hid-quirks.c | 2 ++
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1 file changed, 2 insertions(+)
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diff --git a/drivers/hid/hid-quirks.c b/drivers/hid/hid-quirks.c
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index bf7ecab5d9e5..142e9dae2837 100644
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--- a/drivers/hid/hid-quirks.c
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+++ b/drivers/hid/hid-quirks.c
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@@ -478,6 +478,8 @@ static const struct hid_device_id hid_have_special_driver[] = {
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#if IS_ENABLED(CONFIG_HID_MAGICMOUSE)
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{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_MAGICMOUSE) },
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{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_MAGICTRACKPAD) },
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+ { HID_BLUETOOTH_DEVICE(BT_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_MAGICTRACKPAD2) },
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+ { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_MAGICTRACKPAD2) },
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#endif
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#if IS_ENABLED(CONFIG_HID_MAYFLASH)
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{ HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_PS3) },
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--
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cgit v1.2.3-1-gf6bb5
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From e437ac931e89629f952ce9f3f9dfe45ac505cd0d Mon Sep 17 00:00:00 2001
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From: Joshua Ashton <joshua@froggi.es>
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Date: Tue, 5 Jan 2021 19:46:01 +0000
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Subject: [PATCH] drm/amdgpu: don't limit gtt size on apus
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Since commit 24562523688b ("Revert "drm/amd/amdgpu: set gtt size
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according to system memory size only""), the GTT size was limited by
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3GiB or VRAM size.
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This is problematic on APU systems with a small carveout
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(notably, those that ship with dGPUs where this is unconfigurable),
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where the carveout size can be as low as 128MiB.
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This makes it so the GTT size heuristic always uses 3/4ths of
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the system memory size on APUs (limiting the size by 3GiB/VRAM size
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only on devices with dedicated video memory).
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Fixes: 24562523688b ("Revert drm/amd/amdgpu: set gtt size according to
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system memory size only")
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Signed-off-by: Joshua Ashton <joshua@froggi.es>
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---
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drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +++--
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drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 12 +++++++++---
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2 files changed, 12 insertions(+), 5 deletions(-)
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diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
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index 72efd579ec5e..a5a41e9272d6 100644
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--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
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+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
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@@ -192,8 +192,9 @@ module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
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/**
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* DOC: gttsize (int)
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- * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
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- * otherwise 3/4 RAM size).
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+ * Restrict the size of GTT domain in MiB for testing. The default is -1 (On APUs this is 3/4th
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+ * of the system memory; on dGPUs this is 3GiB or VRAM sized, whichever is bigger,
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+ * with an upper bound of 3/4th of system memory.
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*/
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MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
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module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
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diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
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index 4d8f19ab1014..294f26f4f310 100644
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--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
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+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
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@@ -1865,9 +1865,15 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
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struct sysinfo si;
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si_meminfo(&si);
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- gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
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- adev->gmc.mc_vram_size),
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- ((uint64_t)si.totalram * si.mem_unit * 3/4));
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+ gtt_size = (uint64_t)si.totalram * si.mem_unit * 3/4;
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+ /* If we have dedicated memory, limit our GTT size to
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+ * 3GiB or VRAM size, whichever is bigger
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+ */
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+ if (!(adev->flags & AMD_IS_APU)) {
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+ gtt_size = min(max(AMDGPU_DEFAULT_GTT_SIZE_MB << 20,
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+ adev->gmc.mc_vram_size),
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+ gtt_size);
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+ }
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}
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else
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gtt_size = (uint64_t)amdgpu_gtt_size << 20;
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--
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2.30.0
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From f7f49141a5dbe9c99d78196b58c44307fb2e6be3 Mon Sep 17 00:00:00 2001
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From: Tk-Glitch <ti3nou@gmail.com>
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Date: Wed, 3 Feb 2021 11:20:12 +0200
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Subject: Revert "cpufreq: Avoid configuring old governors as default with intel_pstate"
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This is an undesirable behavior for us since our aggressive ondemand performs
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better than schedutil for gaming when using intel_pstate in passive mode.
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Also it interferes with the option to select the desired default governor we have.
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diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
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index 2c7171e0b0010..85de313ddec29 100644
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--- a/drivers/cpufreq/Kconfig
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+++ b/drivers/cpufreq/Kconfig
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@@ -71,7 +71,6 @@ config CPU_FREQ_DEFAULT_GOV_USERSPACE
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config CPU_FREQ_DEFAULT_GOV_ONDEMAND
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bool "ondemand"
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- depends on !(X86_INTEL_PSTATE && SMP)
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select CPU_FREQ_GOV_ONDEMAND
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select CPU_FREQ_GOV_PERFORMANCE
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help
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@@ -83,7 +84,6 @@ config CPU_FREQ_DEFAULT_GOV_ONDEMAND
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config CPU_FREQ_DEFAULT_GOV_CONSERVATIVE
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bool "conservative"
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- depends on !(X86_INTEL_PSTATE && SMP)
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select CPU_FREQ_GOV_CONSERVATIVE
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select CPU_FREQ_GOV_PERFORMANCE
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help
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https://lore.kernel.org/lkml/20210819004305.20203-1-deepak.sharma@amd.com/
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From: Deepak Sharma <deepak.sharma@amd.com>
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To: <deepak.sharma@amd.com>
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Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>,
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Len Brown <len.brown@intel.com>, Pavel Machek <pavel@ucw.cz>,
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Thomas Gleixner <tglx@linutronix.de>,
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"Ingo Molnar" <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
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"maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)"
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<x86@kernel.org>, "H. Peter Anvin" <hpa@zytor.com>,
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"open list:SUSPEND TO RAM" <linux-pm@vger.kernel.org>,
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"open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)"
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<linux-kernel@vger.kernel.org>
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Subject: [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs
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Date: Wed, 18 Aug 2021 17:43:05 -0700
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Message-ID: <20210819004305.20203-1-deepak.sharma@amd.com> (raw)
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AMD CPU which support C3 shares cache. Its not necessary to flush the
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caches in software before entering C3. This will cause performance drop
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for the cores which share some caches. ARB_DIS is not used with current
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AMD C state implementation. So set related flags correctly.
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Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
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---
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arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
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1 file changed, 15 insertions(+)
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diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
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index 7de599eba7f0..62a5986d625a 100644
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--- a/arch/x86/kernel/acpi/cstate.c
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+++ b/arch/x86/kernel/acpi/cstate.c
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@@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
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*/
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flags->bm_control = 0;
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}
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+ if (c->x86_vendor == X86_VENDOR_AMD) {
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+ /*
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+ * For all AMD CPUs that support C3, caches should not be
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+ * flushed by software while entering C3 type state. Set
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+ * bm->check to 1 so that kernel doesn't need to execute
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+ * cache flush operation.
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+ */
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+ flags->bm_check = 1;
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+ /*
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+ * In current AMD C state implementation ARB_DIS is no longer
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+ * used. So set bm_control to zero to indicate ARB_DIS is not
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+ * required while entering C3 type state.
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+ */
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+ flags->bm_control = 0;
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+ }
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}
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EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
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--
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2.25.1
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