soc/amd/picasso/include/data_fabric: add DF PCI config map register

PPR #55570 Rev 3.18 was used as a reference.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ide492f4479b85cd885044bbf74d8bf18c12e552b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

src/soc/amd/picasso/include/soc/data_fabric.h

@@ -11,6 +11,25 @@
 #define D18F0_VGAEN			DF_REG_ID(0, 0x80)
 #define   VGA_ADDR_ENABLE		BIT(0)
 
+#define DF_PCI_CFG_MAP0			DF_REG_ID(0, 0xa0)
+
+#define DF_PCI_CFG_MAP_COUNT		8
+
+#define DF_PCI_CFG_MAP(reg)		(DF_PCI_CFG_MAP0 + (reg) * sizeof(uint32_t))
+
+union df_pci_cfg_map {
+	struct {
+		uint32_t re		: 1; /* [ 0.. 0] */
+		uint32_t we		: 1; /* [ 1.. 1] */
+		uint32_t		: 2; /* [ 2.. 3] */
+		uint32_t dst_fabric_id	: 8; /* [ 4..11] */
+		uint32_t		: 4; /* [12..15] */
+		uint32_t bus_num_base	: 8; /* [16..23] */
+		uint32_t bus_num_limit	: 8; /* [24..31] */
+	};
+	uint32_t raw;
+};
+
 #define DF_IO_BASE0			DF_REG_ID(0, 0xc0)
 #define DF_IO_LIMIT0			DF_REG_ID(0, 0xc4)