Add support for Intel Sandybridge CPU (northbridge part)
Change-Id: I06228ecf9cac931ad34e32871d5a4f2a4857b2ac Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/854 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Stefan Reinauer
383
src/northbridge/intel/sandybridge/raminit.c
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383
src/northbridge/intel/sandybridge/raminit.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <string.h>
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#include <arch/hlt.h>
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <cbmem.h>
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#include <arch/cbfs.h>
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#include <cbfs.h>
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#include <ip_checksum.h>
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#include <pc80/mc146818rtc.h>
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#include "raminit.h"
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#include "pei_data.h"
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#include "sandybridge.h"
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/* Management Engine is in the southbridge */
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#include "southbridge/intel/bd82x6x/me.h"
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#if CONFIG_CHROMEOS
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#include <vendorcode/google/chromeos/chromeos.h>
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#endif
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#if 0
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#include <fdt/libfdt.h>
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#endif
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/*
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* MRC scrambler seed offsets should be reserved in
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* mainboard cmos.layout and not covered by checksum.
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*/
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#if CONFIG_USE_OPTION_TABLE
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#include "option_table.h"
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#define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3)
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#define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3)
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#define CMOS_OFFSET_MRC_SEED_CHK (CMOS_VSTART_mrc_scrambler_seed_chk >> 3)
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#else
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#define CMOS_OFFSET_MRC_SEED 112
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#define CMOS_OFFSET_MRC_SEED_S3 116
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#define CMOS_OFFSET_MRC_SEED_CHK 120
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#endif
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#define MRC_DATA_ALIGN 0x1000
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#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
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struct mrc_data_container {
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u32 mrc_signature; // "MRCD"
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u32 mrc_data_size; // Actual total size of this structure
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u32 mrc_checksum; // IP style checksum
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u32 reserved; // For header alignment
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u8 mrc_data[0]; // Variable size, platform/run time dependent.
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} __attribute__ ((packed));
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static void save_mrc_data(struct pei_data *pei_data)
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{
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u16 c1, c2, checksum;
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#if CONFIG_EARLY_CBMEM_INIT
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struct mrc_data_container *mrcdata;
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int output_len = ALIGN(pei_data->mrc_output_len, 16);
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/* Save the MRC S3 restore data to cbmem */
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cbmem_initialize();
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mrcdata = cbmem_add
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(CBMEM_ID_MRCDATA,
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output_len + sizeof(struct mrc_data_container));
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printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n",
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pei_data->mrc_output, mrcdata, output_len);
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mrcdata->mrc_signature = MRC_DATA_SIGNATURE;
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mrcdata->mrc_data_size = output_len;
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mrcdata->reserved = 0;
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memcpy(mrcdata->mrc_data, pei_data->mrc_output,
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pei_data->mrc_output_len);
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/* Zero the unused space in aligned buffer. */
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if (output_len > pei_data->mrc_output_len)
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memset(mrcdata->mrc_data+pei_data->mrc_output_len, 0,
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output_len - pei_data->mrc_output_len);
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mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data,
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mrcdata->mrc_data_size);
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#endif
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/* Save the MRC seed values to CMOS */
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cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
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printk(BIOS_DEBUG, "Save scrambler seed 0x%08x to CMOS 0x%02x\n",
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pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
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cmos_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
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printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n",
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pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
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/* Save a simple checksum of the seed values */
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c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed,
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sizeof(u32));
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c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3,
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sizeof(u32));
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checksum = add_ip_checksums(sizeof(u32), c1, c2);
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cmos_write(checksum & 0xff, CMOS_OFFSET_MRC_SEED_CHK);
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cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK+1);
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}
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#if CONFIG_CHROMEOS
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static void prepare_mrc_cache(struct pei_data *pei_data)
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{
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const struct fdt_header *fdt_header;
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const struct fdt_property *fdtp;
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int offset, len;
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const char *compatible = "chromeos,flashmap";
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const char *subnode = "rw-mrc-cache";
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const char *property = "reg";
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u32 *data;
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struct mrc_data_container *mrc_cache, *mrc_next;
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u8 *mrc_region, *region_ptr;
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u16 c1, c2, checksum, seed_checksum;
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u32 region_size, entry_id = 0;
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u64 flashrom_base = 0;
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// preset just in case there is an error
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pei_data->mrc_input = NULL;
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pei_data->mrc_input_len = 0;
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/* Read scrambler seeds from CMOS */
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pei_data->scrambler_seed = cmos_read32(CMOS_OFFSET_MRC_SEED);
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printk(BIOS_DEBUG, "Read scrambler seed 0x%08x from CMOS 0x%02x\n",
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pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
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pei_data->scrambler_seed_s3 = cmos_read32(CMOS_OFFSET_MRC_SEED_S3);
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printk(BIOS_DEBUG, "Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n",
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pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
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/* Compute seed checksum and compare */
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c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed,
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sizeof(u32));
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c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3,
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sizeof(u32));
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checksum = add_ip_checksums(sizeof(u32), c1, c2);
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seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK);
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seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK+1) << 8;
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if (checksum != seed_checksum) {
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printk(BIOS_ERR, "%s: invalid seed checksum\n", __func__);
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pei_data->scrambler_seed = 0;
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pei_data->scrambler_seed_s3 = 0;
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return;
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}
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fdt_header = cbfs_find_file(CONFIG_FDT_FILE_NAME, CBFS_TYPE_FDT);
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if (!fdt_header) {
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printk(BIOS_ERR, "%s: no FDT found!\n", __func__);
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return;
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}
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offset = fdt_node_offset_by_compatible(fdt_header, 0, compatible);
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if (offset < 0) {
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printk(BIOS_ERR, "%s: no %s node found!\n",
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__func__, compatible);
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return;
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}
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if (fdt_get_base_addr(fdt_header, offset, &flashrom_base) < 0) {
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printk(BIOS_ERR, "%s: no base address in node name!\n",
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__func__);
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return;
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}
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offset = fdt_subnode_offset(fdt_header, offset, subnode);
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if (offset < 0) {
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printk(BIOS_ERR, "%s: no %s found!\n", __func__, subnode);
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return;
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}
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fdtp = fdt_get_property(fdt_header, offset, property, &len);
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if (!fdtp || (len != 8)) {
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printk(BIOS_ERR, "%s: property %s at %p, len %d!\n",
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__func__, property, fdtp, len);
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return;
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}
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data = (u32 *)fdtp->data;
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// Calculate actual address of the MRC cache in memory
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region_size = fdt32_to_cpu(data[1]);
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mrc_region = region_ptr = (u8*)
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((unsigned long)flashrom_base + fdt32_to_cpu(data[0]));
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mrc_cache = mrc_next = (struct mrc_data_container *)mrc_region;
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if (!mrc_cache || mrc_cache->mrc_signature != MRC_DATA_SIGNATURE) {
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printk(BIOS_ERR, "%s: invalid MRC data\n", __func__);
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return;
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}
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if (mrc_cache->mrc_data_size == -1UL) {
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printk(BIOS_ERR, "%s: MRC cache not initialized?\n", __func__);
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return;
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} else {
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/* MRC data blocks are aligned within the region */
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u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size;
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if (mrc_size & (MRC_DATA_ALIGN - 1UL)) {
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mrc_size &= ~(MRC_DATA_ALIGN - 1UL);
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mrc_size += MRC_DATA_ALIGN;
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}
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/* Search for the last filled entry in the region */
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while (mrc_next &&
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mrc_next->mrc_signature == MRC_DATA_SIGNATURE) {
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entry_id++;
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mrc_cache = mrc_next;
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/* Stay in the mrcdata region defined in fdt */
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if ((entry_id * mrc_size) > region_size)
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break;
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region_ptr += mrc_size;
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mrc_next = (struct mrc_data_container *)region_ptr;
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}
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entry_id--;
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}
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/* Verify checksum */
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if (mrc_cache->mrc_checksum !=
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compute_ip_checksum(mrc_cache->mrc_data,
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mrc_cache->mrc_data_size)) {
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printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__);
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return;
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}
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pei_data->mrc_input = mrc_cache->mrc_data;
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pei_data->mrc_input_len = mrc_cache->mrc_data_size;
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printk(BIOS_DEBUG, "%s: at %p, entry %u size %x checksum %04x\n",
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__func__, pei_data->mrc_input, entry_id,
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pei_data->mrc_input_len, mrc_cache->mrc_checksum);
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}
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#endif
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static const char* ecc_decoder[] = {
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"inactive",
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"active on IO",
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"disabled on IO",
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"active"
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};
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/*
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* Dump in the log memory controller configuration as read from the memory
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* controller registers.
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*/
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static void report_memory_config(void)
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{
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u32 addr_decoder_common, addr_decode_ch[2];
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int i;
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addr_decoder_common = MCHBAR32(0x5000);
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addr_decode_ch[0] = MCHBAR32(0x5004);
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addr_decode_ch[1] = MCHBAR32(0x5008);
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printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
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(MCHBAR32(0x5e04) * 13333 * 2 + 50)/100);
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printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
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addr_decoder_common & 3,
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(addr_decoder_common >> 2) & 3,
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(addr_decoder_common >> 4) & 3);
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for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
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u32 ch_conf = addr_decode_ch[i];
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printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n",
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i, ch_conf);
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printk(BIOS_DEBUG, " ECC %s\n",
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ecc_decoder[(ch_conf >> 24) & 3]);
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printk(BIOS_DEBUG, " enhanced interleave mode %s\n",
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((ch_conf >> 22) & 1) ? "on" : "off");
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printk(BIOS_DEBUG, " rank interleave %s\n",
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((ch_conf >> 21) & 1) ? "on" : "off");
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printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n",
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((ch_conf >> 0) & 0xff) * 256,
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((ch_conf >> 19) & 1) ? 16 : 8,
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((ch_conf >> 17) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? "" : ", selected");
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printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n",
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((ch_conf >> 8) & 0xff) * 256,
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((ch_conf >> 20) & 1) ? 16 : 8,
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((ch_conf >> 18) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? ", selected" : "");
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}
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}
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/**
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* Find PEI executable in coreboot filesystem and execute it.
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*
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* @param pei_data: configuration data for UEFI PEI reference code
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*/
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void sdram_initialize(struct pei_data *pei_data)
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{
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struct sys_info sysinfo;
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const char *target = "mrc.bin";
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unsigned long entry;
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/* Wait for ME to be ready */
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intel_early_me_init();
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intel_early_me_uma_size();
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printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n");
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memset(&sysinfo, 0, sizeof(sysinfo));
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sysinfo.boot_path = pei_data->boot_mode;
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#if CONFIG_CHROMEOS
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/*
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* Do not pass MRC data in for recovery mode boot,
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* Always pass it in for S3 resume.
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*/
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if (!recovery_mode_enabled() || pei_data->boot_mode == 2)
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prepare_mrc_cache(pei_data);
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/* If MRC data is not found we cannot continue S3 resume. */
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if (pei_data->boot_mode == 2 && !pei_data->mrc_input) {
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outb(0x6, 0xcf9);
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hlt();
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}
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#endif
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/* Locate and call UEFI System Agent binary. */
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entry = (unsigned long)cbfs_find_file(target, 0xab);
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if (entry) {
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int rv;
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asm volatile (
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"call *%%ecx\n\t"
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:"=a" (rv) : "c" (entry), "a" (pei_data));
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if (rv) {
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printk(BIOS_ERR, "MRC returned %d\n", rv);
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die("Nonzero MRC return value\n");
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}
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} else {
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die("UEFI PEI System Agent not found.\n");
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}
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/* For reference print the System Agent version
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* after executing the UEFI PEI stage.
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*/
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u32 version = MCHBAR32(0x5034);
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printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n",
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version >> 24 , (version >> 16) & 0xff,
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(version >> 8) & 0xff, version & 0xff);
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intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
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report_memory_config();
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/* S3 resume: don't save scrambler seed or MRC data */
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if (pei_data->boot_mode != 2)
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save_mrc_data(pei_data);
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}
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struct cbmem_entry *get_cbmem_toc(void)
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{
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return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
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}
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unsigned long get_top_of_ram(void)
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{
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/* Base of TSEG is top of usable DRAM */
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u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
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return (unsigned long) tom;
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}
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