From 00b535505de9c80baf018bfa055023435ec17bf0 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Wed, 20 Feb 2019 16:33:33 -0700 Subject: [PATCH] soc/intel/cannonlake: Set FSP-S Enable8254ClockGating using clock_gate_8254 devicetree parameter Tested on system76 galp3-c Signed-off-by: Jeremy Soller Change-Id: Id346173ac7ae5246de0b38b9dd23be7b72e70f1e --- src/soc/intel/cannonlake/fsp_params.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index cc01d10fe8..e0a62cc0ac 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -219,6 +219,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = config->clock_gate_8254; + params->Enable8254ClockGatingOnS3 = config->clock_gate_8254; + /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));