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Update AMD SR5650 and SB700

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This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes.  The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements.  This particular change
affects all mainboards that use the SB700, and their changes are
include herein.  These mainboards are:
  Advansus a785e,
  AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
  Asrock 939a785gmh,
  Asus m4a78-em, m4a785-m,
  Gigabyte ma785gm,
  Iei Kino-780am2-fam10
  Jetway pa78vm5
  Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.

Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
efdesign98
2011-07-20 12:37:58 -06:00
committed by Marc Jones
parent 09ea8ea1a7
commit 00c8c4a316
49 changed files with 537 additions and 348 deletions
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46
src/southbridge/amd/sb700/reset.c Normal file → Executable file
View File

@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
* Copyright (C) 2010 - 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,17 +17,51 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <reset.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <reset.h> /* hard_reset, soft_rest*/
#include <arch/io.h> /* inb, outb */
#include <arch/romcc_io.h> /* pci_read_config32, device_t, PCI_DEV */
#include "../../../northbridge/amd/amdk8/reset_test.c"
#define HT_INIT_CONTROL 0x6C
#define HTIC_BIOSR_Detect (1<<5)
#if CONFIG_MAX_PHYSICAL_CPUS > 32
#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
#else
#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
#endif
static void set_bios_reset(void)
{
u32 nodes;
u32 htic;
device_t dev;
int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
for(i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;
pci_write_config32(dev, HT_INIT_CONTROL, htic);
}
}
void hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
/* Actually it is not a real hard_reset
* --- it only reset coherent link table, but not reset link freq and width
*/
outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
}
void soft_reset(void)
{
set_bios_reset();
/* link reset */
outb(0x06, 0x0cf9);
}