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soc/amd/common/block/psp/psp_gen2: simplify soc_read_c2p38

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Commit 198cc26e4951b3dbca588286706b7df562c45d42 (soc/amd/common/block/
psp/psp_gen2: use SMN access to PSP) changed how the PSP registers are
accessed. Since the new method doesn't need to rely on a MMIO base
address to be configured, the read will always be successful and so
soc_read_c2p38 doesn't need to return an error status and can directly
return the value instead.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1abace04668947ba3223a107461a27dddc0a9d83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2022-05-05 15:19:03 +02:00
parent d8d522884b
commit 00ec1b9fc7
2 changed files with 4 additions and 11 deletions
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2
src/soc/amd/common/block/psp/psp_def.h
View File

@ -86,6 +86,6 @@ void psp_print_cmd_status(int cmd_status, struct mbox_buffer_header *header);
/* This command needs to be implemented by the generation specific code. */ /* This command needs to be implemented by the generation specific code. */
int send_psp_command(u32 command, void *buffer); int send_psp_command(u32 command, void *buffer);
enum cb_err soc_read_c2p38(uint32_t *msg_38_value); uint32_t soc_read_c2p38(void);
#endif /* __AMD_PSP_DEF_H__ */ #endif /* __AMD_PSP_DEF_H__ */

13
src/soc/amd/common/block/psp/psp_gen2.c
View File

@ -111,10 +111,9 @@ int send_psp_command(u32 command, void *buffer)
return 0; return 0;
} }
enum cb_err soc_read_c2p38(uint32_t *msg_38_value) uint32_t soc_read_c2p38(void)
{ {
*msg_38_value = smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET); return smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET);
return CB_SUCCESS;
} }
static void psp_set_spl_fuse(void *unused) static void psp_set_spl_fuse(void *unused)
@ -122,7 +121,6 @@ static void psp_set_spl_fuse(void *unused)
if (!CONFIG(SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL)) if (!CONFIG(SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL))
return; return;
uint32_t msg_38_value = 0;
int cmd_status = 0; int cmd_status = 0;
struct mbox_cmd_late_spl_buffer buffer = { struct mbox_cmd_late_spl_buffer buffer = {
.header = { .header = {
@ -130,12 +128,7 @@ static void psp_set_spl_fuse(void *unused)
} }
}; };
if (soc_read_c2p38(&msg_38_value) != CB_SUCCESS) { if (soc_read_c2p38() & CORE_2_PSP_MSG_38_FUSE_SPL) {
printk(BIOS_ERR, "PSP: Failed to read psp base address.\n");
return;
}
if (msg_38_value & CORE_2_PSP_MSG_38_FUSE_SPL) {
printk(BIOS_DEBUG, "PSP: Fuse SPL requested\n"); printk(BIOS_DEBUG, "PSP: Fuse SPL requested\n");
cmd_status = send_psp_command(MBOX_BIOS_CMD_SET_SPL_FUSE, &buffer); cmd_status = send_psp_command(MBOX_BIOS_CMD_SET_SPL_FUSE, &buffer);
psp_print_cmd_status(cmd_status, NULL); psp_print_cmd_status(cmd_status, NULL);