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soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO

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Only the headers on Intel FSP repository have the CnviWifiCore
present. Options guarded for RPL like: DisableDynamicTccoldHandshake
or EnableFastVmode and IccLimit is also supported by all public FSPs
(except ADL-N for the handshake).

Options like LowerBasicMemTestSize and DisableSagvReorder have to be
guarded when FSP_USE_REPO is not selected, as publci FSPs do not have
these options.

Use FSP_USE_REPO instead of/in addition to SOC_INTEL_RAPTORLAKE
as dependency on the guarded UPDs to make them available for FSPs
that support them as well. Also prioritize the headers from FSP repo
over vendorcode headers if FSP_USE_REPO is selected.

Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
This commit is contained in:
Michał Żygowski
2023-07-12 13:22:09 +02:00
parent ce7d818254
commit 01025d3ae7
5 changed files with 11 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/intel/alderlake/Kconfig
View File

@@ -397,13 +397,13 @@ config FSP_TYPE_IOT
config FSP_HEADER_PATH
string "Location of FSP headers"
default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N
default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if SOC_INTEL_RAPTORLAKE
default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N && !FSP_USE_REPO
default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if SOC_INTEL_RAPTORLAKE && !FSP_USE_REPO
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT
default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P
default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S
default "src/vendorcode/intel/fsp/fsp2_0/alderlake/"
default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" if !FSP_USE_REPO
config FSP_FD_PATH
string

9
src/soc/intel/alderlake/fsp_params.c
View File

@@ -818,11 +818,9 @@ static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_alderlake_config *config)
{
/* CNVi */
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) || CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
#if !CONFIG(SOC_INTEL_RAPTORLAKE)
/* This option is only available in public FSP headers of ADL-P and ADL-S */
#if CONFIG(FSP_USE_REPO)
/* This option is only available in public FSP headers on FSP repo */
s_cfg->CnviWifiCore = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI);
#endif
#endif
s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI);
s_cfg->CnviBtCore = config->cnvi_bt_core;
@@ -1032,8 +1030,7 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
s_cfg->C1e = 0;
else
s_cfg->C1e = 1;
#if CONFIG(SOC_INTEL_RAPTORLAKE)
#if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO)
s_cfg->EnableHwpScalabilityTracking = config->enable_hwp_scalability_tracking;
#endif
}

2
src/soc/intel/alderlake/include/soc/vr_config.h
View File

@@ -8,7 +8,7 @@
#include <fsp/api.h>
struct vr_config {
#if CONFIG(SOC_INTEL_RAPTORLAKE)
#if CONFIG(SOC_INTEL_RAPTORLAKE) || CONFIG(FSP_USE_REPO)
/*
* When enabled, this feature makes the SoC throttle when the power
* consumption exceeds the I_TRIP threshold.

5
src/soc/intel/alderlake/romstage/fsp_params.c
View File

@@ -158,7 +158,7 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
m_cfg->DdrFreqLimit = config->max_dram_speed_mts;
m_cfg->DdrSpeedControl = 1;
}
#if CONFIG(SOC_INTEL_RAPTORLAKE)
#if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO)
m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size;
m_cfg->DisableSagvReorder = config->disable_sagv_reorder;
#endif
@@ -272,7 +272,8 @@ static void fill_fspm_tcss_params(FSP_M_CONFIG *m_cfg,
m_cfg->TcssDma0En = is_devfn_enabled(SA_DEVFN_TCSS_DMA0);
m_cfg->TcssDma1En = is_devfn_enabled(SA_DEVFN_TCSS_DMA1);
#if CONFIG(SOC_INTEL_RAPTORLAKE)
#if (CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO)) || \
(!CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) && CONFIG(FSP_USE_REPO))
m_cfg->DisableDynamicTccoldHandshake =
config->disable_dynamic_tccold_handshake;
#endif

2
src/soc/intel/alderlake/vr_config.c
View File

@@ -353,7 +353,7 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = {
static void fill_vr_fast_vmode(FSP_S_CONFIG *s_cfg,
int domain, const struct vr_config *chip_cfg)
{
#if CONFIG(SOC_INTEL_RAPTORLAKE)
#if CONFIG(SOC_INTEL_RAPTORLAKE) || CONFIG(FSP_USE_REPO)
s_cfg->EnableFastVmode[domain] = chip_cfg->enable_fast_vmode;
if (s_cfg->EnableFastVmode[domain])
s_cfg->IccLimit[domain] = chip_cfg->fast_vmode_i_trip;