cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequence
This fixes Family 15h multiple package support; the previous code hung in CAR setup and romstage when more than one CPU package was installed for a variety of loosely related reasons. TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors and several different RDIMM configurations. Change-Id: I171197c90f72d3496a385465937b7666cbf7e308 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12020 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Timothy Pearson
committed by
Martin Roth
Martin Roth
parent
631c8a2690
commit
0122afb609
@@ -385,13 +385,49 @@ static u8 convertNodeToLink(u8 srcNode, u8 targetNode, sMainData *pDat)
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*/
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static void htDiscoveryFloodFill(sMainData *pDat)
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{
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u8 currentNode = 0;
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u8 currentLink;
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uint8_t currentNode = 0;
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uint8_t currentLink;
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uint8_t currentLinkID;
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/* NOTE
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* Each node inside a dual node (socket G34) processor must share
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* an adjacent node ID. Alter the link scan order such that the
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* other internal node is always scanned first...
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*/
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uint8_t currentLinkScanOrder_Default[8] = {0, 1, 2, 3, 4, 5, 6, 7};
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uint8_t currentLinkScanOrder_G34_Fam10[8] = {1, 0, 2, 3, 4, 5, 6, 7};
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uint8_t currentLinkScanOrder_G34_Fam15[8] = {2, 0, 1, 3, 4, 5, 6, 7};
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uint8_t fam15h = 0;
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uint8_t rev_gte_d = 0;
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uint8_t dual_node = 0;
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uint32_t f3xe8;
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uint32_t family;
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uint32_t model;
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f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8);
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family = model = cpuid_eax(0x80000001);
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model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4);
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family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
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if (family >= 0x6f) {
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/* Family 15h or later */
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fam15h = 1;
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}
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if ((model >= 0x8) || fam15h)
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/* Revision D or later */
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rev_gte_d = 1;
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if (rev_gte_d)
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/* Check for dual node capability */
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if (f3xe8 & 0x20000000)
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dual_node = 1;
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/* Entries are always added in pairs, the even indices are the 'source'
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* side closest to the BSP, the odd indices are the 'destination' side
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*/
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while (currentNode <= pDat->NodesDiscovered)
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{
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u32 temp;
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@@ -419,11 +455,24 @@ static void htDiscoveryFloodFill(sMainData *pDat)
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/* Enable routing tables on currentNode*/
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pDat->nb->enableRoutingTables(currentNode, pDat->nb);
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for (currentLink = 0; currentLink < pDat->nb->maxLinks; currentLink++)
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for (currentLinkID = 0; currentLinkID < pDat->nb->maxLinks; currentLinkID++)
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{
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BOOL linkfound;
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u8 token;
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if (currentLinkID < 8) {
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if (dual_node) {
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if (fam15h)
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currentLink = currentLinkScanOrder_G34_Fam15[currentLinkID];
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else
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currentLink = currentLinkScanOrder_G34_Fam10[currentLinkID];
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} else {
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currentLink = currentLinkScanOrder_Default[currentLinkID];
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}
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} else {
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currentLink = currentLinkID;
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}
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if (pDat->HtBlock->AMD_CB_IgnoreLink && pDat->HtBlock->AMD_CB_IgnoreLink(currentNode, currentLink))
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continue;
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@@ -47,8 +47,9 @@
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#define REG_NODE_ID_0X60 0x60
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#define REG_UNIT_ID_0X64 0x64
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#define REG_LINK_TRANS_CONTROL_0X68 0x68
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#define REG_LINK_INIT_CONTROL_0X6C 0x6C
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#define REG_LINK_INIT_CONTROL_0X6C 0x6c
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#define REG_HT_CAP_BASE_0X80 0x80
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#define REG_NORTHBRIDGE_CFG_3X8C 0x8c
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#define REG_HT_LINK_RETRY0_0X130 0x130
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#define REG_HT_TRAFFIC_DIST_0X164 0x164
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#define REG_HT_LINK_EXT_CONTROL0_0X170 0x170
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@@ -87,6 +88,21 @@
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*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
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***************************************************************************/
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static inline uint8_t is_fam15h(void)
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{
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uint8_t fam15h = 0;
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uint32_t family;
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family = cpuid_eax(0x80000001);
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family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
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if (family >= 0x6f)
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/* Family 15h or later */
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fam15h = 1;
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return fam15h;
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}
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/***************************************************************************//**
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*
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* SBDFO
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@@ -215,8 +231,18 @@ static void writeRoutingTable(u8 node, u8 target, u8 link, cNorthBridge *nb)
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static void writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb)
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{
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u32 temp = nodeID;
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u32 temp;
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ASSERT((node < nb->maxNodes) && (nodeID < nb->maxNodes));
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if (is_fam15h()) {
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temp = 1;
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AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(node),
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makePCIBusFromNode(node),
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makePCIDeviceFromNode(node),
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CPU_NB_FUNC_03,
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REG_NORTHBRIDGE_CFG_3X8C),
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22, 22, &temp);
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}
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temp = nodeID;
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AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(node),
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makePCIBusFromNode(node),
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makePCIDeviceFromNode(node),
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@@ -82,22 +82,129 @@ static u32 get_nodes(void)
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return nodes;
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}
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static const char * event_class_string_decodes[] = {
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[HT_EVENT_CLASS_CRITICAL] = "CRITICAL",
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[HT_EVENT_CLASS_ERROR] = "ERROR",
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[HT_EVENT_CLASS_HW_FAULT] = "HARDWARE FAULT",
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[HT_EVENT_CLASS_WARNING] = "WARNING",
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[HT_EVENT_CLASS_INFO] = "INFO"
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};
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static const char * event_string_decodes[] = {
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[HT_EVENT_COH_EVENTS] = "HT_EVENT_COH_EVENTS",
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[HT_EVENT_COH_NO_TOPOLOGY] = "HT_EVENT_COH_NO_TOPOLOGY",
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[HT_EVENT_COH_LINK_EXCEED] = "HT_EVENT_COH_LINK_EXCEED",
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[HT_EVENT_COH_FAMILY_FEUD] = "HT_EVENT_COH_FAMILY_FEUD",
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[HT_EVENT_COH_NODE_DISCOVERED] = "HT_EVENT_COH_NODE_DISCOVERED",
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[HT_EVENT_COH_MPCAP_MISMATCH] = "HT_EVENT_COH_MPCAP_MISMATCH",
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[HT_EVENT_NCOH_EVENTS] = "HT_EVENT_NCOH_EVENTS",
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[HT_EVENT_NCOH_BUID_EXCEED] = "HT_EVENT_NCOH_BUID_EXCEED",
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[HT_EVENT_NCOH_LINK_EXCEED] = "HT_EVENT_NCOH_LINK_EXCEED",
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[HT_EVENT_NCOH_BUS_MAX_EXCEED] = "HT_EVENT_NCOH_BUS_MAX_EXCEED",
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[HT_EVENT_NCOH_CFG_MAP_EXCEED] = "HT_EVENT_NCOH_CFG_MAP_EXCEED",
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[HT_EVENT_NCOH_DEVICE_FAILED] = "HT_EVENT_NCOH_DEVICE_FAILED",
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[HT_EVENT_NCOH_AUTO_DEPTH] = "HT_EVENT_NCOH_AUTO_DEPTH",
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[HT_EVENT_OPT_EVENTS] = "HT_EVENT_OPT_EVENTS",
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[HT_EVENT_OPT_REQUIRED_CAP_RETRY] = "HT_EVENT_OPT_REQUIRED_CAP_RETRY",
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[HT_EVENT_OPT_REQUIRED_CAP_GEN3] = "HT_EVENT_OPT_REQUIRED_CAP_GEN3",
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[HT_EVENT_HW_EVENTS] = "HT_EVENT_HW_EVENTS",
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[HT_EVENT_HW_SYNCHFLOOD] = "HT_EVENT_HW_SYNCHFLOOD",
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[HT_EVENT_HW_HTCRC] = "HT_EVENT_HW_HTCRC"
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};
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/**
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* void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0)
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*/
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static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0)
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{
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u8 i;
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uint8_t i;
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uint8_t log_level;
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uint8_t dump_event_detail;
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printk(BIOS_DEBUG, "AMD_CB_EventNotify()\n");
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printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event);
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printk(BIOS_DEBUG, "AMD_CB_EventNotify(): ");
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for (i = 0; i < *pEventData0; i++) {
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printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i));
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/* Decode event */
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dump_event_detail = 1;
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switch (evtClass) {
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case HT_EVENT_CLASS_CRITICAL:
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case HT_EVENT_CLASS_ERROR:
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case HT_EVENT_CLASS_HW_FAULT:
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case HT_EVENT_CLASS_WARNING:
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case HT_EVENT_CLASS_INFO:
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log_level = BIOS_DEBUG;
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printk(log_level, event_class_string_decodes[evtClass]);
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break;
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default:
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log_level = BIOS_DEBUG;
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printk(log_level, "UNKNOWN");
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break;
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}
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printk(BIOS_DEBUG, "\n");
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printk(log_level, ": ");
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switch(event) {
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case HT_EVENT_COH_EVENTS:
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case HT_EVENT_COH_NO_TOPOLOGY:
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case HT_EVENT_COH_LINK_EXCEED:
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case HT_EVENT_COH_FAMILY_FEUD:
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printk(log_level, event_string_decodes[event]);
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break;
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case HT_EVENT_COH_NODE_DISCOVERED:
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{
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printk(log_level, "HT_EVENT_COH_NODE_DISCOVERED");
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sHtEventCohNodeDiscovered *evt = (sHtEventCohNodeDiscovered*)pEventData0;
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printk(log_level, ": node %d link %d new node: %d",
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evt->node, evt->link, evt->newNode);
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dump_event_detail = 0;
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break;
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}
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case HT_EVENT_COH_MPCAP_MISMATCH:
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case HT_EVENT_NCOH_EVENTS:
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case HT_EVENT_NCOH_BUID_EXCEED:
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case HT_EVENT_NCOH_LINK_EXCEED:
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case HT_EVENT_NCOH_BUS_MAX_EXCEED:
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case HT_EVENT_NCOH_CFG_MAP_EXCEED:
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printk(log_level, event_string_decodes[event]);
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break;
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case HT_EVENT_NCOH_DEVICE_FAILED:
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{
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printk(log_level, event_string_decodes[event]);
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sHtEventNcohDeviceFailed *evt = (sHtEventNcohDeviceFailed*)pEventData0;
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printk(log_level, ": node %d link %d depth: %d attemptedBUID: %d",
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evt->node, evt->link, evt->depth, evt->attemptedBUID);
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dump_event_detail = 0;
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break;
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}
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case HT_EVENT_NCOH_AUTO_DEPTH:
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{
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printk(log_level, event_string_decodes[event]);
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sHtEventNcohAutoDepth *evt = (sHtEventNcohAutoDepth*)pEventData0;
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printk(log_level, ": node %d link %d depth: %d",
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evt->node, evt->link, evt->depth);
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dump_event_detail = 0;
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break;
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}
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case HT_EVENT_OPT_EVENTS:
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case HT_EVENT_OPT_REQUIRED_CAP_RETRY:
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case HT_EVENT_OPT_REQUIRED_CAP_GEN3:
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case HT_EVENT_HW_EVENTS:
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case HT_EVENT_HW_SYNCHFLOOD:
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case HT_EVENT_HW_HTCRC:
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printk(log_level, event_string_decodes[event]);
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break;
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default:
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printk(log_level, "HT_EVENT_UNKNOWN");
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break;
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}
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printk(log_level, "\n");
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if (dump_event_detail) {
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printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event);
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for (i = 0; i < *pEventData0; i++) {
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printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i));
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}
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printk(BIOS_DEBUG, "\n");
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}
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}
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/**
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@@ -206,9 +313,10 @@ void amd_ht_fixup(struct sys_info *sysinfo) {
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for (node = 0; node < node_count; node++) {
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f3xe8 = pci_read_config32(NODE_PCI(node, 3), 0xe8);
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uint8_t internal_node_number = ((f3xe8 & 0xc0000000) >> 30);
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printk(BIOS_DEBUG, "amd_ht_fixup(): node %d (internal node ID %d): disabling defective HT link\n", node, internal_node_number);
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printk(BIOS_DEBUG, "amd_ht_fixup(): node %d (internal node ID %d): disabling defective HT link", node, internal_node_number);
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if (internal_node_number == 0) {
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uint8_t package_link_3_connected = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x98:0xd8) & 0x1;
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printk(BIOS_DEBUG, " (L3 connected: %d)\n", package_link_3_connected);
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if (package_link_3_connected) {
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/* Set WidthIn and WidthOut to 0 */
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dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x84:0xc4);
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@@ -230,15 +338,21 @@ void amd_ht_fixup(struct sys_info *sysinfo) {
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}
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} else if (internal_node_number == 1) {
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uint8_t package_link_3_connected = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0xf8:0xb8) & 0x1;
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printk(BIOS_DEBUG, " (L3 connected: %d)\n", package_link_3_connected);
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if (package_link_3_connected) {
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/* Set WidthIn and WidthOut to 0 */
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dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0xe4:0xa4);
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dword &= ~0x77000000;
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pci_write_config32(NODE_PCI(node, 0), (fam15h)?0xe4:0xa4, dword);
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/* Set Ganged to 1 */
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dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x18c:0x174);
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/* WARNING
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* The Family 15h BKDG states that 0x18c should be set,
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* however this is in error. 0x17c is the correct control
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* register (sublink 0) for these processors...
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*/
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dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x17c:0x174);
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dword |= 0x00000001;
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pci_write_config32(NODE_PCI(node, 0), (fam15h)?0x18c:0x174, dword);
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pci_write_config32(NODE_PCI(node, 0), (fam15h)?0x17c:0x174, dword);
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} else {
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/* Set ConnDly to 1 */
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dword = pci_read_config32(NODE_PCI(node, 0), 0x16c);
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@@ -5451,6 +5451,7 @@ static void mct_InitialMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc
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cpu_divisor = (0x1 << cpu_did);
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pMCTstat->TSCFreq = (100 * (cpu_fid + 0x10)) / cpu_divisor;
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printk(BIOS_DEBUG, "mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15\n");
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mct_ForceNBPState0_En_Fam15(pMCTstat, pDCTstat);
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} else {
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/* K10 BKDG v3.62 section 2.8.9.2 */
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