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Combine Broadwell Chromeboxes using variant board scheme

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Combine existing boards google/guado, rikku, and tidus using
their common reference board google/jecht as a base.

Additional changes besides simple consolidation include:
 - simplify power LED functions
 - simplify HDA verb definitions using azelia macros
 - use common SoC functions to generate FADT table
 - correct FADT table header version
 - remove unused haswell_pci_irqs.asl
 - remove unused header includes (various)
 - set sane default fan speed (0x4d) for all variants

Variant setup modeled after google/beltino

Change-Id: I77a2dffe9601734916a33fd04ead98016ad0bc4b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17913
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Matt DeVillier
2016-12-17 17:13:23 -06:00
committed by Martin Roth
parent 6390e525fc
commit 0148fcb4e1
112 changed files with 176 additions and 5424 deletions
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104
src/mainboard/google/jecht/mainboard.c
View File

@@ -14,22 +14,8 @@
* GNU General Public License for more details.
*/
#include <types.h>
#include <string.h>
#include <smbios.h>
#include <device/device.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#if CONFIG_VGA_ROM_RUN
#include <x86emu/x86emu.h>
#endif
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
@@ -39,92 +25,6 @@ void mainboard_suspend_resume(void)
outb(0xcb, 0xb2);
}
#if CONFIG_VGA_ROM_RUN
static int int15_handler(void)
{
int res = 0;
printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
__func__, X86_AX, X86_BX, X86_CX, X86_DX);
switch (X86_AX) {
case 0x5f34:
/*
* Set Panel Fitting Hook:
* bit 2 = Graphics Stretching
* bit 1 = Text Stretching
* bit 0 = Centering (do not set with bit1 or bit2)
* 0 = video bios default
*/
X86_AX = 0x005f;
X86_CX = 0x0001;
res = 1;
break;
case 0x5f35:
/*
* Boot Display Device Hook:
* bit 0 = CRT
* bit 1 = TV (eDP) *
* bit 2 = EFP *
* bit 3 = LFP
* bit 4 = CRT2
* bit 5 = TV2 (eDP) *
* bit 6 = EFP2 *
* bit 7 = LFP2
*/
X86_AX = 0x005f;
X86_CX = 0x0000;
res = 1;
break;
case 0x5f51:
/*
* Hook to select active LFP configuration:
* 00h = No LVDS, VBIOS does not enable LVDS
* 01h = Int-LVDS, LFP driven by integrated LVDS decoder
* 02h = SVDO-LVDS, LFP driven by SVDO decoder
* 03h = eDP, LFP Driven by Int-DisplayPort encoder
*/
X86_AX = 0x005f;
X86_CX = 0x0003;
res = 1;
break;
case 0x5f70:
switch ((X86_CX >> 8) & 0xff) {
case 0:
/* Get Mux */
X86_AX = 0x005f;
X86_CX = 0x0000;
res = 1;
break;
case 1:
/* Set Mux */
X86_AX = 0x005f;
X86_CX = 0x0000;
res = 1;
break;
case 2:
/* Get SG/Non-SG mode */
X86_AX = 0x005f;
X86_CX = 0x0000;
res = 1;
break;
default:
/* Interrupt was not handled */
printk(BIOS_DEBUG,
"Unknown INT15 5f70 function: 0x%02x\n",
((X86_CX >> 8) & 0xff));
break;
}
break;
default:
printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
break;
}
return res;
}
#endif
static void mainboard_init(device_t dev)
{
lan_init();
@@ -137,10 +37,6 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
#if CONFIG_VGA_ROM_RUN
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
#endif
}
struct chip_operations mainboard_ops = {