soc/intel/quark: Prepare for FSP2.0 support

Split the original contents of romstage.c into car.c, romstage.c and
fsp1_1.c.

TEST=Build and run on Galileo Gen2

Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15862
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/quark/Makefile.inc

@@ -34,6 +34,7 @@ romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += chip.c
 ramstage-y += ehci.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c
 ramstage-y += gpio_i2c.c
 ramstage-y += i2c.c
 ramstage-y += lpc.c