soc/intel/quark: Prepare for FSP2.0 support

Split the original contents of romstage.c into car.c, romstage.c and
fsp1_1.c.

TEST=Build and run on Galileo Gen2

Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15862
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/quark/include/soc/pm.h

@@ -24,6 +24,7 @@ struct chipset_power_state {
 	uint32_t prev_sleep_state;
 } __attribute__ ((packed));
 
+struct chipset_power_state *get_power_state(void);
 struct chipset_power_state *fill_power_state(void);
 
 #endif

src/soc/intel/quark/include/soc/ramstage.h

@@ -23,5 +23,6 @@
 #include <soc/QuarkNcSocId.h>
 
 void mainboard_gpio_i2c_init(device_t dev);
+void fsp_silicon_init(void);
 
 #endif /* _SOC_RAMSTAGE_H_ */

src/soc/intel/quark/include/soc/romstage.h

@@ -26,6 +26,8 @@
 #include <soc/reg_access.h>
 
 asmlinkage void *car_stage_c_entry(void);
+void clear_smi_and_wake_events(void);
+void disable_rom_shadow(void);
 void report_platform_info(void);
 int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base);
 void pcie_init(void);