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Enable CNVi wake, document all RTD3 pins with names from schematics

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Change-Id: I5581b39b3d4a072124cbb09cc4fbe16a671eb700
This commit is contained in:
Jeremy Soller
2020-11-24 08:54:16 -07:00
parent b4dcbd3c28
commit 0182cebfbc
2 changed files with 15 additions and 14 deletions
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10
src/mainboard/system76/galp5/devicetree.cb
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@@ -185,17 +185,17 @@ chip soc/intel/tigerlake
end end
device ref shared_ram on end device ref shared_ram on end
device ref cnvi_wifi on device ref cnvi_wifi on
# chip drivers/wifi/generic chip drivers/wifi/generic
# register "wake" = "GPE0_PME_B0" register "wake" = "GPE0_PME_B0"
# device generic 0 on end device generic 0 on end
# end end
end end
device ref i2c0 on device ref i2c0 on
# Touchpad I2C bus # Touchpad I2C bus
register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
chip drivers/i2c/hid chip drivers/i2c/hid
register "generic.hid" = ""PNP0C50"" register "generic.hid" = ""PNP0C50""
register "generic.desc" = ""TODO Touchpad"" register "generic.desc" = ""FocalTech Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)"
register "generic.probed" = "1" register "generic.probed" = "1"
register "hid_desc_reg_offset" = "0x01" register "hid_desc_reg_offset" = "0x01"

19
src/mainboard/system76/lemp10/devicetree.cb
View File

@@ -142,8 +142,8 @@ chip soc/intel/tigerlake
register "PcieClkSrcClkReq[3]" = "3" register "PcieClkSrcClkReq[3]" = "3"
#TODO #TODO
# chip soc/intel/common/block/pcie/rtd3 # chip soc/intel/common/block/pcie/rtd3
# register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)" # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)" # SSD1_PWR_DN#
# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # GPP_C12_RTD3 (labeled incorrectly)
# #TODO: Support disable/enable CPU RP clock # #TODO: Support disable/enable CPU RP clock
# register "srcclk_pin" = "-1" # register "srcclk_pin" = "-1"
# device generic 0 on end # device generic 0 on end
@@ -181,10 +181,10 @@ chip soc/intel/tigerlake
end end
device ref shared_ram on end device ref shared_ram on end
device ref cnvi_wifi on device ref cnvi_wifi on
# chip drivers/wifi/generic chip drivers/wifi/generic
# register "wake" = "GPE0_PME_B0" register "wake" = "GPE0_PME_B0"
# device generic 0 on end device generic 0 on end
# end end
end end
device ref i2c0 on device ref i2c0 on
# Touchpad I2C bus # Touchpad I2C bus
@@ -225,7 +225,8 @@ chip soc/intel/tigerlake
register "PcieRpEnable[5]" = "1" register "PcieRpEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "1" register "PcieRpLtrEnable[5]" = "1"
register "PcieClkSrcUsage[2]" = "5" register "PcieClkSrcUsage[2]" = "5"
register "PcieClkSrcClkReq[2]" = "2" end register "PcieClkSrcClkReq[2]" = "2"
end
device ref pcie_rp9 on device ref pcie_rp9 on
# PCIe root port #9 x4, Clock 0 (SSD2) # PCIe root port #9 x4, Clock 0 (SSD2)
register "PcieRpEnable[8]" = "1" register "PcieRpEnable[8]" = "1"
@@ -233,8 +234,8 @@ chip soc/intel/tigerlake
register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcUsage[0]" = "8"
register "PcieClkSrcClkReq[0]" = "0" register "PcieClkSrcClkReq[0]" = "0"
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_DN#
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)" # GPP_D13_RTD3 (labeled incorrectly)
register "srcclk_pin" = "0" register "srcclk_pin" = "0"
device generic 0 on end device generic 0 on end
end end