- Update abuild.sh so it will rebuild successfull builds
- Move pci_set_method out of hardwaremain.c - Re-add debugging name field but only include the CONFIG_CHIP_NAME is enabled. All instances are now wrapped in CHIP_NAME - Many minor cleanups so most ports build. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@@ -4,7 +4,7 @@
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#include <string.h>
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#include <stdint.h>
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void *smp_write_config_table(void *v, unsigned long * processor_map)
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void *smp_write_config_table(void *v)
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{
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static const char sig[4] = "PCMP";
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static const char oem[8] = "IBM ";
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@@ -35,7 +35,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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mc->mpe_checksum = 0;
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mc->reserved = 0;
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smp_write_processors(mc, processor_map);
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smp_write_processors(mc);
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{
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device_t dev;
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@@ -83,20 +83,22 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
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{
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device_t dev;
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uint32_t base;
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struct resource *res;
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/* 8131-1 apic #3 */
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dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
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if (dev) {
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base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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base &= PCI_BASE_ADDRESS_MEM_MASK;
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smp_write_ioapic(mc, 0x03, 0x11, base);
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, 0x03, 0x11, res->base);
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}
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}
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/* 8131-2 apic #4 */
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dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
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if (dev) {
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base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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base &= PCI_BASE_ADDRESS_MEM_MASK;
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smp_write_ioapic(mc, 0x04, 0x11, base);
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, 0x04, 0x11, res->base);
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}
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}
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}
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@@ -164,10 +166,10 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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return smp_next_mpe_entry(mc);
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}
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unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr);
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return (unsigned long)smp_write_config_table(v, processor_map);
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return (unsigned long)smp_write_config_table(v);
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}
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