This patch is from 2009-10-20

Convert all DEBUG_SMBUS, DEBUG_SMI, and DEBUG_RAM_SETUP custom and
local #defines into globally configurable kconfig options (and Options.lb
options for as long as newconfig still exists) which can be enabled
by the user in the "Debugging" menu.

The respective menu items only appear if a board is selected where the
chipset code actually provides such additional DEBUG output.

All three variables default to 0 / off for now.

Also, drop a small chunk of dead/useless code in the
src/northbridge/via/cn700/raminit.c file, which would otherwise break
compilation.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>

Reworked to still apply to trunk, added X86EMU_DEBUG (and make the x86emu/yabel
code only work printf instead of a redefined version of printk and 
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/Kconfig

@@ -609,6 +609,190 @@ config GDB_STUB
 	  If enabled, you will be able to set breakpoints for gdb debugging.
 	  See src/arch/i386/lib/c_start.S for details.
 
+config DEBUG_RAM_SETUP
+	bool "Output verbose RAM init debug messages"
+	default n
+	depends on (NORTHBRIDGE_AMD_AMDFAM10 \
+		 || NORTHBRIDGE_AMD_AMDK8 \
+		 || NORTHBRIDGE_VIA_CN700 \
+		 || NORTHBRIDGE_VIA_CX700 \
+		 || NORTHBRIDGE_VIA_VX800 \
+		 || NORTHBRIDGE_INTEL_E7501 \
+		 || NORTHBRIDGE_INTEL_I440BX \
+		 || NORTHBRIDGE_INTEL_I82810 \
+		 || NORTHBRIDGE_INTEL_I82830 \
+		 || NORTHBRIDGE_INTEL_I945)
+	help
+	  This option enables additional RAM init related debug messages.
+	  It is recommended to enable this when debugging issues on your
+	  board which might be RAM init related.
+
+	  Note: This option will increase the size of the coreboot image.
+
+	  If unsure, say N.
+
+config DEBUG_SMBUS
+	bool "Output verbose SMBus debug messages"
+	default n
+	depends on (SOUTHBRIDGE_VIA_VT8237R \
+		 || NORTHBRIDGE_VIA_VX800 \
+		 || NORTHBRIDGE_VIA_CX700 \
+		 || NORTHBRIDGE_AMD_AMDK8)
+	help
+	  This option enables additional SMBus (and SPD) debug messages.
+
+	  Note: This option will increase the size of the coreboot image.
+
+	  If unsure, say N.
+
+config DEBUG_SMI
+	bool "Output verbose SMI debug messages"
+	default n
+	depends on HAVE_SMI_HANDLER
+	help
+	  This option enables additional SMI related debug messages.
+
+	  Note: This option will increase the size of the coreboot image.
+
+	  If unsure, say N.
+
+config X86EMU_DEBUG
+	bool "Output verbose x86emu debug messages"
+	default n
+	depends on PCI_OPTION_ROM_RUN_YABEL
+	help
+	  This option enables additional x86emu related debug messages.
+
+	  Note: This option will increase the size of the coreboot image.
+
+	  If unsure, say N.
+
+config X86EMU_DEBUG_JMP
+	bool "Trace JMP/RETF"
+	default n
+	depends on X86EMU_DEBUG
+	help
+	  Print information about JMP and RETF opcodes from x86emu.
+
+	  Note: This option will increase the size of the coreboot image.
+
+	  If unsure, say N.
+
+config X86EMU_DEBUG_TRACE
+	bool "Trace all opcodes"
+	default n
+	depends on X86EMU_DEBUG
+	help
+	  Print _all_ opcodes that are executed by x86emu.
+	  
+	  WARNING: This will produce a LOT of output and take a long time.
+
+	  Note: This option will increase the size of the coreboot image.
+
+	  If unsure, say N.
+
+config X86EMU_DEBUG_PNP
+	bool "Log Plug&Play accesses"
+	default n
+	depends on X86EMU_DEBUG
+	help
+	  Print Plug And Play accesses made by option ROMs.
+
+	  Note: This option will increase the size of the coreboot image.
+
+	  If unsure, say N.
+
+config X86EMU_DEBUG_DISK
+	bool "Log Disk I/O"
+	default n
+	depends on X86EMU_DEBUG
+	help
+	  Print Disk I/O related messages.
+
+	  Note: This option will increase the size of the coreboot image.
+
+	  If unsure, say N.
+
+config X86EMU_DEBUG_PMM
+	bool "Log PMM"
+	default n
+	depends on X86EMU_DEBUG
+	help
+	  Print messages related to POST Memory Manager (PMM).
+
+	  Note: This option will increase the size of the coreboot image.
+
+	  If unsure, say N.
+
+
+config X86EMU_DEBUG_VBE
+	bool "Debug VESA BIOS Extensions"
+	default n
+	depends on X86EMU_DEBUG
+	help
+	  Print messages related to VESA BIOS Extension (VBE) functions.
+
+	  Note: This option will increase the size of the coreboot image.
+
+	  If unsure, say N.
+
+config X86EMU_DEBUG_INT10
+	bool "Redirect INT10 output to console"
+	default n
+	depends on X86EMU_DEBUG
+	help
+	  Let INT10 (i.e. character output) calls print messages to debug output.
+
+	  Note: This option will increase the size of the coreboot image.
+
+	  If unsure, say N.
+
+config X86EMU_DEBUG_INTERRUPTS
+	bool "Log intXX calls"
+	default n
+	depends on X86EMU_DEBUG
+	help
+	  Print messages related to interrupt handling.
+
+	  Note: This option will increase the size of the coreboot image.
+
+	  If unsure, say N.
+
+config X86EMU_DEBUG_CHECK_VMEM_ACCESS
+	bool "Log special memory accesses"
+	default n
+	depends on X86EMU_DEBUG
+	help
+	  Print messages related to accesses to certain areas of the virtual
+	  memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
+
+	  Note: This option will increase the size of the coreboot image.
+
+	  If unsure, say N.
+
+config X86EMU_DEBUG_MEM
+	bool "Log all memory accesses"
+	default n
+	depends on X86EMU_DEBUG
+	help
+	  Print memory accesses made by option ROM.
+	  Note: This also includes accesses to fetch instructions.
+
+	  Note: This option will increase the size of the coreboot image.
+
+	  If unsure, say N.
+
+config X86EMU_DEBUG_IO
+	bool "Log IO accesses"
+	default n
+	depends on X86EMU_DEBUG
+	help
+	  Print I/O accesses made by option ROM.
+
+	  Note: This option will increase the size of the coreboot image.
+
+	  If unsure, say N.
+
 endmenu
 
 config LIFT_BSP_APIC_ID

src/console/printk.c

@@ -19,8 +19,6 @@
 /* Keep together for sysctl support */
 
 int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
-int default_message_loglevel = DEFAULT_MESSAGE_LOGLEVEL;
-int minimum_console_loglevel = MINIMUM_CONSOLE_LOGLEVEL;
 int default_console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
 
 DECLARE_SPIN_LOCK(console_lock)

src/cpu/x86/smm/smihandler.c

@@ -27,8 +27,6 @@
 
 void southbridge_smi_set_eos(void);
 
-/* To enable SMI define DEBUG_SMI in smiutil.c */
-
 typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
 
 /* SMI multiprocessing semaphore */

src/cpu/x86/smm/smiutil.c

@@ -25,8 +25,6 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
 
-// #define DEBUG_SMI
-
 /* ********************* smi_util ************************* */
 
 /* Data */
@@ -119,7 +117,7 @@ void uart_init(void)
 
 void console_init(void)
 {
-#ifdef DEBUG_SMI
+#if CONFIG_DEBUG_SMI
 	console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
 	uart_init();
 #else

src/devices/Kconfig

@@ -74,63 +74,6 @@ config PCI_OPTION_ROM_RUN_YABEL
 
 endchoice
 
-# TODO: Describe better, and/or make a "choice" selection for this.
-config YABEL_DEBUG_FLAGS
-	prompt "Hex value for YABEL debug flags"
-	hex
-	default 0x0
-	depends on PCI_OPTION_ROM_RUN_YABEL
-	help
-	  CONFIG_YABEL_DEBUG_FLAGS is a binary switch that allows you
-	  to select the following items to debug. 1=on 0=off. After you
-	  decide what you want to debug create the binary value, convert to
-	  hex and set the option.
-
-	  Example for "debug all":
-	    CONFIG_YABEL_DEBUG_FLAGS = 0x31FF
-
-	  |-DEBUG_JMP - Print info about JMP and RETF opcodes from x86emu
-	  ||-DEBUG_TRACE_X86EMU - Print _all_ opcodes that are executed by
-	  ||                      x86emu (WARNING: this will produce a LOT
-	  ||                      of output)
-	  |||-Currently unused
-	  ||||-Currently unused
-	  |||||-Currently unused
-	  ||||||-DEBUG_PNP - Print Plug And Play accesses made by option ROM
-	  |||||||-DEBUG_DISK - Print Disk I/O related messages, currently unused
-	  ||||||||-DEBUG_PMM - Print messages related to POST Memory
-	  ||||||||             Manager (PMM)
-	  |||||||||-DEBUG_VBE - Print messages related to VESA BIOS Extension
-	  |||||||||             (VBE) functions
-	  ||||||||||-DEBUG_PRINT_INT10 - Let INT10 (i.e. character output)
-	  ||||||||||                     calls print messages to debug output
-	  |||||||||||-DEBUG_INTR - Print messages related to interrupt handling
-	  ||||||||||||-DEBUG_CHECK_VMEM_ACCESS - Print messages related to
-	  ||||||||||||                           accesses to certain areas of
-	  ||||||||||||                           the virtual memory (e.g. BDA
-	  ||||||||||||                           (BIOS Data Area) or interrupt
-	  ||||||||||||                           vectors)
-	  |||||||||||||-DEBUG_MEM - Print memory accesses made by option ROM
-	  |||||||||||||             (NOTE: this also includes accesses to
-	  |||||||||||||             fetch instructions)
-	  ||||||||||||||-DEBUG_IO - Print I/O accesses made by option ROM
-	  11000111111111 - Maximum binary value, i.e. "debug all"
-	                   (WARNING: This could run for hours)
-
-	  DEBUG_IO			0x0001
-	  DEBUG_MEM			0x0002
-	  DEBUG_CHECK_VMEM_ACCESS	0x0004
-	  DEBUG_INTR			0x0008
-	  DEBUG_PRINT_INT10		0x0010
-	  DEBUG_VBE			0x0020
-	  DEBUG_PMM			0x0040
-	  DEBUG_DISK			0x0080
-	  DEBUG_PNP			0x0100
-	  DEBUG_TRACE_X86EMU		0x1000
-	  DEBUG_JMP			0x2000
-
-	  See debug.h for values. 0 is no debug output, 0x31ff is _verbose_.
-
 config YABEL_PCI_ACCESS_OTHER_DEVICES
 	prompt "Allow option ROMs to access other devices"
 	bool
@@ -150,6 +93,11 @@ config YABEL_VIRTMEM_LOCATION
 	  YABEL requires 1MB memory for its CPU emulation. This memory is
 	  normally located at 16MB.
 
+config YABEL_VIRTMEM_LOCATION
+	hex
+	depends on PCI_OPTION_ROM_RUN_YABEL && !EXPERT
+	default 0x1000000
+
 config YABEL_DIRECTHW
 	prompt "Direct hardware access"
 	bool

src/mainboard/amd/dbm690t/romstage.c

@@ -57,7 +57,6 @@
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
@@ -67,6 +66,7 @@
 
 #include "southbridge/amd/rs690/rs690_early_setup.c"
 #include "southbridge/amd/sb600/sb600_early_setup.c"
+#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
 
 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
 static void memreset(int controllers, const struct mem_controller *ctrl)

src/mainboard/amd/pistachio/romstage.c

@@ -51,7 +51,6 @@
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
@@ -61,6 +60,7 @@
 
 #include "southbridge/amd/rs690/rs690_early_setup.c"
 #include "southbridge/amd/sb600/sb600_early_setup.c"
+#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
 
 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
 static void memreset(int controllers, const struct mem_controller *ctrl)

src/mainboard/amd/serengeti_cheetah_fam10/romstage.c

@@ -29,8 +29,6 @@
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
-#define DEBUG_SMBUS 1
-
 #define SET_NB_CFG_54 1
 
 //used by raminit

src/mainboard/asus/a8n_e/romstage.c

@@ -30,9 +30,6 @@
 /* Used by raminit. */
 #define QRANK_DIMM_SUPPORT 1
 
-/* Turn this on for SMBus debugging output. */
-#define DEBUG_SMBUS 0
-
 #if CONFIG_LOGICAL_CPUS == 1
 #define SET_NB_CFG_54 1
 #endif

src/mainboard/asus/a8v-e_se/romstage.c

@@ -40,8 +40,6 @@ unsigned int get_sbdn(unsigned bus);
 /* If we want to wait for core1 done before DQS training, set it to 0. */
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-/* #define DEBUG_SMBUS 1 */
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -59,10 +57,10 @@ unsigned int get_sbdn(unsigned bus);
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/asus/m2v-mx_se/romstage.c

@@ -44,8 +44,6 @@ unsigned int get_sbdn(unsigned bus);
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
-/* #define DEBUG_SMBUS 1 */
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>

src/mainboard/kontron/986lcd-m/romstage.c

@@ -445,7 +445,7 @@ void real_main(unsigned long bist)
 
 #if !CONFIG_HAVE_ACPI_RESUME
 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if defined(DEBUG_RAM_SETUP)
+#if CONFIG_DEBUG_RAM_SETUP
 	sdram_dump_mchbar_registers();
 #endif
 

src/mainboard/msi/ms7135/romstage.c

@@ -30,9 +30,6 @@
 /* Used by raminit. */
 #define QRANK_DIMM_SUPPORT 1
 
-/* Turn this on for SMBus debugging output. */
-#define DEBUG_SMBUS 0
-
 #if CONFIG_LOGICAL_CPUS == 1
 #define SET_NB_CFG_54 1
 #endif

src/mainboard/msi/ms7260/romstage.c

@@ -24,7 +24,6 @@
 #define __PRE_RAM__
 
 // #define CACHE_AS_RAM_ADDRESS_DEBUG 1
-// #define DEBUG_SMBUS 1
 // #define RAM_TIMING_DEBUG 1
 // #define DQS_TRAIN_DEBUG 1
 // #define RES_DEBUG 1

src/mainboard/msi/ms9185/romstage.c

@@ -42,8 +42,6 @@
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#define DEBUG_SMBUS 1
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>

src/mainboard/msi/ms9282/romstage.c

@@ -38,8 +38,6 @@
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#define DEBUG_SMBUS 1
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>

src/northbridge/amd/amdfam10/debug.c

@@ -220,11 +220,7 @@ static void dump_pci_devices_on_bus(u32 busn)
 	}
 }
 
-#ifndef DEBUG_SMBUS
-#define DEBUG_SMBUS 0
-#endif
-
-#if DEBUG_SMBUS == 1
+#if CONFIG_DEBUG_SMBUS
 
 static void dump_spd_registers(const struct mem_controller *ctrl)
 {

src/northbridge/amd/amdfam10/raminit_amdmct.c

@@ -23,21 +23,16 @@ static  void print_raminit(const char *strval, u32 val)
 	printk_debug("%s%08x\n", strval, val);
 }
 
-
-#define RAMINIT_DEBUG 1
-
-
 static  void print_tx(const char *strval, u32 val)
 {
-#if RAMINIT_DEBUG == 1
+#if CONFIG_DEBUG_RAM_SETUP
 	print_raminit(strval, val);
 #endif
 }
 
-
 static  void print_t(const char *strval)
 {
-#if RAMINIT_DEBUG == 1
+#if CONFIG_DEBUG_RAM_SETUP
 	print_debug(strval);
 #endif
 }

src/northbridge/amd/amdk8/debug.c

@@ -134,11 +134,8 @@ static void dump_pci_devices_on_bus(unsigned busn)
 	}
 }
 
-#ifndef DEBUG_SMBUS
-#define DEBUG_SMBUS 0
-#endif
+#if CONFIG_DEBUG_SMBUS
 
-#if DEBUG_SMBUS == 1
 static void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;

src/northbridge/amd/amdk8/raminit_f.c

@@ -34,9 +34,7 @@
 #define QRANK_DIMM_SUPPORT 0
 #endif
 
-#define RAM_TIMING_DEBUG 0
-
-#if RAM_TIMING_DEBUG == 1
+#if DEBUG_RAM_SETUP
 #define printk_raminit printk_debug
 #else
 #define printk_raminit(fmt, arg...)

src/northbridge/intel/e7501/raminit.c

@@ -22,10 +22,7 @@
 // Unfortunately the code seems to chew up several K of space.
 //#define VALIDATE_DIMM_COMPATIBILITY
 
-// Uncomment this to enable local debugging messages
-//#define DEBUG_RAM_CONFIG
-
-#if defined(DEBUG_RAM_CONFIG)
+#if CONFIG_DEBUG_RAM_SETUP
 #define RAM_DEBUG_MESSAGE(x)	print_debug(x)
 #define RAM_DEBUG_HEX32(x)		print_debug_hex32(x)
 #define RAM_DEBUG_HEX8(x)		print_debug_hex8(x)

src/northbridge/intel/i440bx/raminit.c

@@ -28,11 +28,8 @@
 Macros and definitions.
 -----------------------------------------------------------------------------*/
 
-/* Uncomment this to enable debugging output. */
-#define DEBUG_RAM_SETUP 1
-
 /* Debugging macros. */
-#if defined(DEBUG_RAM_SETUP)
+#if CONFIG_DEBUG_RAM_SETUP
 #define PRINT_DEBUG(x)		print_debug(x)
 #define PRINT_DEBUG_HEX8(x)	print_debug_hex8(x)
 #define PRINT_DEBUG_HEX16(x)	print_debug_hex16(x)

src/northbridge/intel/i82810/raminit.c

@@ -29,11 +29,8 @@
 Macros and definitions.
 -----------------------------------------------------------------------------*/
 
-/* Uncomment this to enable debugging output. */
-// #define DEBUG_RAM_SETUP 1
-
 /* Debugging macros. */
-#if defined(DEBUG_RAM_SETUP)
+#if CONFIG_DEBUG_RAM_SETUP
 #define PRINT_DEBUG(x)		print_debug(x)
 #define PRINT_DEBUG_HEX8(x)	print_debug_hex8(x)
 #define PRINT_DEBUG_HEX16(x)	print_debug_hex16(x)

src/northbridge/intel/i82830/raminit.c

@@ -29,11 +29,8 @@
 Macros and definitions.
 -----------------------------------------------------------------------------*/
 
-/* Uncomment this to enable debugging output. */
-/* #define DEBUG_RAM_SETUP 1 */
-
 /* Debugging macros. */
-#if defined(DEBUG_RAM_SETUP)
+#if CONFIG_DEBUG_RAM_SETUP
 #define PRINT_DEBUG(x)		print_debug(x)
 #define PRINT_DEBUG_HEX8(x)	print_debug_hex8(x)
 #define PRINT_DEBUG_HEX16(x)	print_debug_hex16(x)

src/northbridge/intel/i945/raminit.c

@@ -24,10 +24,8 @@
 #include "raminit.h"
 #include "i945.h"
 
-#define DEBUG_RAM_SETUP
-
 /* Debugging macros. */
-#if defined(DEBUG_RAM_SETUP)
+#if CONFIG_DEBUG_RAM_SETUP
 #define PRINTK_DEBUG(x...)	printk_debug(x)
 #else
 #define PRINTK_DEBUG(x...)
@@ -73,7 +71,7 @@ static void ram_read32(u32 offset)
 	read32(offset);
 }
 
-#ifdef DEBUG_RAM_SETUP
+#if CONFIG_DEBUG_RAM_SETUP
 static void sdram_dump_mchbar_registers(void)
 {
 	int i;

src/northbridge/via/cn700/raminit.c

@@ -25,9 +25,7 @@
 #include <delay.h>
 #include "cn700.h"
 
-// #define DEBUG_RAM_SETUP 1
-
-#ifdef DEBUG_RAM_SETUP
+#ifdef CONFIG_DEBUG_RAM_SETUP
 #define PRINT_DEBUG_MEM(x)		print_debug(x)
 #define PRINT_DEBUG_MEM_HEX8(x)		print_debug_hex8(x)
 #define PRINT_DEBUG_MEM_HEX16(x)	print_debug_hex16(x)
@@ -51,12 +49,6 @@ static void do_ram_command(device_t dev, u8 command)
 	reg &= 0xf8;		/* Clear bits 2-0. */
 	reg |= command;
 	pci_write_config8(dev, DRAM_MISC_CTL, reg);
-
-	PRINT_DEBUG_MEM("    Sending RAM command 0x");
-	PRINT_DEBUG_MEM_HEX8(reg);
-	PRINT_DEBUG_MEM(" to 0x");
-	PRINT_DEBUG_MEM_HEX32(0 + addr_offset);
-	PRINT_DEBUG_MEM("\r\n");
 }
 
 /**

src/northbridge/via/cx700/cx700_early_smbus.c

@@ -48,10 +48,7 @@
 #define SMBUS_DELAY()		outb(0x80, 0x80)
 
 /* Debugging macros. */
-
-// #define DEBUG_SMBUS 1
-
-#ifdef DEBUG_SMBUS
+#if CONFIG_DEBUG_SMBUS
 #define PRINT_DEBUG(x)		print_debug(x)
 #define PRINT_DEBUG_HEX16(x)	print_debug_hex16(x)
 #else
@@ -102,7 +99,7 @@ static void smbus_wait_until_ready(void)
 		SMBUS_DELAY();
 		++loops;
 	}
-#ifdef DEBUG_SMBUS
+#if CONFIG_DEBUG_SMBUS
 	/* Some systems seem to have a flakey SMBus. No need to spew a lot of
 	 * errors on those, once we know that SMBus access is principally
 	 * working.
@@ -234,7 +231,7 @@ static void enable_smbus(void)
 }
 
 /* Debugging Function */
-#ifdef DEBUG_SMBUS
+#ifdef CONFIG_DEBUG_SMBUS
 static void dump_spd_data(const struct mem_controller *ctrl)
 {
 	int dimm, offset, regs;

src/northbridge/via/cx700/raminit.c

@@ -24,10 +24,8 @@
 #include <delay.h>
 #include "cx700_registers.h"
 
-// #define DEBUG_RAM_SETUP 1
-
 /* Debugging macros. */
-#if defined(DEBUG_RAM_SETUP)
+#if CONFIG_DEBUG_RAM_SETUP
 #define PRINTK_DEBUG(x...)      printk_debug(x)
 #else
 #define PRINTK_DEBUG(x...)

src/northbridge/via/vx800/raminit.c

@@ -21,9 +21,7 @@
 #include <sdram_mode.h>
 #include <delay.h>
 
-#define DEBUG_RAM_SETUP 1
-
-#ifdef DEBUG_RAM_SETUP
+#if CONFIG_DEBUG_RAM_SETUP
 #define PRINT_DEBUG_MEM(x)		print_debug(x)
 #define PRINT_DEBUG_MEM_HEX8(x)		print_debug_hex8(x)
 #define PRINT_DEBUG_MEM_HEX16(x)	print_debug_hex16(x)

src/northbridge/via/vx800/vx800_early_smbus.c

@@ -49,11 +49,7 @@
 
 #define SMBUS_DELAY()		outb(0x80, 0x80)
 
-/* Debugging macros. Only necessary if something isn't working right */
-
-#define DEBUG_SMBUS 1
-
-#ifdef DEBUG_SMBUS
+#ifdef CONFIG_DEBUG_SMBUS
 #define PRINT_DEBUG(x)		print_debug(x)
 #define PRINT_DEBUG_HEX16(x)	print_debug_hex16(x)
 #else
@@ -289,7 +285,7 @@ void smbus_fixup(const struct mem_controller *ctrl)
 }
 
 /* Debugging Function */
-#ifdef DEBUG_SMBUS
+#if CONFIG_DEBUG_SMBUS
 static void dump_spd_data(void)
 {
 	int dimm, offset, regs;

src/southbridge/intel/i82801gx/i82801gx_smihandler.c

@@ -28,8 +28,6 @@
 #include <device/pci_def.h>
 #include "i82801gx.h"
 
-#define DEBUG_SMI
-
 #define APM_CNT		0xb2
 #define   CST_CONTROL	0x85
 #define   PST_CONTROL	0x80

src/southbridge/via/vt8237r/vt8237r.h

@@ -65,7 +65,7 @@
 #define I2C_TRANS_CMD			0x40
 #define CLOCK_SLAVE_ADDRESS		0x69
 
-#if DEBUG_SMBUS == 1
+#if CONFIG_DEBUG_SMBUS
 #define PRINT_DEBUG(x)		print_debug(x)
 #define PRINT_DEBUG_HEX16(x)	print_debug_hex16(x)
 #else