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Inagua: Synchronize AMD/inagua mainboard.

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AMD/persimmon mainboard code is derived from AMD/inagua mainbard.
Persimmom update a lot in the last few month, sync these modification to inagua.

Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/542
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Kerry Sheh 2012-01-19 13:18:36 +08:00 committed by Marc Jones
parent 91be49b2d0
commit 01f7ab9335
24 changed files with 249 additions and 717 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

122
src/mainboard/amd/inagua/BiosCallOuts.c
View File

@ -19,13 +19,12 @@
#include "agesawrapper.h" #include "agesawrapper.h"
#include "amdlib.h" #include "amdlib.h"
#include "dimmSpd.h"
#include "BiosCallOuts.h" #include "BiosCallOuts.h"
#include "Ids.h"
#include "OptionsIds.h"
#include "heapManager.h" #include "heapManager.h"
#include "SB800.h" #include "SB800.h"
STATIC BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] = STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
{ {
{AGESA_ALLOCATE_BUFFER, {AGESA_ALLOCATE_BUFFER,
BiosAllocateBuffer BiosAllocateBuffer
@ -55,102 +54,44 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] =
BiosRunFuncOnAp BiosRunFuncOnAp
}, },
{AGESA_GET_IDS_INIT_DATA, {AGESA_GNB_PCIE_SLOT_RESET,
BiosGetIdsInitData BiosGnbPcieSlotReset
},
{AGESA_HOOKBEFORE_DRAM_INIT,
BiosHookBeforeDramInit
},
{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,
BiosHookBeforeDramInitRecovery
}, },
{AGESA_HOOKBEFORE_DQS_TRAINING, {AGESA_HOOKBEFORE_DQS_TRAINING,
BiosHookBeforeDQSTraining BiosHookBeforeDQSTraining
}, },
{AGESA_HOOKBEFORE_DRAM_INIT,
BiosHookBeforeDramInit
},
{AGESA_HOOKBEFORE_EXIT_SELF_REF, {AGESA_HOOKBEFORE_EXIT_SELF_REF,
BiosHookBeforeExitSelfRefresh BiosHookBeforeExitSelfRefresh
}, },
{AGESA_GNB_PCIE_SLOT_RESET,
BiosGnbPcieSlotReset
},
}; };
AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{ {
UINTN i; UINTN i;
AGESA_STATUS CalloutStatus; AGESA_STATUS CalloutStatus;
UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
for (i = 0; i < REQUIRED_CALLOUTS; i++) CalloutStatus = AGESA_UNSUPPORTED;
{
if (BiosCallouts[i].CalloutName == Func)
{
break;
}
}
if(i >= REQUIRED_CALLOUTS)
{
return AGESA_UNSUPPORTED;
}
for (i = 0; i < CallOutCount; i++) {
if (BiosCallouts[i].CalloutName == Func) {
CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
return CalloutStatus; return CalloutStatus;
}
CONST IDS_NV_ITEM IdsData[] =
{
/*{
AGESA_IDS_NV_MAIN_PLL_CON,
0x1
},
{
AGESA_IDS_NV_MAIN_PLL_FID_EN,
0x1
},
{
AGESA_IDS_NV_MAIN_PLL_FID,
0x8
},
{
AGESA_IDS_NV_CUSTOM_NB_PSTATE,
},
{
AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL,
},
{
AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL,
},
{
AGESA_IDS_NV_FORCE_NB_PSTATE,
},
*/
{
0xFFFF,
0xFFFF
}
};
#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
UINTN i;
IDS_NV_ITEM *IdsPtr;
IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr;
if (Data == IDS_CALLOUT_INIT) {
for (i = 0; i < NUM_IDS_ENTRIES; i++) {
IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue;
IdsPtr[i].IdsNvId = IdsData[i].IdsNvId;
} }
} }
return AGESA_SUCCESS;
}
return CalloutStatus;
}
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{ {
@ -210,7 +151,6 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
/* If BufferHandle has not been allocated on the heap, CurrNodePtr here points /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
to the end of the allocated nodes list. to the end of the allocated nodes list.
*/ */
} }
/* Find the node that best fits the requested buffer size */ /* Find the node that best fits the requested buffer size */
FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
@ -343,7 +283,6 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
/* Clear the BufferSize and NextNodeOffset of the previous first node */ /* Clear the BufferSize and NextNodeOffset of the previous first node */
FreedNodePtr->BufferSize = 0; FreedNodePtr->BufferSize = 0;
FreedNodePtr->NextNodeOffset = 0; FreedNodePtr->NextNodeOffset = 0;
} else { } else {
/* Otherwise, add freed node to the start of the list /* Otherwise, add freed node to the start of the list
Update NextNodeOffset and BufferSize to include the Update NextNodeOffset and BufferSize to include the
@ -390,7 +329,6 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
if (AllocNodeOffset == EndNodeOffset) { if (AllocNodeOffset == EndNodeOffset) {
PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
AllocNodePtr->BufferSize = 0; AllocNodePtr->BufferSize = 0;
AllocNodePtr->NextNodeOffset = 0; AllocNodePtr->NextNodeOffset = 0;
} else { } else {
@ -438,7 +376,7 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr); Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr);
return Status; return Status;
} }
@ -481,7 +419,7 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
Status = AmdMemoryReadSPD (Func, Data, ConfigPtr); Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr);
return Status; return Status;
} }
@ -511,7 +449,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
MemData = ConfigPtr; MemData = ConfigPtr;
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
/* Get SB800 MMIO Base (AcpiMmioAddr) */ /* Get SB MMIO Base (AcpiMmioAddr) */
WriteIo8 (0xCD6, 0x27); WriteIo8 (0xCD6, 0x27);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16 = Data8<<8; Data16 = Data8<<8;
@ -534,12 +472,14 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
TempData8 &= 0x23; TempData8 &= 0x23;
TempData8 |= Data8; TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~BIT5; Data8 &= ~BIT5;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
TempData8 &= 0x03; TempData8 &= 0x03;
TempData8 |= Data8; TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
Data8 |= BIT2+BIT3; Data8 |= BIT2+BIT3;
Data8 &= ~BIT4; Data8 &= ~BIT4;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
@ -575,6 +515,13 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
} }
return Status; return Status;
} }
/* Call the host environment interface to provide a user hook opportunity. */
AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
return AGESA_SUCCESS;
}
/* Call the host environment interface to provide a user hook opportunity. */ /* Call the host environment interface to provide a user hook opportunity. */
AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{ {
@ -607,8 +554,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
switch (ResetInfo->ResetId) switch (ResetInfo->ResetId)
{ {
case 4: case 4:
switch (ResetInfo->ResetControl) switch (ResetInfo->ResetControl) {
{
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 &= ~(UINT8)BIT6 ; Data8 &= ~(UINT8)BIT6 ;
@ -624,8 +570,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
} }
break; break;
case 6: case 6:
switch (ResetInfo->ResetControl) switch (ResetInfo->ResetControl) {
{
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 &= ~(UINT8)BIT6 ; Data8 &= ~(UINT8)BIT6 ;
@ -641,8 +586,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
} }
break; break;
case 7: case 7:
switch (ResetInfo->ResetControl) switch (ResetInfo->ResetControl) {
{
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 &= ~(UINT8)BIT6 ; Data8 &= ~(UINT8)BIT6 ;

2
src/mainboard/amd/inagua/BiosCallOuts.h
View File

@ -64,6 +64,8 @@ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPt
/* Call the host environment interface to provide a user hook opportunity. */ /* Call the host environment interface to provide a user hook opportunity. */
AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
/* Call the host environment interface to provide a user hook opportunity. */ /* Call the host environment interface to provide a user hook opportunity. */
AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
/* Call the host environment interface to provide a user hook opportunity. */
AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
/* PCIE slot reset control */ /* PCIE slot reset control */
AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);

25
src/mainboard/amd/inagua/Kconfig
View File

@ -22,8 +22,6 @@ if BOARD_AMD_INAGUA
config BOARD_SPECIFIC_OPTIONS # dummy config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y def_bool y
select ARCH_X86 select ARCH_X86
select DIMM_DDR3
select DIMM_UNREGISTERED
select CPU_AMD_AGESA_FAMILY14 select CPU_AMD_AGESA_FAMILY14
select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
select NORTHBRIDGE_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14
@ -81,18 +79,6 @@ config MEM_TRAIN_SEQ
int int
default 2 default 2
config SB_HT_CHAIN_ON_BUS0
int
default 1
config HT_CHAIN_END_UNITID_BASE
hex
default 0x1
config HT_CHAIN_UNITID_BASE
hex
default 0x0
config IRQ_SLOT_COUNT config IRQ_SLOT_COUNT
int int
default 11 default 11
@ -147,19 +133,10 @@ config VGA_BIOS_ID
depends on VGA_BIOS depends on VGA_BIOS
default "1002,9802" default "1002,9802"
config AHCI_ROM config SB800_AHCI_ROM
bool bool
default n default n
#config AHCI_ROM_FILE
# string "AHCI ROM path and filename"
# depends on AHCI_ROM
# default "rom/ahci/sb800.bin"
config AHCI_ROM_ID
string "AHCI device PCI IDs"
depends on AHCI_ROM
default "1002,4391"
endif # BOARD_AMD_INAGUA endif # BOARD_AMD_INAGUA

7
src/mainboard/amd/inagua/Makefile.inc
View File

@ -17,6 +17,13 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
# #
ifeq ($(CONFIG_AHCI_BIOS),y)
stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
pci$(stripped_ahcibios_id).rom-type := optionrom
endif
romstage-y += buildOpts.c romstage-y += buildOpts.c
romstage-y += agesawrapper.c romstage-y += agesawrapper.c
romstage-y += dimmSpd.c romstage-y += dimmSpd.c

6
src/mainboard/amd/inagua/OptionsIds.h
View File

@ -51,11 +51,9 @@
**/ **/
#define IDSOPT_IDS_ENABLED TRUE #define IDSOPT_IDS_ENABLED TRUE
//#define IDSOPT_CONTROL_ENABLED TRUE //#define IDSOPT_TRACING_ENABLED TRUE
#define IDSOPT_TRACING_ENABLED TRUE
//#define IDSOPT_PERF_ANALYSIS TRUE
#define IDSOPT_ASSERT_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE
//#undef IDSOPT_DEBUG_ENABLED
//#define IDSOPT_DEBUG_ENABLED FALSE //#define IDSOPT_DEBUG_ENABLED FALSE
//#undef IDSOPT_HOST_SIMNOW //#undef IDSOPT_HOST_SIMNOW
//#define IDSOPT_HOST_SIMNOW FALSE //#define IDSOPT_HOST_SIMNOW FALSE

58
src/mainboard/amd/inagua/PlatformGnbPcie.c
View File

@ -26,6 +26,34 @@
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This is the stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] **PeiServices
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
VOID *BrazosPciePortPtr;
VOID *BrazosPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_PORT_DESCRIPTOR PortList [] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
@ -83,34 +111,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
&DdiList[0] &DdiList[0]
}; };
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This is the stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] **PeiServices
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
VOID *BrazosPciePortPtr;
VOID *BrazosPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
// GNB PCIe topology Porting // GNB PCIe topology Porting
// //
@ -126,7 +126,7 @@ OemCustomizeInitEarly (
if ( Status!= AGESA_SUCCESS) { if ( Status!= AGESA_SUCCESS) {
// Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
ASSERT(FALSE); ASSERT(FALSE);
return Status; return;
} }
BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;

84
src/mainboard/amd/inagua/acpi/ssdt2.asl
View File

@ -1,84 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
{
Scope (_SB)
{
External (DADD, MethodObj)
External (GHCE, MethodObj)
External (GHCN, MethodObj)
External (GHCL, MethodObj)
External (GHCD, MethodObj)
External (GNUS, MethodObj)
External (GIOR, MethodObj)
External (GMEM, MethodObj)
External (GWBN, MethodObj)
External (GBUS, MethodObj)
External (PICF)
External (\_SB.PCI0.LNKA, DeviceObj)
External (\_SB.PCI0.LNKB, DeviceObj)
External (\_SB.PCI0.LNKC, DeviceObj)
External (\_SB.PCI0.LNKD, DeviceObj)
Device (PCIX)
{
// BUS ? Second HT Chain
Name (HCIN, 0xcc) // HC2 0x01
Name (_UID, 0xdd) // HC 0x03
Name (_HID, "PNP0A03")
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
{
Return (DADD(GHCN(HCIN), 0x00000000))
}
Method (_BBN, 0, NotSerialized)
{
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
}
Method (_STA, 0, NotSerialized)
{
Return (\_SB.GHCE(HCIN))
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate () { })
Store( GHCN(HCIN), Local4)
Store( GHCL(HCIN), Local5)
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
Return (Local3)
}
#include "acpi/pci2_hc.asl"
}
}
}

84
src/mainboard/amd/inagua/acpi/ssdt3.asl
View File

@ -1,84 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
{
Scope (_SB)
{
External (DADD, MethodObj)
External (GHCE, MethodObj)
External (GHCN, MethodObj)
External (GHCL, MethodObj)
External (GHCD, MethodObj)
External (GNUS, MethodObj)
External (GIOR, MethodObj)
External (GMEM, MethodObj)
External (GWBN, MethodObj)
External (GBUS, MethodObj)
External (PICF)
External (\_SB.PCI0.LNKA, DeviceObj)
External (\_SB.PCI0.LNKB, DeviceObj)
External (\_SB.PCI0.LNKC, DeviceObj)
External (\_SB.PCI0.LNKD, DeviceObj)
Device (PCIX)
{
// BUS ? Second HT Chain
Name (HCIN, 0xcc) // HC2 0x01
Name (_UID, 0xdd) // HC 0x03
Name (_HID, "PNP0A03")
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
{
Return (DADD(GHCN(HCIN), 0x00000000))
}
Method (_BBN, 0, NotSerialized)
{
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
}
Method (_STA, 0, NotSerialized)
{
Return (\_SB.GHCE(HCIN))
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate () { })
Store( GHCN(HCIN), Local4)
Store( GHCL(HCIN), Local5)
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
Return (Local3)
}
#include "acpi/pci3_hc.asl"
}
}
}

84
src/mainboard/amd/inagua/acpi/ssdt4.asl
View File

@ -1,84 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
{
Scope (_SB)
{
External (DADD, MethodObj)
External (GHCE, MethodObj)
External (GHCN, MethodObj)
External (GHCL, MethodObj)
External (GHCD, MethodObj)
External (GNUS, MethodObj)
External (GIOR, MethodObj)
External (GMEM, MethodObj)
External (GWBN, MethodObj)
External (GBUS, MethodObj)
External (PICF)
External (\_SB.PCI0.LNKA, DeviceObj)
External (\_SB.PCI0.LNKB, DeviceObj)
External (\_SB.PCI0.LNKC, DeviceObj)
External (\_SB.PCI0.LNKD, DeviceObj)
Device (PCIX)
{
// BUS ? Second HT Chain
Name (HCIN, 0xcc) // HC2 0x01
Name (_UID, 0xdd) // HC 0x03
Name (_HID, "PNP0A03")
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
{
Return (DADD(GHCN(HCIN), 0x00000000))
}
Method (_BBN, 0, NotSerialized)
{
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
}
Method (_STA, 0, NotSerialized)
{
Return (\_SB.GHCE(HCIN))
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate () { })
Store( GHCN(HCIN), Local4)
Store( GHCL(HCIN), Local5)
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
Return (Local3)
}
#include "acpi/pci4_hc.asl"
}
}
}

85
src/mainboard/amd/inagua/acpi/ssdt5.asl
View File

@ -1,85 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
{
Scope (_SB)
{
External (DADD, MethodObj)
External (GHCE, MethodObj)
External (GHCN, MethodObj)
External (GHCL, MethodObj)
External (GHCD, MethodObj)
External (GNUS, MethodObj)
External (GIOR, MethodObj)
External (GMEM, MethodObj)
External (GWBN, MethodObj)
External (GBUS, MethodObj)
External (PICF)
External (\_SB.PCI0.LNKA, DeviceObj)
External (\_SB.PCI0.LNKB, DeviceObj)
External (\_SB.PCI0.LNKC, DeviceObj)
External (\_SB.PCI0.LNKD, DeviceObj)
Device (PCIX)
{
// BUS ? Second HT Chain
Name (HCIN, 0xcc) // HC2 0x01
Name (_UID, 0xdd) // HC 0x03
Name (_HID, "PNP0A03")
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
{
Return (DADD(GHCN(HCIN), 0x00000000))
}
Method (_BBN, 0, NotSerialized)
{
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
}
Method (_STA, 0, NotSerialized)
{
Return (\_SB.GHCE(HCIN))
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate () { })
Store( GHCN(HCIN), Local4)
Store( GHCL(HCIN), Local5)
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
Return (Local3)
}
#include "acpi/pci5_hc.asl"
}
}
}

7
src/mainboard/amd/inagua/acpi_tables.c
View File

@ -20,6 +20,7 @@
#include <console/console.h> #include <console/console.h>
#include <string.h> #include <string.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/acpigen.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
@ -245,9 +246,10 @@ unsigned long write_acpi_tables(unsigned long start)
memcpy((void *)current, ssdt, ssdt->length); memcpy((void *)current, ssdt, ssdt->length);
ssdt = (acpi_header_t *) current; ssdt = (acpi_header_t *) current;
current += ssdt->length; current += ssdt->length;
acpi_add_table(rsdp,ssdt);
} }
else { else {
printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n");
} }
acpi_add_table(rsdp,ssdt); acpi_add_table(rsdp,ssdt);
#endif #endif
@ -275,6 +277,9 @@ unsigned long write_acpi_tables(unsigned long start)
printk(BIOS_DEBUG, "slit\n"); printk(BIOS_DEBUG, "slit\n");
dump_mem(slit, ((void *)slit) + slit->header.length); dump_mem(slit, ((void *)slit) + slit->header.length);
printk(BIOS_DEBUG, "alib\n");
dump_mem(ssdt, ((void *)alib) + alib->length);
printk(BIOS_DEBUG, "ssdt\n"); printk(BIOS_DEBUG, "ssdt\n");
dump_mem(ssdt, ((void *)ssdt) + ssdt->length); dump_mem(ssdt, ((void *)ssdt) + ssdt->length);

8
src/mainboard/amd/inagua/agesawrapper.c
View File

@ -57,7 +57,6 @@ VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL; VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL; VOID *AcpiAlib = NULL;
/*------------------------------------------------------------------------------ /*------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S * T Y P E D E F S A N D S T R U C T U R E S
*------------------------------------------------------------------------------ *------------------------------------------------------------------------------
@ -190,7 +189,6 @@ agesawrapper_amdinitreset (
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams, LibAmdMemFill (&AmdResetParams,
0, 0,
sizeof (AMD_RESET_PARAMS), sizeof (AMD_RESET_PARAMS),
@ -485,6 +483,12 @@ agesawrapper_amdinitlate (
AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
AcpiAlib = AmdLateParamsPtr->AcpiAlib; AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
" DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n"
" Mce:%p\n Cmc:%p\n Alib:%p\n",
__func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
/* Don't release the structure until coreboot has copied the ACPI tables. /* Don't release the structure until coreboot has copied the ACPI tables.
* AmdReleaseStruct (&AmdLateParams); * AmdReleaseStruct (&AmdLateParams);
*/ */

9
src/mainboard/amd/inagua/agesawrapper.h
View File

@ -22,7 +22,6 @@
*---------------------------------------------------------------------------------------- *----------------------------------------------------------------------------------------
*/ */
#ifndef _AGESAWRAPPER_H_ #ifndef _AGESAWRAPPER_H_
#define _AGESAWRAPPER_H_ #define _AGESAWRAPPER_H_
@ -39,7 +38,6 @@
#define AMD_APU_SSID 0x1234 #define AMD_APU_SSID 0x1234
#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum { enum {
PICK_DMI, /* DMI Interface */ PICK_DMI, /* DMI Interface */
PICK_PSTATE, /* Acpi Pstate SSDT Table */ PICK_PSTATE, /* Acpi Pstate SSDT Table */
@ -50,8 +48,6 @@ enum {
PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ PICK_ALIB, /* SACPI SSDT table with ALIB implementation */
}; };
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S * T Y P E D E F S A N D S T R U C T U R E S
*---------------------------------------------------------------------------------------- *----------------------------------------------------------------------------------------
@ -77,15 +73,18 @@ typedef struct {
*--------------------------------------------------------------------------------------- *---------------------------------------------------------------------------------------
*/ */
//void brazos_platform_stage(void);
UINT32 agesawrapper_amdinitreset (void); UINT32 agesawrapper_amdinitreset (void);
UINT32 agesawrapper_amdinitearly (void); UINT32 agesawrapper_amdinitearly (void);
UINT32 agesawrapper_amdinitenv (void); UINT32 agesawrapper_amdinitenv (void);
UINT32 agesawrapper_amdinitlate (void); UINT32 agesawrapper_amdinitlate (void);
UINT32 agesawrapper_amdinitpost (void); UINT32 agesawrapper_amdinitpost (void);
UINT32 agesawrapper_amdinitmid (void); UINT32 agesawrapper_amdinitmid (void);
UINT32 agesawrapper_amdreadeventlog (void); UINT32 agesawrapper_amdreadeventlog (void);
UINT32 agesawrapper_amdinitcpuio (void);
UINT32 agesawrapper_amdinitmmio (void); UINT32 agesawrapper_amdinitmmio (void);
UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
void *agesawrapper_getlateinitptr (int pick); void *agesawrapper_getlateinitptr (int pick);
#endif #endif

116
src/mainboard/amd/inagua/buildOpts.c
View File

@ -33,8 +33,6 @@
* @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
*/ */
#include "AGESA.h"
#include "CommonReturns.h"
#include "Filecode.h" #include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
@ -80,16 +78,16 @@
#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE
#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE
//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE
#define BLDOPT_REMOVE_ECC_SUPPORT FALSE #define BLDOPT_REMOVE_ECC_SUPPORT FALSE
//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE
//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE
#define BLDOPT_REMOVE_DQS_TRAINING FALSE #define BLDOPT_REMOVE_DQS_TRAINING FALSE
//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
#define BLDOPT_REMOVE_ACPI_PSTATES FALSE #define BLDOPT_REMOVE_ACPI_PSTATES FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
@ -97,17 +95,17 @@
#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE
//#define BLDOPT_REMOVE_SRAT TRUE #define BLDOPT_REMOVE_SRAT FALSE
//#define BLDOPT_REMOVE_SLIT TRUE #define BLDOPT_REMOVE_SLIT FALSE
//#define BLDOPT_REMOVE_WHEA TRUE #define BLDOPT_REMOVE_WHEA FALSE
//#define BLDOPT_REMOVE_DMI TRUE #define BLDOPT_REMOVE_DMI TRUE
//#define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_HT_ASSIST TRUE
//#define BLDOPT_REMOVE_ATM_MODE TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE
//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE
//#define BLDOPT_REMOVE_C6_STATE TRUE //#define BLDOPT_REMOVE_C6_STATE TRUE
//#define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_GFX_RECOVERY TRUE
#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
/* /*
@ -123,30 +121,7 @@
#define AGESA_ENTRY_INIT_S3SAVE TRUE #define AGESA_ENTRY_INIT_S3SAVE TRUE
#define AGESA_ENTRY_INIT_RESUME TRUE #define AGESA_ENTRY_INIT_RESUME TRUE
#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
/*
* Agesa configuration values selection.
* Uncomment and specify the value for the configuration options
* needed by the system.
*/
/* The fixed MTRR values to be set after memory initialization. */
CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
{
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1E },
{ CPU_LIST_TERMINAL }
};
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
@ -201,7 +176,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE //#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE
//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE //#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE
//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 //#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0
//#define BLDCFG_CFG_GNB_HD_AUDIO TRUE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE
//#define BLDCFG_CFG_ABM_SUPPORT FALSE //#define BLDCFG_CFG_ABM_SUPPORT FALSE
//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 //#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0
//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 //#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0
@ -244,7 +219,33 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
/*
* Agesa configuration values selection.
* Uncomment and specify the value for the configuration options
* needed by the system.
*/
#include "AGESA.h"
#include "CommonReturns.h"
/* The fixed MTRR values to be set after memory initialization. */
CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
{
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
{ CPU_LIST_TERMINAL }
};
/* Include the files that instantiate the configuration definitions. */ /* Include the files that instantiate the configuration definitions. */
#include "cpuRegisters.h" #include "cpuRegisters.h"
#include "cpuFamRegisters.h" #include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h" #include "cpuFamilyTranslation.h"
@ -253,7 +254,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
#include "CreateStruct.h" #include "CreateStruct.h"
#include "cpuFeatures.h" #include "cpuFeatures.h"
#include "Table.h" #include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h" #include "cpuEarlyInit.h"
#include "cpuLateInit.h" #include "cpuLateInit.h"
#include "GnbInterface.h" #include "GnbInterface.h"
@ -271,13 +271,37 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
* version string as appropriate for the release. The trunk copy of this file * version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X' * should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/ ****************************************************************************/
// This is the delivery package title, "BrazosPI" // This is the delivery package title, "BrazosPI"
// This string MUST be exactly 8 characters long // This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
// This is the release version number of the AGESA component // This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long // This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE*/
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
// The following definitions specify the default values for various parameters in which there are // The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product // no clearly defined defaults to be used in the common file. The values below are based on product
@ -373,7 +397,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
#include "mn.h" #include "mn.h"
//DA Customer table //DA Customer table
UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
{ {
// Hardcoded Memory Training Values // Hardcoded Memory Training Values
@ -415,7 +439,7 @@ UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
// TABLE END // TABLE END
NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
}; };
UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]); CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);
/* *************************************************************************** /* ***************************************************************************
* Optional User code to be included into the AGESA build * Optional User code to be included into the AGESA build

8
src/mainboard/amd/inagua/devicetree.cb
View File

@ -28,7 +28,7 @@ chip northbridge/amd/agesa/family14/root_complex
# device pci 18.0 on # northbridge # device pci 18.0 on # northbridge
chip northbridge/amd/agesa/family14 # PCI side of HT root complex chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
device pci 1.1 on end # Internal Multimedia device pci 1.1 on end # Internal Multimedia
device pci 4.0 on end # PCIE P2P bridge 0x9604 device pci 4.0 on end # PCIE P2P bridge 0x9604
device pci 5.0 off end # PCIE P2P bridge 0x9605 device pci 5.0 off end # PCIE P2P bridge 0x9605
@ -65,14 +65,14 @@ chip northbridge/amd/agesa/family14/root_complex
end end
end # kbc1100 end # kbc1100
end #LPC end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # USB 2 device pci 14.5 on end # USB 2
device pci 15.0 on end # PCIe PortA device pci 15.0 on end # PCIe PortA
device pci 15.1 on end # PCIe PortB device pci 15.1 on end # PCIe PortB
device pci 15.2 on end # PCIe PortC device pci 15.2 on end # PCIe PortC
device pci 15.3 on end # PCIe PortD device pci 15.3 on end # PCIe PortD
device pci 16.0 off end # OHCI USB3 device pci 16.0 on end # OHCI USB3
device pci 16.2 off end # EHCI USB3 device pci 16.2 on end # EHCI USB3
register "gpp_configuration" = "4" #1:1:1:1 register "gpp_configuration" = "4" #1:1:1:1
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800 end #southbridge/amd/cimx/sb800

39
src/mainboard/amd/inagua/dimmSpd.c
View File

@ -20,6 +20,7 @@
#include "Porting.h" #include "Porting.h"
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h" #include "amdlib.h"
#include "OEM.h" /* SMBUS0_BASE_ADDRESS */
AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info); AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) #define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
@ -30,13 +31,12 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
* SPD address table - porting required * SPD address table - porting required
*/ */
#define SMBUS_BASE_ADDR 0xB00 static const UINT8 spdAddressLookup [1] [2] [2] = // socket, channel, dimm
static const UINT8 spdAddressLookup [1] [2] [1] = // socket, channel, dimm
{ {
// socket 0 // socket 0
{ {
{0xA0}, // channel 0 dimms {0xA0, 0xA2}, // channel 0 dimms
{0xA2}, // channel 1 dimms {0x00, 0x00}, // channel 1 dimms
}, },
}; };
@ -46,7 +46,7 @@ static const UINT8 spdAddressLookup [1] [2] [1] = // socket, channel, dimm
*/ */
static int readSmbusByteData (int iobase, int address, char *buffer, int offset) static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
{ {
unsigned int status; unsigned int status;
UINT64 limit; UINT64 limit;
@ -60,8 +60,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
// time limit to avoid hanging for unexpected error status (should never happen) // time limit to avoid hanging for unexpected error status (should never happen)
limit = __rdtsc () + 2000000000 / 10; limit = __rdtsc () + 2000000000 / 10;
for (;;) for (;;) {
{
status = __inbyte (iobase); status = __inbyte (iobase);
if (__rdtsc () > limit) break; if (__rdtsc () > limit) break;
if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
@ -72,7 +71,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
buffer [0] = __inbyte (iobase + 5); buffer [0] = __inbyte (iobase + 5);
if (status == 2) status = 0; // check for done with no errors if (status == 2) status = 0; // check for done with no errors
return status; return status;
} }
/*----------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
* *
@ -81,7 +80,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
*/ */
static int readSmbusByte (int iobase, int address, char *buffer) static int readSmbusByte (int iobase, int address, char *buffer)
{ {
unsigned int status; unsigned int status;
UINT64 limit; UINT64 limit;
@ -90,8 +89,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
// time limit to avoid hanging for unexpected error status // time limit to avoid hanging for unexpected error status
limit = __rdtsc () + 2000000000 / 10; limit = __rdtsc () + 2000000000 / 10;
for (;;) for (;;) {
{
status = __inbyte (iobase); status = __inbyte (iobase);
if (__rdtsc () > limit) break; if (__rdtsc () > limit) break;
if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
@ -102,7 +100,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
buffer [0] = __inbyte (iobase + 5); buffer [0] = __inbyte (iobase + 5);
if (status == 2) status = 0; // check for done with no errors if (status == 2) status = 0; // check for done with no errors
return status; return status;
} }
/*--------------------------------------------------------------------------- /*---------------------------------------------------------------------------
* *
@ -114,7 +112,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
*/ */
static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
{ {
int index, error; int index, error;
/* read the first byte using offset zero */ /* read the first byte using offset zero */
@ -122,14 +120,13 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
if (error) return error; if (error) return error;
/* read the remaining bytes using auto-increment for speed */ /* read the remaining bytes using auto-increment for speed */
for (index = 1; index < count; index++) for (index = 1; index < count; index++) {
{
error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
if (error) return error; if (error) return error;
} }
return 0; return 0;
} }
static void writePmReg (int reg, int data) static void writePmReg (int reg, int data)
{ {
@ -138,16 +135,16 @@ static void writePmReg (int reg, int data)
} }
static void setupFch (int ioBase) static void setupFch (int ioBase)
{ {
writePmReg (0x2D, ioBase >> 8); writePmReg (0x2D, ioBase >> 8);
writePmReg (0x2C, ioBase | 1); writePmReg (0x2C, ioBase | 1);
writePmReg (0x29, 0x80); writePmReg (0x29, 0x80);
writePmReg (0x28, 0x61); writePmReg (0x28, 0x61);
__outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
} }
AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
{ {
int spdAddress, ioBase; int spdAddress, ioBase;
if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR;
@ -156,7 +153,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
if (spdAddress == 0) return AGESA_ERROR; if (spdAddress == 0) return AGESA_ERROR;
ioBase = SMBUS_BASE_ADDR; ioBase = SMBUS0_BASE_ADDRESS;
setupFch (ioBase); setupFch (ioBase);
return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
} }

9
src/mainboard/amd/inagua/dsdt.asl
View File

@ -27,7 +27,7 @@ DefinitionBlock (
0x00010001 /* OEM Revision */ 0x00010001 /* OEM Revision */
) )
{ /* Start of ASL file */ { /* Start of ASL file */
/* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */
/* Data to be patched by the BIOS during POST */ /* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */ /* FIXME the patching is not done yet! */
@ -36,7 +36,7 @@ DefinitionBlock (
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */ Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@ -1379,7 +1379,7 @@ DefinitionBlock (
/* Real Time Clock Device */ /* Real Time Clock Device */
Device(RTC0) { Device(RTC0) {
Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
Name(_CRS, ResourceTemplate() { Name(_CRS, ResourceTemplate() {
IRQNoFlags(){8} IRQNoFlags(){8}
IO(Decode16,0x0070, 0x0070, 0, 2) IO(Decode16,0x0070, 0x0070, 0, 2)
@ -1483,9 +1483,8 @@ DefinitionBlock (
0xF300 /* length */ 0xF300 /* length */
) )
#if 0
Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
#if 0
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */

4
src/mainboard/amd/inagua/fadt.c
View File

@ -40,9 +40,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memset((void *)fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4); memcpy(header->signature, "FACP", 4);
header->length = 244; header->length = 244;
header->revision = 1; header->revision = 3;
memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, "AMD ", 8); memcpy(header->oem_table_id, "COREBOOT", 8);
memcpy(header->asl_compiler_id, ASLC, 4); memcpy(header->asl_compiler_id, ASLC, 4);
header->asl_compiler_revision = 0; header->asl_compiler_revision = 0;

23
src/mainboard/amd/inagua/get_bus_conf.c
View File

@ -24,6 +24,7 @@
#include <stdint.h> #include <stdint.h>
#include <stdlib.h> #include <stdlib.h>
#include <cpu/amd/amdfam14.h> #include <cpu/amd/amdfam14.h>
#include "agesawrapper.h"
#if CONFIG_AMD_SB_CIMX #if CONFIG_AMD_SB_CIMX
#include <sb_cimx.h> #include <sb_cimx.h>
#endif #endif
@ -34,6 +35,7 @@
*/ */
u8 bus_isa; u8 bus_isa;
u8 bus_sb800[3]; u8 bus_sb800[3];
u32 apicid_sb800;
/* /*
* Here you only need to set value in pci1234 for HT-IO that could be installed or not * Here you only need to set value in pci1234 for HT-IO that could be installed or not
@ -44,27 +46,15 @@ u32 pci1234x[] = {
0x0000ff0, 0x0000ff0,
}; };
/*
* HT Chain device num, actually it is unit id base of every ht device in chain,
* assume every chain only have 4 ht device at most
*/
u32 hcdnx[] = {
0x20202020,
};
u32 bus_type[256]; u32 bus_type[256];
u32 sbdn_sb800; u32 sbdn_sb800;
//KZ [092110]extern void get_pci1234(void);
static u32 get_bus_conf_done = 0; static u32 get_bus_conf_done = 0;
void get_bus_conf(void) void get_bus_conf(void)
{ {
u32 apicid_base;
u32 status; u32 status;
device_t dev; device_t dev;
@ -105,7 +95,6 @@ void get_bus_conf(void)
bus_type[i] = 0; /* default ISA bus. */ bus_type[i] = 0; /* default ISA bus. */
} }
bus_type[0] = 1; /* pci */ bus_type[0] = 1; /* pci */
// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; // bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
@ -114,8 +103,6 @@ void get_bus_conf(void)
/* sb800 */ /* sb800 */
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
if (dev) { if (dev) {
bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
@ -133,12 +120,14 @@ void get_bus_conf(void)
bus_isa++; bus_isa++;
} }
} }
for (j = bus_sb800[2]; j < bus_isa; j++) for (j = bus_sb800[2]; j < bus_isa; j++)
bus_type[j] = 1; bus_type[j] = 1;
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
bus_isa = 10; bus_isa = 10;
apicid_base = CONFIG_MAX_CPUS;
apicid_sb800 = apicid_base;
#if CONFIG_AMD_SB_CIMX #if CONFIG_AMD_SB_CIMX
sb_Late_Post(); sb_Late_Post();

3
src/mainboard/amd/inagua/irq_tables.c
View File

@ -23,8 +23,7 @@
#include <string.h> #include <string.h>
#include <stdint.h> #include <stdint.h>
#include <arch/pirq_routing.h> #include <arch/pirq_routing.h>
//#include <cpu/amd/amdfam10_sysconf.h> #include <cpu/amd/amdfam14.h>
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,

14
src/mainboard/amd/inagua/mainboard.c
View File

@ -28,7 +28,8 @@
//#include <southbridge/amd/sb800/sb800.h> //#include <southbridge/amd/sb800/sb800.h>
#include "chip.h" #include "chip.h"
//#define SMBUS_IO_BASE 0x6000 void set_pcie_reset(void);
void set_pcie_dereset(void);
/** /**
* TODO * TODO
@ -49,11 +50,12 @@ void set_pcie_dereset(void)
uint64_t uma_memory_base, uma_memory_size; uint64_t uma_memory_base, uma_memory_size;
/************************************************* /*************************************************
* enable the dedicated function in inagua board. * enable the dedicated function in INAGUA board.
*************************************************/ *************************************************/
static void inagua_enable(device_t dev) static void inagua_enable(device_t dev)
{ {
printk(BIOS_INFO, "Mainboard Inagua Enable. dev=0x%p\n", dev); printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
#if (CONFIG_GFXUMA == 1) #if (CONFIG_GFXUMA == 1)
msr_t msr, msr2; msr_t msr, msr2;
uint32_t sys_mem; uint32_t sys_mem;
@ -78,11 +80,11 @@ static void inagua_enable(device_t dev)
else { else {
if (sys_mem >= 0x40000000) { if (sys_mem >= 0x40000000) {
uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */
} } else {
else {
uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */
} }
} }
uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base); __func__, uma_memory_size, uma_memory_base);
@ -109,6 +111,6 @@ int add_mainboard_resources(struct lb_memory *mem)
return 0; return 0;
} }
struct chip_operations mainboard_ops = { struct chip_operations mainboard_ops = {
CHIP_NAME("AMD INAGUA Mainboard") CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
.enable_dev = inagua_enable, .enable_dev = inagua_enable,
}; };

144
src/mainboard/amd/inagua/mptable.c
View File

@ -24,114 +24,55 @@
#include <arch/io.h> #include <arch/io.h>
#include <string.h> #include <string.h>
#include <stdint.h> #include <stdint.h>
#include <arch/cpu.h> #include <cpu/amd/amdfam14.h>
#include <cpu/x86/lapic.h>
#include <SBPLATFORM.h> #include <SBPLATFORM.h>
#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1
extern u8 bus_sb800[2]; extern u8 bus_sb800[2];
extern u32 apicid_sb800;
extern u32 bus_type[256]; extern u32 bus_type[256];
extern u32 sbdn_sb800; extern u32 sbdn_sb800;
u32 apicid_sb800;
u8 picr_data[] = {
0x0B,0x0A,0x0B,0x05,0x1F,0x1F,0x1F,0x1F,0x50,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
0x1F,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x0A,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x0B,0x0A,0x0B,0x05
};
u8 intr_data[] = { u8 intr_data[] = {
0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,
0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, [0x18] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
0x10,0x11,0x12,0x13 [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,
[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
[0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
[0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
[0x50] = 0x10,0x11,0x12,0x13
}; };
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
{
mc->mpc_length += length;
mc->mpc_entry_count++;
}
static void my_smp_write_bus(struct mp_config_table *mc,
unsigned char id, const char *bustype)
{
struct mpc_config_bus *mpc;
mpc = smp_next_mpc_entry(mc);
memset(mpc, '\0', sizeof(*mpc));
mpc->mpc_type = MP_BUS;
mpc->mpc_busid = id;
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
smp_add_mpc_entry(mc, sizeof(*mpc));
}
static void *smp_write_config_table(void *v) static void *smp_write_config_table(void *v)
{ {
struct mp_config_table *mc; struct mp_config_table *mc;
int bus_isa; int bus_isa;
int boot_apic_id;
unsigned apic_version;
unsigned cpu_features;
unsigned cpu_feature_flags;
struct cpuid_result result;
unsigned long cpu_flag;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR); mptable_init(mc, LAPIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8); memcpy(mc->mpc_oem, "AMD ", 8);
/*Inagua used dure core cpu with one die */ smp_write_processors(mc);
boot_apic_id = lapicid();
apic_version = lapic_read(LAPIC_LVR) & 0xff;
result = cpuid(1);
cpu_features = result.eax;
cpu_feature_flags = result.edx;
cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
smp_write_processor(mc,
0, apic_version,
cpu_flag, cpu_features, cpu_feature_flags
);
cpu_flag = MPC_CPU_ENABLED;
smp_write_processor(mc,
1, apic_version,
cpu_flag, cpu_features, cpu_feature_flags
);
get_bus_conf(); get_bus_conf();
//mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
device_t dev;
u32 dword; u32 dword;
u8 byte; u8 byte;
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0; dword &= 0xFFFFFFF0;
/* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24);
apicid_sb800 = IO_APIC_ID;
smp_write_ioapic(mc, apicid_sb800, 0x21, dword); smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
outb(picr_data[byte], 0xC01);
}
/* APIC IRQ routine */
for (byte = 0x0; byte < sizeof(intr_data); byte ++) { for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00); outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01); outb(intr_data[byte], 0xC01);
@ -141,55 +82,37 @@ static void *smp_write_config_table(void *v)
#define IO_LOCAL_INT(type, intr, apicid, pin) \ #define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
//mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
/*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sb800, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sb800, 0x1);
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x2, apicid_sb800, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_sb800, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_sb800, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, 0x49, apicid_sb800, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_sb800, 0x6);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_sb800, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_sb800, 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, apicid_sb800, 0x9);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0xa, apicid_sb800, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0x1c, apicid_sb800, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_sb800, 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_sb800, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_sb800, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_sb800, 0xf);
/* PCI interrupts are level triggered, and are /* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple. * associated with a specific bus/device/function tuple.
*/ */
#define PCI_INT(bus, dev, int_sign, pin) \ #if CONFIG_GENERATE_ACPI_TABLES == 0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin)) #define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* APU Internal Graphic Device*/ /* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
/* SMBUS */ //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10); PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
/* Southbridge HD Audio */ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
PCI_INT(0x0, 0x14, 0x2, intr_data[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
PCI_INT(0x0, 0x14, 0x5, intr_data[0x36]);
/* sata */ /* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* on board NIC & Slot PCIE. */ /* on board NIC & Slot PCIE. */
/* PCI slots */ /* PCI slots */
@ -215,21 +138,18 @@ static void *smp_write_config_table(void *v)
PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
/* PCIe Lan*/ /* PCIe PortA */
PCI_INT(0x0, 0x06, 0x0, 0x13);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10); PCI_INT(0x0, 0x15, 0x0, 0x10);
/* FCH PCIe PortB */ /* PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11); PCI_INT(0x0, 0x15, 0x1, 0x11);
/* FCH PCIe PortC */ /* PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12); PCI_INT(0x0, 0x15, 0x2, 0x12);
/* FCH PCIe PortD */ /* PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13); PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */ /* There is no extension information... */
/* Compute the checksums */ /* Compute the checksums */

2
src/mainboard/amd/inagua/platform_cfg.h
View File

@ -103,7 +103,7 @@
* @breif INCHIP Sata Controller Mode * @breif INCHIP Sata Controller Mode
* NOTE: DO NOT ALLOW SATA & IDE use same mode * NOTE: DO NOT ALLOW SATA & IDE use same mode
*/ */
#define SATA_MODE NATIVE_IDE_MODE #define SATA_MODE CONFIG_SB800_SATA_MODE
/** /**
* @breif INCHIP Sata IDE Controller Mode * @breif INCHIP Sata IDE Controller Mode

23
src/mainboard/amd/inagua/romstage.c
View File

@ -17,6 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <lib.h>
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <device/pci_def.h> #include <device/pci_def.h>
@ -25,9 +26,11 @@
#include <arch/stages.h> #include <arch/stages.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <arch/romcc_io.h> #include <arch/romcc_io.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <console/console.h> #include <console/console.h>
#include <console/loglevel.h> #include <console/loglevel.h>
#include "agesawrapper.h"
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "superio/smsc/kbc1100/kbc1100_early_init.c" #include "superio/smsc/kbc1100/kbc1100_early_init.c"
#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/lapic/boot_cpu.c"
@ -35,21 +38,21 @@
#include "pc80/i8259.c" #include "pc80/i8259.c"
#include "sb_cimx.h" #include "sb_cimx.h"
#include "SBPLATFORM.h" #include "SBPLATFORM.h"
#include <arch/cpu.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
u32 agesawrapper_amdinitmmio(void);
u32 agesawrapper_amdinitreset(void);
u32 agesawrapper_amdinitearly(void);
u32 agesawrapper_amdinitenv(void);
u32 agesawrapper_amdinitlate(void);
u32 agesawrapper_amdinitpost(void);
u32 agesawrapper_amdinitmid(void);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
u32 val; u32 val;
/* all cores: allow caching of flash chip code and data
* (there are no cache-as-ram reliability concerns with family 14h)
*/
__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
/* all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
*/
__writemsr (0xc0010062, 0);
if (!cpu_init_detectedx && boot_cpu()) { if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30); post_code(0x30);
sb_Poweron_Init(); sb_Poweron_Init();