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drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug

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Starting with Intel CPX there is a bug in the reference code during
the Pipe init. This code synchronises the CAR between sockets in FSP-M.
This code implicitly assumes that the FSP heap is right above the
RC heap, where both of them are located at the bottom part of CAR.

Work around this issue by making that implicit assumption done in FSP
explicit in the coreboot linker script and allocation.

TEST=intel/archercity CRB

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>

Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80579
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This commit is contained in:
Arthur Heymans
2024-02-18 11:45:30 +01:00
committed by Nico Huber
parent 67166a7eb2
commit 0201d989f2
5 changed files with 25 additions and 2 deletions
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6
src/arch/x86/car.ld
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@@ -9,6 +9,10 @@
.car.data . (NOLOAD) : {
_car_region_start = . ;
. += CONFIG_FSP_M_RC_HEAP_SIZE;
#if CONFIG(FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND)
REGION(fspm_heap, ., CONFIG_FSP_TEMP_RAM_SIZE, 16)
#endif
#if CONFIG(PAGING_IN_CACHE_AS_RAM)
/* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB
* aligned when using this option. */
@@ -107,7 +111,7 @@ _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start)
. = _car_region_start;
.car.fspm_rc_heap . (NOLOAD) : {
. += CONFIG_FSP_M_RC_HEAP_SIZE;
. += CONFIG_FSP_M_RC_HEAP_SIZE;
}
. = _car_region_end;