Add support for Intel Ibex Peak (Mobile 5) southbridge

Change-Id: If56f2cacc5f1b2ef9c7b6aea508d458a43dd1309
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3397
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/southbridge/intel/ibexpeak/Kconfig

@@ -0,0 +1,85 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config SOUTHBRIDGE_INTEL_IBEXPEAK
+	bool
+
+if SOUTHBRIDGE_INTEL_IBEXPEAK
+
+config SOUTH_BRIDGE_OPTIONS # dummy
+	def_bool y
+	select IOAPIC
+	select HAVE_HARD_RESET
+	select HAVE_USBDEBUG
+	select HAVE_SMI_HANDLER
+	select USE_WATCHDOG_ON_BOOT
+	select PCIEXP_ASPM
+	select PCIEXP_COMMON_CLOCK
+	select SPI_FLASH
+
+config EHCI_BAR
+	hex
+	default 0xfef00000
+
+config EHCI_DEBUG_OFFSET
+	hex
+	default 0xa0
+
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+	string
+	default "southbridge/intel/ibexpeak/bootblock.c"
+
+config SERIRQ_CONTINUOUS_MODE
+	bool
+	default n
+	help
+	  If you set this option to y, the serial IRQ machine will be
+	  operated in continuous mode.
+
+config HPET_MIN_TICKS
+	hex
+	default 0x80
+
+config HAVE_GBE_BIN
+	bool "Add gigabit ethernet firmware"
+	default n
+	help
+	  The integrated gigabit ethernet controller needs a firmware file.
+	  Select this if you are going to use the PCH integrated controller
+	  and have the firmware.
+
+config GBE_BIN_PATH
+	string "Path to gigabit ethernet firmware"
+	depends on HAVE_GBE_BIN
+	default "3rdparty/mainboard/$(MAINBOARDDIR)/gbe.bin"
+
+config LOCK_MANAGEMENT_ENGINE
+	bool "Lock Management Engine section"
+	default n
+	help
+	  The Intel Management Engine supports preventing write accesses
+	  from the host to the Management Engine section in the firmware
+	  descriptor. If the ME section is locked, it can only be overwritten
+	  with an external SPI flash programmer. You will want this if you
+	  want to increase security of your ROM image once you are sure
+	  that the ME firmware is no longer going to change.
+
+	  If unsure, say N.
+
+endif