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vendor: mediatek: Add mediatek mt8192 dram initialization code

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This is the DRAM initialization code from the reference
implementation released by Mediatek for MT8192.

The DRAM calibration code can be taken as a standalone
library, used by different boot loaders for initializing
DRAM and following a different coding style (coreboot was
using Linux Kernel coding style), so we have to put it
in vendor code folder.

Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Xi Chen
2021-02-05 11:45:12 +08:00
committed by Hung-Te Lin
parent 69da754112
commit 022b1b992f
53 changed files with 85570 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
MAINTAINERS
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@ -614,6 +614,12 @@ M: Hung-Te Lin <hungte@chromium.org>
S: Supported S: Supported
F: src/soc/mediatek/ F: src/soc/mediatek/
MEDIATEK MT8192
M: Xi Chen <xixi.chen@mediatek.com>
S: Maintained
F: src/soc/mediatek/mt8192/
F: src/vendorcode/mediatek/mt8192/
ORPHANED ARM SOCS ORPHANED ARM SOCS
S: Orphaned S: Orphaned
F: src/cpu/armltd/ F: src/cpu/armltd/

1
src/vendorcode/mediatek/Makefile.inc Normal file
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@ -0,0 +1 @@
subdirs-$(CONFIG_SOC_MEDIATEK_MT8192) += mt8192

5
src/vendorcode/mediatek/mt8192/Makefile.inc Normal file
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@ -0,0 +1,5 @@
subdirs-y += dramc
CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include
CPPFLAGS_common += -Isrc/soc/mediatek/common/include
CPPFLAGS_common += -Isrc/vendorcode/mediatek/mt8192/dramc/include -Isrc/vendorcode/mediatek/mt8192/include

1243
src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c Normal file
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File diff suppressed because it is too large Load Diff

983
src/vendorcode/mediatek/mt8192/dramc/DIG_NONSHUF_config.c Normal file
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@ -0,0 +1,983 @@
/* SPDX-License-Identifier: BSD-3-Clause */
#include "dramc_dv_init.h"
Gating_confg_T Gat_p;
//============================================
// digital PHY config
//============================================
static void DIG_PHY_config(DRAMC_CTX_T *p)
{
#if ENABLE_PINMUX_FOR_RANK_SWAP
U8 RK_SWAP_EN = 1;
#else
U8 RK_SWAP_EN = 0;
#endif
mcSHOW_DBG_MSG(("[Flow] Enable top DCM control >>>>> \n"));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2) , P_Fld( 3 , MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2) , P_Fld( 0 , MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG ) \
| P_Fld( 0x1f , MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2) , P_Fld( 1 , MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG ) \
| P_Fld( 0x1f , MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2) , P_Fld( 0 , MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG ) \
| P_Fld( 0x1f , MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2) , P_Fld( 0x17 , MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL ) \
| P_Fld( 1 , MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0) , P_Fld( 0 , MISC_CTRL0_R_STBENCMP_DIV4CK_EN ) \
| P_Fld( 1 , MISC_CTRL0_R_DQS0IEN_DIV4_CK_CG_CTRL ) \
| P_Fld( 1 , MISC_CTRL0_R_DQS1IEN_DIV4_CK_CG_CTRL ) \
| P_Fld( 0 , MISC_CTRL0_R_CLKIEN_DIV4_CK_CG_CTRL ) \
| P_Fld( 1 , MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RXDVS2) , P_Fld( 1 , MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG));
mcSHOW_DBG_MSG(("[Flow] Enable top DCM control <<<<< \n"));
mcSHOW_DBG_MSG(("Enable DLL master slave shuffle \n"));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFS_EMI_CLK) , P_Fld( 1 , MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 1 , B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld(RK_SWAP_EN, MISC_CTRL1_R_RK_PINMUXSWAP_EN ));
mcDELAY_US(1);
if(A_T->NEW_RANK_MODE==0)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 4 , B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0 ) \
| P_Fld( 0 , B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 4 , B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1 ) \
| P_Fld( 0 , B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ10) , P_Fld( 0 , B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ10) , P_Fld( 0 , B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1 ));
}
else
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 0 , B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0 ) \
| P_Fld( 1 , B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 0 , B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1 ) \
| P_Fld( 1 , B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ10) , P_Fld( 1 , B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ10) , P_Fld( 1 , B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1 ));
}
if(A_T->NEW_8X_MODE==1)
{
DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL) , P_Fld( 1 , MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE ) \
| P_Fld( 3 , MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN ));
DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
}
}
static void GATING_MODE_CFG(Gating_confg_T *tr)
{
tr->GAT_TRACK_EN = ((A_D->DQ_SEMI_OPEN == 1)||(A_D->DQ_CA_OPEN==1))?0:1;
tr->RX_GATING_MODE = 2; //fix 7UI mode under LPDDR4
tr->RX_GATING_TRACK_MODE = 2; //fix FIFO mode under LPDDR4
tr->PICG_EARLY_EN = 1; //fix under LPDDR4, if LPDDR5 have to set 1
tr->SELPH_MODE = 1; //random inside {0,1} //for improve APHY XRTR2R. NEW_APHY MODE with 1.
tr->VALID_LAT_VALUE = 1; //random inside {0,1}
mcSHOW_DBG_MSG(("============================================================== \n"));
mcSHOW_DBG_MSG(("Gating Mode config\n" ));
mcSHOW_DBG_MSG(("============================================================== \n"));
mcSHOW_DBG_MSG(("Config description: \n"));
mcSHOW_DBG_MSG(("RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode\n"));
mcSHOW_DBG_MSG(("RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode\n"));
mcSHOW_DBG_MSG(("SELPH_MODE 0: By rank 1: By Phase \n"));
mcSHOW_DBG_MSG(("============================================================== \n"));
mcSHOW_DBG_MSG(("GAT_TRACK_EN = %2d\n",tr->GAT_TRACK_EN ));
mcSHOW_DBG_MSG(("RX_GATING_MODE = %2d\n",tr->RX_GATING_MODE ));
mcSHOW_DBG_MSG(("RX_GATING_TRACK_MODE = %2d\n",tr->RX_GATING_TRACK_MODE));
mcSHOW_DBG_MSG(("SELPH_MODE = %2d\n",tr->SELPH_MODE ));
mcSHOW_DBG_MSG(("PICG_EARLY_EN = %2d\n",tr->PICG_EARLY_EN ));
mcSHOW_DBG_MSG(("VALID_LAT_VALUE = %2d\n",tr->VALID_LAT_VALUE ));
mcSHOW_DBG_MSG(("============================================================== \n"));
}
//======================================
//gating widnow mode
//======================================
static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
{
mcSHOW_DBG_MSG(("Enter into Gating configuration >>>> \n"));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld(!gat_c->GAT_TRACK_EN, MISC_STBCAL1_STBCNT_SW_RST ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2) , P_Fld(gat_c->SELPH_MODE, MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld( 1 , MISC_STBCAL1_STBCNT_SHU_RST_EN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld( 1 , MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD ));
if(gat_c->PICG_EARLY_EN == 1)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 1 , B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 1 , B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2) , P_Fld( 1 , MISC_STBCAL2_STB_PICG_EARLY_1T_EN ));
}
//================================
//gating Mode config
//================================
switch (gat_c->RX_GATING_MODE)
{
//Pulse Mode
case 0:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 0 , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 0 , B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 0 , B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 0 , B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL) , P_Fld( 0 , MISC_SHU_STBCAL_DQSIEN_BURST_MODE ));
break;
}
// Burst Mode (8UI)
case 1:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 1 , B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 1 , B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 1 , B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1));
break;
}
// Burst Mode (7UI)
case 2:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 1 , B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 2 , B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 2 , B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld( 1 , MISC_STBCAL1_DQSIEN_7UI_EN ));
break;
}
// Oringinal Burst
case 3:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1 , B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 1 , B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 0 , B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 0 , B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1));
break;
}
default:
{
mcSHOW_DBG_MSG(("ERROR: Gating Mode choose unexpected Mode!!!!\n"));
break;
}
}
//================================
//Gating tracking Mode config
//================================
switch (gat_c->RX_GATING_TRACK_MODE)
{
//Valid DLY Mode
case 0:
{
//TODO SHU1_DQSG if -like mode should set STB_UPDMASKCYC = 0 STB_UPDMASK_EN=0 others STB_UPDMASKCYC=9 STB_UPDMASK_EN=1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL) , P_Fld( 1 , MISC_STBCAL_STB_DQIEN_IG ) \
| P_Fld( 1 , MISC_STBCAL_PICHGBLOCK_NORD ) \
| P_Fld( 0 , MISC_STBCAL_REFUICHG ) \
| P_Fld( 0 , MISC_STBCAL_PHYVALID_IG ) \
| P_Fld( 0 , MISC_STBCAL_STBSTATE_OPT ) \
| P_Fld( 0 , MISC_STBCAL_STBDLELAST_FILTER ) \
| P_Fld( 0 , MISC_STBCAL_STBDLELAST_PULSE ) \
| P_Fld( 0 , MISC_STBCAL_STBDLELAST_OPT ) \
| P_Fld( 1 , MISC_STBCAL_PIMASK_RKCHG_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld( 1 , MISC_STBCAL1_STBCAL_FILTER ) \
| P_Fld( 1 , MISC_STBCAL1_STB_FLAGCLR_OPT ) \
| P_Fld( 1 , MISC_STBCAL1_STB_SHIFT_DTCOUT_IG ) \
| P_Fld( 1 , MISC_STBCAL1_STBCNT_MODESEL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0) , P_Fld( 0 , MISC_CTRL0_R_DMDQSIEN_FIFO_EN ) \
| P_Fld( 2 , MISC_CTRL0_R_DMVALID_DLY ) \
| P_Fld( 1 , MISC_CTRL0_R_DMVALID_DLY_OPT ) \
| P_Fld( 0 , MISC_CTRL0_R_DMSTBEN_SYNCOPT ) \
| P_Fld( 0 , MISC_CTRL0_R_DMVALID_NARROW_IG )); //TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 1 , B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 0 , B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0 ) \
| P_Fld( 0 , B0_DQ9_R_DMDQSIEN_VALID_LAT_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 1 , B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 0 , B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1 ) \
| P_Fld( 0 , B1_DQ9_R_DMDQSIEN_VALID_LAT_B1 ));
break;
}
//-like Mode
case 1:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL) , P_Fld( 0 , MISC_STBCAL_STB_DQIEN_IG ) \
| P_Fld( 0 , MISC_STBCAL_PICHGBLOCK_NORD ) \
| P_Fld( 1 , MISC_STBCAL_REFUICHG ) \
| P_Fld( 0 , MISC_STBCAL_PHYVALID_IG ) \
| P_Fld( 1 , MISC_STBCAL_STBSTATE_OPT ) \
| P_Fld( 0 , MISC_STBCAL_STBDLELAST_FILTER ) \
| P_Fld( 0 , MISC_STBCAL_STBDLELAST_PULSE ) \
| P_Fld( 0 , MISC_STBCAL_STBDLELAST_OPT ) \
| P_Fld( 0 , MISC_STBCAL_PIMASK_RKCHG_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld( 0 , MISC_STBCAL1_STBCAL_FILTER ) \
| P_Fld( 1 , MISC_STBCAL1_STB_FLAGCLR_OPT ) \
| P_Fld( 0 , MISC_STBCAL1_STB_SHIFT_DTCOUT_IG ) \
| P_Fld( 1 , MISC_STBCAL1_STBCNT_MODESEL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0) , P_Fld( 0 , MISC_CTRL0_R_DMDQSIEN_FIFO_EN ) \
| P_Fld( 0 , MISC_CTRL0_R_DMVALID_DLY ) \
| P_Fld( 0 , MISC_CTRL0_R_DMVALID_DLY_OPT ) \
| P_Fld( 0 , MISC_CTRL0_R_DMSTBEN_SYNCOPT ) \
| P_Fld( 1 , MISC_CTRL0_R_DMVALID_NARROW_IG ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 1 , B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 0 , B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0 ) \
| P_Fld( 0 , B0_DQ9_R_DMDQSIEN_VALID_LAT_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 1 , B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 0 , B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1 ) \
| P_Fld( 0 , B1_DQ9_R_DMDQSIEN_VALID_LAT_B1 ));
break;
}
//FIFO Mode
case 2:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL) , P_Fld( 1 , MISC_STBCAL_STB_DQIEN_IG ) \
| P_Fld( 1 , MISC_STBCAL_PICHGBLOCK_NORD ) \
| P_Fld( 0 , MISC_STBCAL_REFUICHG ) \
| P_Fld( 0 , MISC_STBCAL_PHYVALID_IG ) \
| P_Fld( 0 , MISC_STBCAL_STBSTATE_OPT ) \
| P_Fld( 0 , MISC_STBCAL_STBDLELAST_FILTER ) \
| P_Fld( 0 , MISC_STBCAL_STBDLELAST_PULSE ) \
| P_Fld( 0 , MISC_STBCAL_STBDLELAST_OPT ) \
| P_Fld( 1 , MISC_STBCAL_PIMASK_RKCHG_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1) , P_Fld( 1 , MISC_STBCAL1_STBCAL_FILTER ) \
| P_Fld( 1 , MISC_STBCAL1_STB_FLAGCLR_OPT ) \
| P_Fld( 1 , MISC_STBCAL1_STB_SHIFT_DTCOUT_IG ) \
| P_Fld( 1 , MISC_STBCAL1_STBCNT_MODESEL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL0) , P_Fld( 1 , MISC_CTRL0_R_DMDQSIEN_FIFO_EN ) \
| P_Fld( 0 , MISC_CTRL0_R_DMVALID_DLY ) \
| P_Fld( 0 , MISC_CTRL0_R_DMVALID_DLY_OPT ) \
| P_Fld( 0 , MISC_CTRL0_R_DMSTBEN_SYNCOPT ) \
| P_Fld( 0 , MISC_CTRL0_R_DMVALID_NARROW_IG )); // @Darren, func no use sync MP settings from HJ
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ6) , P_Fld( 0 , B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9) , P_Fld( 1+gat_c->VALID_LAT_VALUE , B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0 ) \
| P_Fld( 0+gat_c->VALID_LAT_VALUE , B0_DQ9_R_DMDQSIEN_VALID_LAT_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6) , P_Fld( 0 , B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9) , P_Fld( 1+gat_c->VALID_LAT_VALUE , B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1 ) \
| P_Fld( 0+gat_c->VALID_LAT_VALUE , B1_DQ9_R_DMDQSIEN_VALID_LAT_B1 ));
break;
}
default:
{
mcSHOW_DBG_MSG(("ERROR: Gating tracking Mode choose unexpected Mode!!!!"));
break;
}
}
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_PHY2) , P_Fld( 1 , B0_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_PHY2) , P_Fld( 1 , B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL) , P_Fld( 1 , MISC_STBCAL_DQSIENMODE ) \
| P_Fld( 1 , MISC_STBCAL_SREF_DQSGUPD ) \
| P_Fld( 1 , MISC_STBCAL_DQSIENCG_CHG_EN ) \
| P_Fld( 1 , MISC_STBCAL_PICGEN ) \
| P_Fld( 0 , MISC_STBCAL_RKCHGMASKDIS ) \
| P_Fld( 0 , MISC_STBCAL_STBCAL2R ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld( 1 , MISC_CTRL1_R_DMDQSIENCG_EN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2) , P_Fld( 0 , MISC_STBCAL2_STB_GERRSTOP ) \
| P_Fld( 0 , MISC_STBCAL2_STB_GERR_RST ) \
| P_Fld( 1 , MISC_STBCAL2_STB_GERR_B01 ) \
| P_Fld( 0 , MISC_STBCAL2_STB_GERR_B23 ));
//PICG_MODE only support new mode so here fix 1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), P_Fld(1, MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), P_Fld(1, MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT ));
if(A_T->NEW_RANK_MODE == 1)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2) , P_Fld( 1 , MISC_STBCAL2_STB_IG_XRANK_CG_RST ) \
| P_Fld( 1 , MISC_STBCAL2_STB_RST_BY_RANK ) \
| P_Fld( 1 , MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN ));
}
mcSHOW_DBG_MSG(("Exit from Gating configuration <<<< \n"));
}
static void RX_INTPUT_Config(DRAMC_CTX_T *p)
{
U8 VALID_LAT = 1;// TODO inside {0,1}
U8 RDSEL_LAT = 2;// TODO alywas VALID_LAT+1;
U8 dq_min = 0;
U8 dq_max = 0xff;
U8 scale = 3;
U8 threadhold = 0;
U32 dqs_min = 0;
U32 dqs_max = 0x1ff;
U8 RX_force_upd = 0; //TODO
U8 F_LEADLAG = 0; //TODO
U8 RG_MODE_EN = 0; //TODO
U8 irank = 0;
U8 backup_rank = 0;
backup_rank = p->rank;
mcSHOW_DBG_MSG(("[RX_INPUT] configuration >>>>> \n"));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS0) , P_Fld( 1 , B0_RXDVS0_R_HWSAVE_MODE_ENA_B0 ) \
| P_Fld( 0 , B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0 ) \
| P_Fld( 1 , B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0 ) \
| P_Fld( 1 , B0_RXDVS0_R_HWRESTORE_ENA_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_RXDVS0) , P_Fld( 1 , B1_RXDVS0_R_HWSAVE_MODE_ENA_B1 ) \
| P_Fld( 0 , B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1 ) \
| P_Fld( 1 , B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1 ) \
| P_Fld( 1 , B1_RXDVS0_R_HWRESTORE_ENA_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ9 ) , P_Fld( VALID_LAT , B0_DQ9_R_DMRXDVS_VALID_LAT_B0 ) \
| P_Fld( RDSEL_LAT , B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ9 ) , P_Fld( VALID_LAT , B1_DQ9_R_DMRXDVS_VALID_LAT_B1 ) \
| P_Fld( RDSEL_LAT , B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RXDVS2 ) , P_Fld( 1 , MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN ) \
| P_Fld( 0 , MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR ) \
| P_Fld( 0 , MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN ) \
| P_Fld( 1 , MISC_RXDVS2_R_DMRXDVS_DEPTH_HALF ));
for(irank = RANK_0; irank < p->support_rank_num; irank++)
{
vSetRank(p, irank);
//RK0--B0
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS3 ) , P_Fld( dq_min , RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0 ) \
| P_Fld( dq_max , RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS4 ) , P_Fld( dqs_min , RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0 ) \
| P_Fld( dqs_max , RK_B0_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS2 ) , P_Fld( scale , RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0 ) \
| P_Fld( scale , RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0 ) \
| P_Fld( 0 , RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0 ) \
| P_Fld( scale , RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0 ) \
| P_Fld( scale , RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0 ) \
| P_Fld( 0 , RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0 ) \
| P_Fld( 1 , RK_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0 ) \
| P_Fld( 0 , RK_B0_RXDVS2_R_RK0_DVS_MODE_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS1 ) , P_Fld( threadhold , RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG ) \
| P_Fld( threadhold , RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD ));
//RK0--B1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS3 ) , P_Fld( dq_min , RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1 ) \
| P_Fld( dq_max , RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS4 ) , P_Fld( dqs_min , RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1 ) \
| P_Fld( dqs_max , RK_B1_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS2 ) , P_Fld( scale , RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1 ) \
| P_Fld( scale , RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1 ) \
| P_Fld( 0 , RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1 ) \
| P_Fld( scale , RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1 ) \
| P_Fld( scale , RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1 ) \
| P_Fld( 0 , RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1 ) \
| P_Fld( 1 , RK_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1 ) \
| P_Fld( 0 , RK_B1_RXDVS2_R_RK0_DVS_MODE_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS1 ) , P_Fld( threadhold , RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG ) \
| P_Fld( threadhold , RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD ));
}
vSetRank(p, backup_rank);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL1 ) , 0xffffffff , MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL ); //TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS1 ) , P_Fld( F_LEADLAG , B0_RXDVS1_F_LEADLAG_TRACK_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_RXDVS1 ) , P_Fld( F_LEADLAG , B1_RXDVS1_F_LEADLAG_TRACK_B1 ));
if(RX_force_upd == 1)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL ) , P_Fld( 1 , DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT ) \
| P_Fld( 1 , DLLFRZ_CTRL_DLLFRZ_BLOCKLONG ) \
| P_Fld( 1 , DLLFRZ_CTRL_INPUTRXTRACK_BLOCK ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS1 ) , P_Fld( 1 , B0_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_RXDVS1 ) , P_Fld( 1 , B1_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B1 ));
}
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ5 ) , P_Fld( 1 , B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ5 ) , P_Fld( 1 , B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS0 ) , P_Fld( 1 , B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0 )\
| P_Fld( 1 , B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0 )\
| P_Fld( 1 , B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0 )\
| P_Fld( 0 , B0_RXDVS0_R_RX_RANKINCTL_B0 )\
| P_Fld( 1 , B0_RXDVS0_R_RX_RANKINSEL_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_RXDVS0 ) , P_Fld( 1 , B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1 )\
| P_Fld( 1 , B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1 )\
| P_Fld( 1 , B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1 )\
| P_Fld( 0 , B1_RXDVS0_R_RX_RANKINCTL_B1 )\
| P_Fld( 1 , B1_RXDVS0_R_RX_RANKINSEL_B1 ));
for(irank = RANK_0; irank < RANK_MAX; irank++)
{
vSetRank(p, irank);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B0_RXDVS2 ) , P_Fld( 1 , RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0 ) \
| P_Fld( 1 , RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0 ) \
| P_Fld( 2 , RK_B0_RXDVS2_R_RK0_DVS_MODE_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_RK_B1_RXDVS2 ) , P_Fld( 1 , RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1 ) \
| P_Fld( 1 , RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1 ) \
| P_Fld( 2 , RK_B1_RXDVS2_R_RK0_DVS_MODE_B1 ));
}
vSetRank(p, backup_rank);
//Enable RX input delay tracking..
//TODO notice here if SA should not enbale it before RX perbit calibration
if (RG_MODE_EN == 1)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RG_DFS_CTRL) , P_Fld( 1 , MISC_RG_DFS_CTRL_RG_DPY_RXDLY_TRACK_EN ));
} else {
// `TBA_TOP.dvfs_spm_vif.sc_dphy_reserved[1:0] = 2'b11; //TODO
}
mcSHOW_DBG_MSG(("[RX_INPUT] configuration <<<<< \n"));
}
static void DDRPHY_PICG_Config(DRAMC_CTX_T *p)
{
U8 PICG_MODE = 1; // only support new Mode under
U8 MISC_CG_EN = 1;
U8 MISC_CG_REVERSE_DEFAULT_ON = 0; //for default CG enable.
mcSHOW_DBG_MSG(("Enter into PICG configuration >>>> \n"));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4) , P_Fld( PICG_MODE , MISC_CTRL4_R_OPT2_MPDIV_CG ) \
| P_Fld( PICG_MODE , MISC_CTRL4_R_OPT2_CG_MCK ) \
| P_Fld( PICG_MODE , MISC_CTRL4_R_OPT2_CG_DQM ) \
| P_Fld( PICG_MODE , MISC_CTRL4_R_OPT2_CG_DQS ) \
| P_Fld( PICG_MODE , MISC_CTRL4_R_OPT2_CG_DQ ) \
| P_Fld( PICG_MODE , MISC_CTRL4_R_OPT2_CG_DQSIEN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL3) , P_Fld( !PICG_MODE , MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT ) \
| P_Fld( !PICG_MODE , MISC_CTRL3_ARPI_CG_MCK_DQ_OPT ) \
| P_Fld( !PICG_MODE , MISC_CTRL3_ARPI_CG_DQS_OPT ) \
| P_Fld( !PICG_MODE , MISC_CTRL3_ARPI_CG_DQ_OPT ));
//Notice here: MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE = 1 will leading other_shuffle_group before register settle down latch ->error. can not set to 1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL0) , P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE ) \
| P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE ) \
| P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE ) \
| P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE ) \
| P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE ) \
| P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE ) \
| P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE ) \
| P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE ) \
| P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE ) \
| P_Fld( !MISC_CG_EN , MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2) , P_Fld( !MISC_CG_EN , MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE ) \
| P_Fld( !MISC_CG_EN , MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE ) \
| P_Fld( !MISC_CG_EN , MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL5) , P_Fld( MISC_CG_EN , MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN ) \
| P_Fld( MISC_CG_EN , MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN ) \
| P_Fld( MISC_CG_EN , MISC_CG_CTRL5_R_CA_DLY_DCM_EN ) \
| P_Fld( MISC_CG_EN , MISC_CG_CTRL5_R_DQ1_PI_DCM_EN ) \
| P_Fld( MISC_CG_EN , MISC_CG_CTRL5_R_DQ0_PI_DCM_EN ) \
| P_Fld( MISC_CG_EN , MISC_CG_CTRL5_R_CA_PI_DCM_EN ));
//defualt DCM enable, if we wanner to test CG enable, modified default CG condition.
//disable DCM.--- I think just for debug
if(MISC_CG_REVERSE_DEFAULT_ON == 1)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RX_CG_SET0) , P_Fld( 1 , RX_CG_SET0_RDATCKAR ) \
| P_Fld( 1 , RX_CG_SET0_RDYCKAR ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SREF_DPD_CTRL) , P_Fld( 1 , SREF_DPD_CTRL_CMDCKAR ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DCM_CTRL0) , P_Fld( 1 , DCM_CTRL0_BCLKAR ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_CG_SET0) , P_Fld( 1 , TX_CG_SET0_PSELAR ) \
| P_Fld( 1 , TX_CG_SET0_DWCLKRUN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SCSMCTRL_CG) , P_Fld( 1 , SCSMCTRL_CG_SCSM_CGAR ) \
| P_Fld( 1 , SCSMCTRL_CG_SCARB_SM_CGAR ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_TRACKING_SET0) , P_Fld( 1 , TX_TRACKING_SET0_RDDQSOSC_CGAR ) \
| P_Fld( 1 , TX_TRACKING_SET0_HMRRSEL_CGAR ) \
| P_Fld( 1 , TX_TRACKING_SET0_TXUIPI_CAL_CGAR ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ZQ_SET0) , P_Fld( 1 , ZQ_SET0_ZQCS_MASK_SEL_CGAR ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ACTIMING_CTRL) , P_Fld( 1 , ACTIMING_CTRL_CLKWITRFC ) \
| P_Fld( 1 , ACTIMING_CTRL_SEQCLKRUN3 ) \
| P_Fld( 1 , ACTIMING_CTRL_SEQCLKRUN2 ) \
| P_Fld( 1 , ACTIMING_CTRL_SEQCLKRUN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CLKAR) , P_Fld( 1 , CLKAR_REQQUECLKRUN ) \
| P_Fld( 1 , CLKAR_REQQUE_PACG_DIS ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL) , P_Fld( 1 , DRAMC_PD_CTRL_PHYGLUECLKRUN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3) , P_Fld( 1 , TEST2_A3_TESTCLKRUN ));
DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0) , P_Fld( 1 , DVFS_CTRL0_DVFS_CG_OPT ));
DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTYSCAN1) , P_Fld( 1 , MISC_DUTYSCAN1_EYESCAN_DQS_OPT ));
//TODO -- for DPHY shuffle RG have to set to different Group into SRAM or not.--here just conf0 but not all frequency group
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ8) , P_Fld( 1 , SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0 ) \
| P_Fld( 1 , SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0 ) \
| P_Fld( 1 , SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0 ) \
| P_Fld( 1 , SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 ) \
| P_Fld( 1 , SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 ) \
| P_Fld( 1 , SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0 ) \
| P_Fld( 1 , SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 ) \
| P_Fld( 1 , SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 ) \
| P_Fld( 1 , SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 ) \
| P_Fld( 1 , SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0) \
| P_Fld( 1 , SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0 ) \
| P_Fld( 1 , SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ8) , P_Fld( 1 , SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1 ) \
| P_Fld( 1 , SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1 ) \
| P_Fld( 1 , SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1 ) \
| P_Fld( 1 , SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 ) \
| P_Fld( 1 , SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 ) \
| P_Fld( 1 , SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1 ) \
| P_Fld( 1 , SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 ) \
| P_Fld( 1 , SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 ) \
| P_Fld( 1 , SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 ) \
| P_Fld( 1 , SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1) \
| P_Fld( 1 , SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1 ) \
| P_Fld( 1 , SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1 ));
}
mcSHOW_DBG_MSG(("Exit from PICG configuration <<<< \n"));
}
static void DRAMC_COMMON_Config(DRAMC_CTX_T *p)
{
U8 RD2MRR_EXTEND_EN = 1; // for fix Samsung RD2MRR seamless error, If the samsung fix that bug, this could set 0
U8 EBG_EN ;
U8 TMRRI_MODE = 1; // !!!Notice here: 0: Old Mode, 1: New Mode --- FIX NEW MODE. Pertrus not support old mode anymore
U8 NOBLOCKALE_EN = 1;
U8 RUNTIME_MRR = 1;
#if (fcFOR_CHIP_ID == fcMargaux)
U8 dram_mux = p->DRAMPinmux; // 0: DSC, 1: LPBK, 2: MCP
#endif
//pre configuration calculate
if(TMRRI_MODE == 1)
{
NOBLOCKALE_EN = 1;
RUNTIME_MRR = 1;
} else {
//TODO
mcSHOW_DBG_MSG(("NONBLOCKALE RUNTIMEMRR could be random.--for MP should setting 1. just record it."));
}
#if ENABLE_EARLY_BG_CMD==1
if((LPDDR5_EN_S == 1) && (DFS(0)->data_rate < 3200)) EBG_EN = 0; else EBG_EN = 1;
#else
EBG_EN = 0;
#endif
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DDRCOMMON0) , P_Fld( 1 , DDRCOMMON0_BK8EN ) \
| P_Fld( LPDDR5_EN_S , DDRCOMMON0_LPDDR5EN ) \
| P_Fld( LPDDR4_EN_S , DDRCOMMON0_LPDDR4EN ) \
| P_Fld( 0 , DDRCOMMON0_TRCDEARLY )); //if LPDDR5 set1 HEFF mode ACT -> R/W delay-1
#if (fcFOR_CHIP_ID == fcMargaux)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld( dram_mux , MISC_CTRL1_R_DMPINMUX ));
#else
if(LPDDR5_EN_S == 1)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld( 2 , MISC_CTRL1_R_DMPINMUX ));
}
#endif
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0) , P_Fld( 0 , RX_SET0_DM4TO1MODE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0) , P_Fld( 5 , REFCTRL0_REF_PREGATE_CNT ) \
| P_Fld( 0 , REFCTRL0_DMPGVLD_IG ) \
| P_Fld( 4 , REFCTRL0_DISBYREFNUM ) \
| P_Fld( 0 , REFCTRL0_PBREF_DISBYRATE ) \
| P_Fld( 1 , REFCTRL0_PBREF_DISBYREFNUM ) \
| P_Fld( 1 , REFCTRL0_PBREF_BK_REFA_ENA ) \
| P_Fld( 1 , REFCTRL0_PBREF_BK_REFA_NUM ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL1) , P_Fld( 1 , REFCTRL1_PB2AB_OPT ) \
| P_Fld( 1 , REFCTRL1_REF_QUE_AUTOSAVE_EN ) \
| P_Fld( 0 , REFCTRL1_REF_OVERHEAD_ALL_REFPB_ENA ) \
| P_Fld( 1 , REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA ) \
| P_Fld( 0 , REFCTRL1_REF_OVERHEAD_ALL_REFAL_ENA ) \
| P_Fld( 0 , REFCTRL1_REF_OVERHEAD_SLOW_REFAL_ENA ) \
| P_Fld( 0 , REFCTRL1_REF_OVERHEAD_RATE_REFPB_ENA ) \
| P_Fld( 0 , REFCTRL1_REF_OVERHEAD_RATE_REFAL_ENA ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL2) , P_Fld( 0 , REFCTRL2_REF_OVERHEAD_RATE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL) , P_Fld( 0 , DLLFRZ_CTRL_UPDBYWR ) \
| P_Fld( 1 , DLLFRZ_CTRL_DLLFRZ ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAMCTRL) , P_Fld( 0 , DRAMCTRL_ADRDECEN ) \
| P_Fld( 1 , DRAMCTRL_PREALL_OPTION ) \
| P_Fld( 1 , DRAMCTRL_REQQUE_THD_EN ) \
| P_Fld( 1 , DRAMCTRL_DYNMWREN ) \
| P_Fld( 0 , DRAMCTRL_AG0MWR ) \
| P_Fld( 0 , DRAMCTRL_ADRBIT3DEC ) \
| P_Fld( 0 , DRAMCTRL_CTOREQ_HPRI_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ACTIMING_CTRL) , P_Fld( 0 , ACTIMING_CTRL_CLKWITRFC ) \
| P_Fld( 1 , ACTIMING_CTRL_SEQCLKRUN3 ) \
| P_Fld( 0 , ACTIMING_CTRL_FASTW2R ) \
| P_Fld( 0 , ACTIMING_CTRL_REFBW_FREN ) \
| P_Fld( 1 , ACTIMING_CTRL_TMRRICHKDIS ) \
| P_Fld( 0 , ACTIMING_CTRL_REFNA_OPT ) \
| P_Fld(!TMRRI_MODE , ACTIMING_CTRL_MRRIOPT ) \
| P_Fld(!TMRRI_MODE , ACTIMING_CTRL_TMRRIBYRK_DIS ) \
| P_Fld( TMRRI_MODE , ACTIMING_CTRL_TMRRICHKDIS ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ARBCTL) , P_Fld( 0x80 , ARBCTL_MAXPENDCNT ) \
| P_Fld( 0 , ARBCTL_WDATACNTDIS ) );
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAM_CLK_CTRL) , P_Fld( 1 , DRAM_CLK_CTRL_CLK_EN ) );
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CLKAR) , P_Fld( 1 , CLKAR_DCMREF_OPT ) );
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL) , P_Fld( 1 , DRAMC_PD_CTRL_COMBCLKCTRL ) \
| P_Fld( 0 , DRAMC_PD_CTRL_MIOCKCTRLOFF ) \
| P_Fld( 1 , DRAMC_PD_CTRL_PHYCLKDYNGEN ) \
| P_Fld( 1 , DRAMC_PD_CTRL_DCMEN ) \
| P_Fld( 1 , DRAMC_PD_CTRL_DCMEN2 ) \
// | P_Fld( 0x3 , DRAMC_PD_CTRL_APHYPI_CKCGH_CNT )
| P_Fld( 0 , DRAMC_PD_CTRL_PG_DCM_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RKCFG) , P_Fld( 0 , RKCFG_CKE2RANK ) \
| P_Fld( 0 , RKCFG_MRS2RK ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL) , P_Fld( 1 , CKECTRL_CKE2RANK_OPT2 ) \
| P_Fld( 1 , CKECTRL_CKEON ) \
| P_Fld( 0 , CKECTRL_CKETIMER_SEL ) \
| P_Fld( 1 , CKECTRL_CKE2RANK_OPT8 ) \
| P_Fld(!RUNTIME_MRR , CKECTRL_RUNTIMEMRRMIODIS ) \
| P_Fld( 1 , CKECTRL_FASTWAKE_SEL ) \
| P_Fld( 1 , CKECTRL_CKEPBDIS ) \
| P_Fld( !TMRRI_MODE , CKECTRL_RUNTIMEMRRCKEFIX ) \
| P_Fld( 0 , CKECTRL_CKELCKFIX ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SREF_DPD_CTRL) , P_Fld( 1 , SREF_DPD_CTRL_SELFREF_AUTOSAVE_EN) \
| P_Fld( 0 , SREF_DPD_CTRL_GT_SYNC_MASK ) \
| P_Fld( 0 , SREF_DPD_CTRL_DAT_SYNC_MASK ) \
| P_Fld( 0 , SREF_DPD_CTRL_PHY_SYNC_MASK ) \
| P_Fld( 1 , SREF_DPD_CTRL_LPSM_BYPASS_B ) \
| P_Fld( 0 , SREF_DPD_CTRL_SREF_PRD_OPT ) \
| P_Fld( 1 , SREF_DPD_CTRL_CLR_EN ) \
| P_Fld( 0 , SREF_DPD_CTRL_SRFPD_DIS ) \
| P_Fld( 8 , SREF_DPD_CTRL_SREFDLY ) \
| P_Fld( 1 , SREF_DPD_CTRL_SREF_HW_EN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SCHEDULER_COM) , P_Fld( 1 , SCHEDULER_COM_DISRDPHASE1 ) \
| P_Fld( 1 , SCHEDULER_COM_MWHPRIEN ) \
| P_Fld( 0 , SCHEDULER_COM_RWHPRICTL ) \
| P_Fld( 1 , SCHEDULER_COM_RWOFOEN ) \
| P_Fld( 1 , SCHEDULER_COM_RWSPLIT ));
// | P_Fld( 1 , SCHEDULER_COM_BGPIPEEN )); //diff with IPMV2 compile error
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_PERFCTL0) , P_Fld( 1 , PERFCTL0_EMILLATEN ) \
| P_Fld( 1 , PERFCTL0_RWHPRIEN ) \
| P_Fld( EBG_EN , PERFCTL0_EBG_EN ) \
| P_Fld( 1 , PERFCTL0_RWLLATEN ) \
| P_Fld( 1 , PERFCTL0_RWAGEEN ) \
| P_Fld( 1 , PERFCTL0_WFLUSHEN ) \
| P_Fld( 0 , PERFCTL0_REORDEREN ) \
| P_Fld( 0 , PERFCTL0_REORDER_MODE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_HW_MRR_FUN) , P_Fld(RUNTIME_MRR , HW_MRR_FUN_TMRR_ENA ) \
| P_Fld( 0 , HW_MRR_FUN_TRPMRR_EN ) \
| P_Fld( 0 , HW_MRR_FUN_TRCDMRR_EN ) \
| P_Fld( 1 , HW_MRR_FUN_MRR_HW_HIPRI ) \
| P_Fld(RD2MRR_EXTEND_EN , HW_MRR_FUN_TR2MRR_ENA ) \
| P_Fld(RD2MRR_EXTEND_EN , HW_MRR_FUN_R2MRRHPRICTL ) \
| P_Fld(RD2MRR_EXTEND_EN , HW_MRR_FUN_MANTMRR_EN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_ZQ_SET0) , P_Fld( 0x0A , ZQ_SET0_ZQCSAD ) \
| P_Fld( 0x56 , ZQ_SET0_ZQCSOP ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION) , P_Fld( 1 , MPC_OPTION_MPCRKEN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL) , P_Fld(!RUNTIME_MRR , MPC_CTRL_REFR_BLOCKEN ) \
| P_Fld( NOBLOCKALE_EN , MPC_CTRL_ZQ_BLOCKALE_OPT ) \
| P_Fld( NOBLOCKALE_EN , MPC_CTRL_MPC_BLOCKALE_OPT ) \
| P_Fld( NOBLOCKALE_EN , MPC_CTRL_MPC_BLOCKALE_OPT1 ) \
| P_Fld( NOBLOCKALE_EN , MPC_CTRL_MPC_BLOCKALE_OPT2 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_HMR4) , P_Fld( 1 , HMR4_SPDR_MR4_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1) , P_Fld( 0x010000 , RK_TEST2_A1_TEST2_BASE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A2) , P_Fld( 0x000020 , TEST2_A2_TEST2_OFF ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A3) , P_Fld( 1 , TEST2_A3_TESTAUDPAT ) \
| P_Fld( 1 , TEST2_A3_TEST2WREN2_HW_EN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A4) , P_Fld( 0x11 , TEST2_A4_TESTAUDINIT ) \
| P_Fld( 0x0d , TEST2_A4_TESTAUDINC ) \
| P_Fld( 0x04 , TEST2_A4_TESTAGENTRKSEL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CMD_DEC_CTRL0) , P_Fld( 1 , CMD_DEC_CTRL0_RKMODE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_MISCTL0) , P_Fld( 0 , MISCTL0_PAGDIS ) \
| P_Fld( 0 , MISCTL0_PBC_ARB_E1T ) \
| P_Fld( 1 , MISCTL0_REFA_ARB_EN2 ) \
| P_Fld( 1 , MISCTL0_PBC_ARB_EN ) \
| P_Fld( 1 , MISCTL0_REFP_ARB_EN2 ) \
| P_Fld( 0 , MISCTL0_EMIPREEN ) \
| P_Fld( 1 , MISCTL0_PG_WAKEUP_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SCSMCTRL) , P_Fld( 1 , SCSMCTRL_SC_PG_MAN_DIS ) \
| P_Fld( TMRRI_MODE , SCSMCTRL_SC_PG_UPD_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHUCTRL1) , P_Fld( 0x1a , SHUCTRL1_FC_PRDCNT )); //TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DVFS_TIMING_CTRL1) , P_Fld( 1 , DVFS_TIMING_CTRL1_DMSHU_CNT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFPEND1) , P_Fld( 0x5 , REFPEND1_MPENDREFCNT_TH0 ) \
| P_Fld( 0x5 , REFPEND1_MPENDREFCNT_TH1 ) \
| P_Fld( 0x5 , REFPEND1_MPENDREFCNT_TH2 ) \
| P_Fld( 0x5 , REFPEND1_MPENDREFCNT_TH3 ) \
| P_Fld( 0x5 , REFPEND1_MPENDREFCNT_TH4 ) \
| P_Fld( 0x3 , REFPEND1_MPENDREFCNT_TH5 ) \
| P_Fld( 0x3 , REFPEND1_MPENDREFCNT_TH6 ) \
| P_Fld( 0x3 , REFPEND1_MPENDREFCNT_TH7 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CBT_WLEV_CTRL1) , P_Fld( 0x10 , CBT_WLEV_CTRL1_CATRAIN_INTV ) \
| P_Fld( 0x3 , CBT_WLEV_CTRL1_CATRAINLAT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0) , P_Fld( 1 , TX_SET0_DRSCLR_EN ) \
| P_Fld( !TMRRI_MODE , TX_SET0_RK_SCINPUT_OPT ));
if(A_T->LP45_APHY_COMB_EN == 1)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0) , P_Fld( 1 , TX_SET0_OE_DOWNGRADE ));
}
//@Jouling, UI reloade path is updated. (DQSOSCR_SREF_TXUI_RELOAD_OPT)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR) , P_Fld( 0 , DQSOSCR_SREF_TXUI_RELOAD_OPT ) \
| P_Fld( 1 , DQSOSCR_SREF_TXPI_RELOAD_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD) , P_Fld( 1 , DUMMY_RD_DRS_SELFWAKE_DMYRD_DIS ) \
| P_Fld( 2 , DUMMY_RD_RANK_NUM ) \
| P_Fld( 1 , DUMMY_RD_DUMMY_RD_SW ) \
| P_Fld( 1 , DUMMY_RD_DQSG_DMYRD_EN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DUMMY_RD_INTV) , P_Fld( 0 , DUMMY_RD_INTV_DUMMY_RD_CNT7 ) \
| P_Fld( 1 , DUMMY_RD_INTV_DUMMY_RD_CNT6 ) \
| P_Fld( 1 , DUMMY_RD_INTV_DUMMY_RD_CNT5 ) \
| P_Fld( 0 , DUMMY_RD_INTV_DUMMY_RD_CNT4 ) \
| P_Fld( 1 , DUMMY_RD_INTV_DUMMY_RD_CNT3 ) \
| P_Fld( 0 , DUMMY_RD_INTV_DUMMY_RD_CNT2 ) \
| P_Fld( 0 , DUMMY_RD_INTV_DUMMY_RD_CNT1 ) \
| P_Fld( 0 , DUMMY_RD_INTV_DUMMY_RD_CNT0 ));
//Byte Mode choose
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC) , P_Fld( p->dram_cbt_mode[RANK_0] , RK_DQSOSC_RK0_BYTE_MODE ));
vSetRank(p, RANK_1);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC) , P_Fld( p->dram_cbt_mode[RANK_1] , RK_DQSOSC_RK0_BYTE_MODE ));
vSetRank(p, RANK_0);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_TRACKING_SET0) , P_Fld( 0 , TX_TRACKING_SET0_TX_TRACKING_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_CG_SET0) , P_Fld( 1 , TX_CG_SET0_SELPH_4LCG_DIS ));
//DVFS support SRAM_EN only
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0), P_Fld(DV_p.SRAM_EN, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL1) , P_Fld( 1 , SWCMD_CTRL1_WRFIFO_MODE2 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DBG_CMDDEC_CMDSEL0) , P_Fld( M_LP4->EX_ROW_EN[0], DBG_CMDDEC_CMDSEL0_RANK0_10GBEN ) \
| P_Fld( M_LP4->EX_ROW_EN[1], DBG_CMDDEC_CMDSEL0_RANK1_10GBEN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DBIWR_PROTECT) , P_Fld( 1 , DBIWR_PROTECT_DBIWR_IMP_EN ) \
| P_Fld( 0 , DBIWR_PROTECT_DBIWR_PINMUX_EN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RX_SET0) , P_Fld( 1 , RX_SET0_PRE_DLE_VLD_OPT ) \
| P_Fld( 7 , RX_SET0_DATLAT_PDLE_TH ));
//TODO SRAM MD32 control
// @Darren, sync MP settings from Joe (APB will be available when SRAM DMA access)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0) , P_Fld( 1 , MISC_SRAM_DMA0_PENABLE_LAT_WR ) \
| P_Fld( 1 , MISC_SRAM_DMA0_KEEP_APB_ARB_ENA ) \
| P_Fld( 1 , MISC_SRAM_DMA0_KEEP_SRAM_ARB_ENA ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_MD32_REG_SSPM_MCLK_DIV), P_Fld( 1 , SSPM_MCLK_DIV_MCLK_DCM_EN ));
//Indivial random sync
vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DBG_IRQ_CTRL1), 0xFFFFFFFF);
vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DBG_IRQ_CTRL4), 0xFFFFFFFF);
vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DBG_IRQ_CTRL7), 0xFFFFFFFF);
}
static void IO_Release(DRAMC_CTX_T *p)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld( 1 , MISC_CTRL1_R_DM_TX_ARCLK_OE ) \
| P_Fld( 1 , MISC_CTRL1_R_DM_TX_ARCMD_OE ));
if(LPDDR5_EN_S == 1)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ2) , P_Fld( 1 , B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0 ) \
| P_Fld( 1 , B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0 ) \
| P_Fld( 1 , B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0 ) \
| P_Fld( 1 , B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0) );
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ2) , P_Fld( 1 , B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1 ) \
| P_Fld( 1 , B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1 ) \
| P_Fld( 1 , B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1 ) \
| P_Fld( 1 , B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1) );
}
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7) , P_Fld( 0 , CA_CMD7_RG_TX_ARCLKB_PULL_DN ) \
| P_Fld( 0 , CA_CMD7_RG_TX_ARCLKB_PULL_UP ) \
| P_Fld( 0 , CA_CMD7_RG_TX_ARCLK_PULL_DN ) \
| P_Fld( 0 , CA_CMD7_RG_TX_ARCLK_PULL_UP ) \
| P_Fld( 0 , CA_CMD7_RG_TX_ARCS0_PULL_DN ) \
| P_Fld( 0 , CA_CMD7_RG_TX_ARCS0_PULL_UP ) \
| P_Fld( 0 , CA_CMD7_RG_TX_ARCMD_PULL_DN ) \
| P_Fld( 0 , CA_CMD7_RG_TX_ARCMD_PULL_UP ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7) , P_Fld( 0 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0 ) \
| P_Fld( 0 , B0_DQ7_RG_TX_ARDQS0B_PULL_UP_B0 ) \
| P_Fld( 0 , B0_DQ7_RG_TX_ARDQS0_PULL_DN_B0 ) \
| P_Fld( 0 , B0_DQ7_RG_TX_ARDQS0_PULL_UP_B0 ) \
| P_Fld( 0 , B0_DQ7_RG_TX_ARDQM0_PULL_DN_B0 ) \
| P_Fld( 0 , B0_DQ7_RG_TX_ARDQM0_PULL_UP_B0 ) \
| P_Fld( 0 , B0_DQ7_RG_TX_ARDQ_PULL_DN_B0 ) \
| P_Fld( 0 , B0_DQ7_RG_TX_ARDQ_PULL_UP_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7) , P_Fld( 0 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1 ) \
| P_Fld( 0 , B1_DQ7_RG_TX_ARDQS0B_PULL_UP_B1 ) \
| P_Fld( 0 , B1_DQ7_RG_TX_ARDQS0_PULL_DN_B1 ) \
| P_Fld( 0 , B1_DQ7_RG_TX_ARDQS0_PULL_UP_B1 ) \
| P_Fld( 0 , B1_DQ7_RG_TX_ARDQM0_PULL_DN_B1 ) \
| P_Fld( 0 , B1_DQ7_RG_TX_ARDQM0_PULL_UP_B1 ) \
| P_Fld( 0 , B1_DQ7_RG_TX_ARDQ_PULL_DN_B1 ) \
| P_Fld( 0 , B1_DQ7_RG_TX_ARDQ_PULL_UP_B1 ));
//for dram spec CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA will help to fix CKE=0 before for meet 10ns tINIT2
//Assert DRAM reset PIN
#if !SA_CONFIG_EN
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1) , P_Fld( 1 , MISC_CTRL1_R_DMDA_RRESETB_I ));
#endif
}
static void DVFS_PRE_config(DRAMC_CTX_T *p)
{
#if (fcFOR_CHIP_ID == fcMargaux)
U32 MCP_EN = 0; //remove for MCP timing issue
#else
U32 MCP_EN = 1; //for MCP should adjust some setting between CHs (A-B/C-D)
#endif
U32 REF_104M_EN = 1;
DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
mcSHOW_DBG_MSG(("Enter into DVFS_PRE_config >>>>> \n"));
#if ENABLE_ECO_SRAM_DMA_MISS_REG
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ11 ) , P_Fld( 1 , B0_DQ11_DMY_DQ11_B0 ));
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ11 ) , P_Fld( 1 , B1_DQ11_DMY_DQ11_B1 ));
#endif
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0) , P_Fld( 1 , DVFS_CTRL0_VRCG_EN ) \
| P_Fld( 0 , DVFS_CTRL0_DVFS_SYNC_MASK ) \
| P_Fld( 1 , DVFS_CTRL0_MR13_SHU_EN ) \
| P_Fld( 1 , DVFS_CTRL0_HWSET_WLRL ) \
| P_Fld( 0 , DVFS_CTRL0_MRWWOPRA )); //Have to fix 0, 1 with bug (some bank without precharge)
//for DVFS sync
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RG_DFS_CTRL) , P_Fld( 0 , MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL ));//SPM mode TODO should random 0 for SPM mode default
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0 ) , P_Fld( 0 , MISC_SRAM_DMA0_DMA_TIMER_EN ));
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA1 ) , P_Fld( 0x1ffff , MISC_SRAM_DMA1_SPM_RESTORE_STEP_EN ));
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL7 ) , P_Fld( 1 , MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL ));
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL ) , P_Fld( 1 , MISC_DVFSCTL_R_DVFS_PICG_POSTPONE ) \
| P_Fld( 1 , MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT ));
//for channel balance
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2) , P_Fld( 0 , MISC_DVFSCTL2_R_CDC_MUX_SEL_OPTION ) \
| P_Fld( 0 , MISC_DVFSCTL2_R_DVFS_SYNC_MODULE_RST_SEL ));
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2) , P_Fld( 1 , MISC_DVFSCTL2_R_DVFS_CDC_OPTION ));
//Could be randomed
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0 ) , P_Fld( 0 , DVFS_CTRL0_DVFS_CKE_OPT ) \
| P_Fld( 1 , DVFS_CTRL0_SCARB_PRI_OPT ));
//here is a flow??--TODO
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3 ) , P_Fld( 1 , MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK ) \
| P_Fld( 0 , MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_BCLK ) \
| P_Fld( 0 , MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_MCLK ) \
| P_Fld( 1 , MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK ) \
| P_Fld( 3 , MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI ) \
| P_Fld( 1 , MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE ) \
| P_Fld( 7 , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK) \
| P_Fld( 1 , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_MCLK) \
| P_Fld( 0x3f , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK) );
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CLK_CTRL ) , P_Fld( 1 , MISC_CLK_CTRL_DVFS_CLK_MEM_SEL ) \
| P_Fld( 1 , MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN ));
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3 ) , P_Fld( 0x10 , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK));
//flow end??
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_DVFS_TIMING_CTRL1) , P_Fld( 1 , DVFS_TIMING_CTRL1_DMSHU_CNT )\
| P_Fld( 1 , DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT ));
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2 ) , P_Fld( 1 , MISC_DVFSCTL2_R_DVFS_CDC_OPTION )\
| P_Fld( 0 , MISC_DVFSCTL2_R_DVFS_DLL_CHA )\
| P_Fld( 1 , MISC_DVFSCTL2_RG_TOPCK_FMEM_CK_BLOCK_DURING_DFS )\
| P_Fld( 1 , MISC_DVFSCTL2_R_DVFS_PARK_N )\
| P_Fld( 1 , MISC_DVFSCTL2_R_DVFS_OPTION ));
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL ) , P_Fld( REF_104M_EN , MISC_CKMUX_SEL_RG_52M_104M_SEL ));
//notice here:
//*SHU_PHDET_SPM_EN = 1 means during DFS period as master. 2 means slave.
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_OPT ) , P_Fld( 1 , MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN )\
| P_Fld( 2 , MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN )\
| P_Fld( 1 , MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN )\
| P_Fld( 2 , MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN )\
| P_Fld( 1 , MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN )\
| P_Fld( 1 , MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN ));
vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL ) , P_Fld((REF_104M_EN==1)?3:1, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW ) \
| P_Fld((REF_104M_EN==1)?3:1, MISC_DVFSCTL_R_DVFS_PICG_MARGIN2_NEW ) \
| P_Fld((REF_104M_EN==1)?3:1, MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW ) );
if(A_T->DLL_ASYNC_EN == 0)
{
mcSHOW_DBG_MSG(("Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. \n"));
//DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
vSetPHY2ChannelMapping(p, CHANNEL_B);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2 ) , P_Fld( 0 , MISC_DVFSCTL2_R_DVFS_DLL_CHA ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_OPT ) , P_Fld( 2 , MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN ));
#if (CHANNEL_NUM>2)
vSetPHY2ChannelMapping(p, CHANNEL_D);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2 ) , P_Fld( 0 , MISC_DVFSCTL2_R_DVFS_DLL_CHA ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_OPT ) , P_Fld( 2 , MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN ));
#endif
vSetPHY2ChannelMapping(p, CHANNEL_A);
//DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
}
if(MCP_EN == 1)
{
//DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
vSetPHY2ChannelMapping(p, CHANNEL_B);
mcSHOW_DBG_MSG(("MCP Enable leading 2ch's sync singles should adjust delay margin."));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL ) , P_Fld((REF_104M_EN==1)?6:4, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3 ) , P_Fld( 9 , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK ));
#if (CHANNEL_NUM>2)
vSetPHY2ChannelMapping(p, CHANNEL_D);
mcSHOW_DBG_MSG(("MCP Enable leading 2ch's sync singles should adjust delay margin."));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL ) , P_Fld((REF_104M_EN==1)?6:4, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3 ) , P_Fld( 9 , MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK ));
#endif
vSetPHY2ChannelMapping(p, CHANNEL_A);
//DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
}
//DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL ) , P_Fld( 1 , MISC_CKMUX_SEL_FMEM_CK_MUX ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0) , P_Fld( 0 , DVFS_CTRL0_R_DRAMC_CHA )\
| P_Fld( 0 , DVFS_CTRL0_SHU_PHYRST_SEL ));
vSetPHY2ChannelMapping(p, CHANNEL_B);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL ) , P_Fld( 3 , MISC_CKMUX_SEL_FMEM_CK_MUX ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0) , P_Fld( 0 , DVFS_CTRL0_R_DRAMC_CHA )\
| P_Fld( 1 , DVFS_CTRL0_SHU_PHYRST_SEL ));
#if (CHANNEL_NUM>2)
vSetPHY2ChannelMapping(p, CHANNEL_C);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL ) , P_Fld( 1 , MISC_CKMUX_SEL_FMEM_CK_MUX ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0) , P_Fld( 0 , DVFS_CTRL0_R_DRAMC_CHA )\
| P_Fld( 0 , DVFS_CTRL0_SHU_PHYRST_SEL ));
vSetPHY2ChannelMapping(p, CHANNEL_D);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CKMUX_SEL ) , P_Fld( 3 , MISC_CKMUX_SEL_FMEM_CK_MUX ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_DVFS_CTRL0) , P_Fld( 0 , DVFS_CTRL0_R_DRAMC_CHA )\
| P_Fld( 1 , DVFS_CTRL0_SHU_PHYRST_SEL ));
#endif
vSetPHY2ChannelMapping(p, CHANNEL_A);
DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
mcSHOW_DBG_MSG(("Exit from DVFS_PRE_config <<<<< \n"));
}
void DIG_STATIC_SETTING(DRAMC_CTX_T *p)
{
DIG_PHY_config(p);
GATING_MODE_CFG(&Gat_p);
DPHY_GAT_TRACK_Config(p,&Gat_p);
DRAMC_COMMON_Config(p);
#if 1//!SA_CONFIG_EN
DVFS_PRE_config(p);//for DVFS initial config.-- bring-up no need this code. but DVFS will need this
#endif
DDRPHY_PICG_Config(p);
IO_Release(p);
RX_INTPUT_Config(p);//TODO dummy write trigger
}
#if 0
void DPI_DIG_init(void)
{
mysetscope();
DIG_STATIC_SETTING(DramcConfig);
}
#endif

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src/vendorcode/mediatek/mt8192/dramc/DIG_SHUF_config.c Normal file
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@ -0,0 +1,621 @@
/* SPDX-License-Identifier: BSD-3-Clause */
#include "dramc_dv_init.h"
//====================================
//TX CA delay configuration
//------------------------------------
//Notice:
//TX config with shuffle register with all data_rate the same
//if under real IC , need to banlance the PI/Dline calibrated result
//====================================
static void DIG_CONFIG_SHUF_ALG_TXCA(DRAMC_CTX_T *p, int ch_id, int group_id)
{
mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id));
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
u8 TX_UI;
TX_UI = (DFS(group_id)->data_rate<=800) ? 1: 0 ; //TODO -- LPDDR5 need confirm
vSetPHY2ChannelMapping(p, ch_id);
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA1), P_Fld( 0 , SHU_SELPH_CA1_TXDLY_CS )\
| P_Fld( 0 , SHU_SELPH_CA1_TXDLY_CKE )\
| P_Fld( 0 , SHU_SELPH_CA1_TXDLY_ODT )\
| P_Fld( 0 , SHU_SELPH_CA1_TXDLY_RESET)\
| P_Fld( 0 , SHU_SELPH_CA1_TXDLY_WE )\
| P_Fld( 0 , SHU_SELPH_CA1_TXDLY_CAS )\
| P_Fld( 0 , SHU_SELPH_CA1_TXDLY_RAS )\
| P_Fld( 0 , SHU_SELPH_CA1_TXDLY_CS1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA2), P_Fld( 0 , SHU_SELPH_CA2_TXDLY_BA0 )\
| P_Fld( 0 , SHU_SELPH_CA2_TXDLY_BA1 )\
| P_Fld( 0 , SHU_SELPH_CA2_TXDLY_BA2 )\
| P_Fld( 0 , SHU_SELPH_CA2_TXDLY_CKE1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA3), P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA0 )\
| P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA1 )\
| P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA2 )\
| P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA3 )\
| P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA4 )\
| P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA5 )\
| P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA6 )\
| P_Fld( 0 , SHU_SELPH_CA3_TXDLY_RA7 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA4), P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA8 )\
| P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA9 )\
| P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA10 )\
| P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA11 )\
| P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA12 )\
| P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA13 )\
| P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA14 )\
| P_Fld( 0 , SHU_SELPH_CA4_TXDLY_RA15 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA5), P_Fld( TX_UI , SHU_SELPH_CA5_DLY_CS )\
| P_Fld( 1 , SHU_SELPH_CA5_DLY_CKE )\
| P_Fld( 0 , SHU_SELPH_CA5_DLY_ODT )\
| P_Fld( 1 , SHU_SELPH_CA5_DLY_RESET )\
| P_Fld( 1 , SHU_SELPH_CA5_DLY_WE )\
| P_Fld( 1 , SHU_SELPH_CA5_DLY_CAS )\
| P_Fld( 1 , SHU_SELPH_CA5_DLY_RAS )\
| P_Fld( TX_UI , SHU_SELPH_CA5_DLY_CS1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA6), P_Fld( 1 , SHU_SELPH_CA6_DLY_BA0 )\
| P_Fld( 1 , SHU_SELPH_CA6_DLY_BA1 )\
| P_Fld( 1 , SHU_SELPH_CA6_DLY_BA2 )\
| P_Fld( 1 , SHU_SELPH_CA6_DLY_CKE1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA7), P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA0 )\
| P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA1 )\
| P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA2 )\
| P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA3 )\
| P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA4 )\
| P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA5 )\
| P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA6 )\
| P_Fld( TX_UI , SHU_SELPH_CA7_DLY_RA7 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_CA8), P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA8 )\
| P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA9 )\
| P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA10 )\
| P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA11 )\
| P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA12 )\
| P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA13 )\
| P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA14 )\
| P_Fld( TX_UI , SHU_SELPH_CA8_DLY_RA15 ));
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id));
}
//====================================
//Impdance configuration
//------------------------------------
//Notice:
//ANA result depend on calibration
//====================================
static void DIG_CONFIG_SHUF_IMP(DRAMC_CTX_T *p, int ch_id, int group_id)
{
mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id));
U8 IPM_ODT_EN;
U8 CHKCYCLE = 7; //200ns algrith --TODO, @Darren, fix hw imp tracking
U8 TXDLY_CMD = 8; //Need algrithm support .. RL . TODO
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
vSetPHY2ChannelMapping(p, ch_id);
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
IPM_ODT_EN = (DFS(group_id)->data_rate>=2667) ? 1 : 0;
if (DFS(group_id)->data_rate>=4266)
TXDLY_CMD = 0xc;
else if (DFS(group_id)->data_rate>=3733)
TXDLY_CMD = 0xb;
else if (DFS(group_id)->data_rate>=3200)
TXDLY_CMD = 0xa;
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_DRVING2) , P_Fld(!IPM_ODT_EN , SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1) , P_Fld(CHKCYCLE , SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE )\
| P_Fld(8 , SHU_MISC_IMPCAL1_IMPCAL_CALICNT )\
| P_Fld(4 , SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE )\
| P_Fld(0x40 , SHU_MISC_IMPCAL1_IMPCALCNT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12) , P_Fld(IPM_ODT_EN?0x1b:0x0f , SHU_CA_CMD12_RG_RIMP_REV ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1), P_Fld(1 , MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVP_UPD_DIS )\
| P_Fld(1 , MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVN_UPD_DIS )\
| P_Fld(1 , MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_ODTN_UPD_DIS ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_DRVING6) , P_Fld(TXDLY_CMD , SHU_MISC_DRVING6_IMP_TXDLY_CMD ));
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id));
}
//====================================
//RX input delay configuration by mode choose
//------------------------------------
//Notice:
//
//====================================
static void DIG_CONFIG_SHUF_RXINPUT(DRAMC_CTX_T *p, int ch_id, int group_id)
{
U8 PERBYTE_TRACK_EN = 1;//TODO
U8 DQM_TRACK_EN = 1;//TODO --following RD DBI
U8 DQM_FLOW_DQ_SEL = 3;//TODO
U8 RX_force_upd = 0;//TODO
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
vSetPHY2ChannelMapping(p, ch_id);
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id));
if(RX_force_upd == 1)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ8), P_Fld(1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ8), P_Fld(1, SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1));
}
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7) , P_Fld(PERBYTE_TRACK_EN , SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0) \
| P_Fld(DQM_FLOW_DQ_SEL , SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0 ) \
| P_Fld(DQM_TRACK_EN , SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0 ) \
| P_Fld(DQM_TRACK_EN , SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7) , P_Fld(PERBYTE_TRACK_EN , SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1) \
| P_Fld(DQM_FLOW_DQ_SEL , SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1 ) \
| P_Fld(DQM_TRACK_EN , SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1 ) \
| P_Fld(DQM_TRACK_EN , SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ11) , P_Fld(1, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11) , P_Fld(1, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1));
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id));
}
#if ENABLE_WDQS_MODE_2
static void WDQSMode2TxDQOE_CNT(DRAMC_CTX_T *p, U8 *u1DQOE_CNT)
{
switch (p->frequency)
{
case 1866:
*u1DQOE_CNT = 6;
break;
case 1600:
case 1200:
case 800:
case 600:
*u1DQOE_CNT = 5;
break;
case 933:
*u1DQOE_CNT = 4;
break;
case 400:
*u1DQOE_CNT = 9;
break;
default:
mcSHOW_ERR_MSG(("[WDQSMode2TxDQOE_CNT] frequency err!\n"));
#if __ETT__
while (1);
#endif
}
}
#endif
//====================================
// MISC shuffle register fit
//------------------------------------
//Notice:
// MISC shuffle reigster should be fixed
//====================================
static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
{
U8 PICG_MODE = 1;
U8 LP5_HEFF = 0;//TODO
U8 LP5WRAPEN = 1;//Could random 1bit
U8 DQSIEN_DQSSTB_MODE=0;
U8 irank = 0;
U8 LP5_CASMODE = 1; //TODO Impact AC timing 1,2,3 three mode support 1:Low Power; 2:Low Freq; 3:High Eff;
U8 WCKDUAL = 0;
U8 NEW_RANK_MODE = 1;
U8 DUALSCHEN = 1;
U8 backup_rank = 0;
U8 DQOE_OPT = 0, DQOE_CNT = 0;
#if ENABLE_WDQS_MODE_2
DQOE_OPT = 1;
WDQSMode2TxDQOE_CNT(p, &DQOE_CNT);
#endif
backup_rank = p->rank;
mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] MISC >>>>>, group_id=%2d \n", group_id));
if(LPDDR4_EN_S)
{
DUALSCHEN = (A_D->DQ_P2S_RATIO==4) ? 0 : 1;
}
else if (LPDDR5_EN_S)
{
DUALSCHEN = (A_D->CA_P2S_RATIO==2) ? 0 : 1;
}
switch(DFS(group_id)->DQSIEN_MODE)
{
case 1: {DQSIEN_DQSSTB_MODE = 1;break;}
case 2: {DQSIEN_DQSSTB_MODE = 2;break;}
case 3: {DQSIEN_DQSSTB_MODE = 3;break;}
case 6: {DQSIEN_DQSSTB_MODE = 2;break;}
case 7: {DQSIEN_DQSSTB_MODE = 3;break;}
default: mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] Unexpected DFS(group_id)->DQSIEN_MODE=%1d input, group_id=%2d, \n",DFS(group_id)->DQSIEN_MODE, group_id));
}
switch(LP5_CASMODE)
{
case 1: {WCKDUAL=0;LP5_HEFF=0;break;}
case 2: {WCKDUAL=1;LP5_HEFF=0;break;}
case 3: {WCKDUAL=0;LP5_HEFF=1;break;}
default: mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] Unexpected LP5_CASMODE(%d) input\n",LP5_CASMODE));
}
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
vSetPHY2ChannelMapping(p, ch_id);
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0) , P_Fld( 1 , SHU_COMMON0_BL4 ) \
| P_Fld( (A_D->DQ_P2S_RATIO==8) , SHU_COMMON0_FREQDIV4 ) \
| P_Fld( (A_D->DQ_P2S_RATIO==4) , SHU_COMMON0_FDIV2 ) \
| P_Fld( LPDDR4_EN_S , SHU_COMMON0_BC4OTF ) \
| P_Fld( !(A_D->DQ_P2S_RATIO==4) , SHU_COMMON0_DM64BITEN ));//TODO
if(LPDDR5_EN_S == 1)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0) , P_Fld( (A_D->DQ_P2S_RATIO==16) , SHU_COMMON0_FREQDIV8 ) \
| P_Fld( (DFS(group_id)->data_rate>=3733) , SHU_COMMON0_LP5BGEN ) \
| P_Fld( (DFS(group_id)->data_rate<=3200) , SHU_COMMON0_LP5BGOTF ) \
| P_Fld( LP5_HEFF , SHU_COMMON0_LP5WCKON ) \
| P_Fld( (DFS(group_id)->data_rate>=4800) , SHU_COMMON0_DLE256EN ) \
| P_Fld( LP5WRAPEN , SHU_COMMON0_LP5WRAPEN ) \
| P_Fld( LP5_HEFF , SHU_COMMON0_LP5HEFF_MODE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL) , P_Fld( WCKDUAL , SHU_WCKCTRL_WCKDUAL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_WCKCTRL_1) , P_Fld( (A_D->CKR==2) , SHU_WCKCTRL_1_WCKSYNC_PRE_MODE));//TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_LP5_CMD) , P_Fld( (A_D->CA_P2S_RATIO==2) , SHU_LP5_CMD_LP5_CMD1TO2EN ));//TODO
}
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_ACTIMING_CONF), P_Fld( 1 , SHU_ACTIMING_CONF_TREFBWIG ) \
| P_Fld( 54 , SHU_ACTIMING_CONF_SCINTV ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_DCM_CTRL0) , P_Fld( 1 , SHU_DCM_CTRL0_FASTWAKE2 ) \
| P_Fld( 1 , SHU_DCM_CTRL0_FASTWAKE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_CONF0) , P_Fld( 1 , SHU_CONF0_ADVPREEN ) \
| P_Fld( 63 , SHU_CONF0_DMPGTIM ) \
| P_Fld( 0 , SHU_CONF0_REFTHD ) \
| P_Fld( 1 , SHU_CONF0_PBREFEN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_MATYPE) , P_Fld( 2 , SHU_MATYPE_MATYPE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_SCHEDULER) , P_Fld( DUALSCHEN , SHU_SCHEDULER_DUALSCHEN ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0) , P_Fld( 1 , TX_SET0_WPRE2T ));
//TODO SHU_TX_SET0_WPST1P5T OVER3200 DRAM spec need 1 but in TBA should random
//OE_EXT2UI strange rule.--TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0) , P_Fld( (A_D->DQ_P2S_RATIO==4) , SHU_TX_SET0_WDATRGO ) \
| P_Fld( (DFS(group_id)->data_rate>=3200) , SHU_TX_SET0_WPST1P5T ) \
| P_Fld( DQOE_OPT , SHU_TX_SET0_DQOE_OPT ) \
| P_Fld( DQOE_CNT , SHU_TX_SET0_DQOE_CNT ) \
| P_Fld( LPDDR5_EN_S , SHU_TX_SET0_OE_EXT2UI ) \
| P_Fld( ((DFS(group_id)->data_rate==1600) && (A_D->DQ_P2S_RATIO==8))?5:2, SHU_TX_SET0_TXUPD_W2R_SEL )); //TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL1), P_Fld( 0x30 , MISC_SHU_STBCAL1_STB_PI_TRACKING_RATIO) \
| P_Fld( 1 , MISC_SHU_STBCAL1_STB_UPDMASK_EN ) \
| P_Fld( 9 , MISC_SHU_STBCAL1_STB_UPDMASKCYC ) \
| P_Fld( (DFS(group_id)->data_rate > 1600) , MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL)); //TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL) , P_Fld( Gat_p.GAT_TRACK_EN , MISC_SHU_STBCAL_STBCALEN ) \
| P_Fld( Gat_p.GAT_TRACK_EN , MISC_SHU_STBCAL_STB_SELPHCALEN ) \
| P_Fld( DQSIEN_DQSSTB_MODE , MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE)); //TODO
//@Darren, NOTE: Fix gating error or fifo mismatch => DMSTBLAT date_rate=1866 >= 3 : 1
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL) , P_Fld( (((Gat_p.GAT_TRACK_EN)&&(DFS(group_id)->data_rate>=1866))?(2+Gat_p.VALID_LAT_VALUE):(0+Gat_p.VALID_LAT_VALUE)) , MISC_SHU_STBCAL_DMSTBLAT ) \
| P_Fld( 1 , MISC_SHU_STBCAL_PICGLAT ) \
| P_Fld( 1 , MISC_SHU_STBCAL_DQSG_MODE ) \
| P_Fld( PICG_MODE , MISC_SHU_STBCAL_DQSIEN_PICG_MODE));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RANKCTL), P_Fld( PICG_MODE , MISC_SHU_RANKCTL_RANK_RXDLY_OPT ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_MISC ), P_Fld( 1 , SHU_MISC_REQQUE_MAXCNT ));
for(irank = RANK_0; irank < p->support_rank_num; irank++)
{
vSetRank(p, irank);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL), P_Fld( 0 , MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT) \
| P_Fld( (A_D->DQ_P2S_RATIO == 4) , MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT));
}
vSetRank(p, backup_rank);
//RODT offset TODO
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB), P_Fld( 1 , MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN ) \
| P_Fld( 0 , MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE ) \
| P_Fld( (NEW_RANK_MODE)?1:PICG_MODE , MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE ) \
| P_Fld( 1 , MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL) \
| P_Fld( ((A_D->DQ_P2S_RATIO == 4)?2:0) , MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET ) \
| P_Fld( ((A_D->DQ_P2S_RATIO == 4)?1:4) , MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET ) \
| P_Fld( ((A_D->DQ_P2S_RATIO == 16)?19:((A_D->DQ_P2S_RATIO == 8)?13:10)) , MISC_SHU_RODTENSTB_RODTENSTB_EXT ));
//[SV] //SHL, fix RODT rd_period low 1T issue
// @Darren, confirm MP settings w/ Chau-Wei Wang (Jason)
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB1), P_Fld( ((DFS(group_id)->data_rate >=3200)?1:0) , MISC_SHU_RODTENSTB1_RODTENCGEN_TAIL ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RODTENSTB1), P_Fld( ((DFS(group_id)->data_rate >=3200)?2:1) , MISC_SHU_RODTENSTB1_RODTENCGEN_HEAD ));
switch (A_D->DQ_P2S_RATIO)
{
case 4:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 1 , MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 0 , MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE ) \
| P_Fld( 0 , MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT1 ), P_Fld( 1 , MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT ) \
| P_Fld( 1 , MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT ) \
| P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT ));
break;
}
case 8:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 2 , MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 1 , MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE ) \
| P_Fld( 1 , MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT1 ), P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT ) \
| P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT ) \
| P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT ));
break;
}
case 16:
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 3 , MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_SELPH_MODE), P_Fld( 2 , MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE ) \
| P_Fld( 2 , MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT1 ), P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT ) \
| P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT ) \
| P_Fld( 0 , MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT ));
break;
}
default:mcSHOW_DBG_MSG(("ERROR:Unexcepted A_D.DQ_P2S_RATIO = %2d \n", A_D->DQ_P2S_RATIO));
}
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_CKE_CTRL) , P_Fld( 0 , SHURK_CKE_CTRL_CKE_DBE_CNT ));
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] MISC <<<<<<, group_id=%2d \n", group_id));
}
static void DIG_CONFIG_SHUF_DQSGRETRY(DRAMC_CTX_T *p, int ch_id, int group_id)
{
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
vSetPHY2ChannelMapping(p, ch_id);
mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id=%2d \n", group_id));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_DQSG_RETRY1), P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_SW_RESET ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_SW_EN ) \
| P_Fld( (DFS(group_id)->data_rate>=3733) , MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_ONCE ) \
| P_Fld( (DFS(group_id)->data_rate>=3733) , MISC_SHU_DQSG_RETRY1_RETRY_3TIMES ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_1RANK ) \
| P_Fld( (DFS(group_id)->data_rate>=3733) , MISC_SHU_DQSG_RETRY1_RETRY_BY_RANK ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_DM4BYTE ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_DQSIENLAT ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_STBENCMP_ALLBYTE) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN ) \
| P_Fld( 0 /*@Darren, sync MP settings by YT (DFS(group_id)->data_rate>=3733)*/ , MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_CMP_DATA ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_ALE_BLOCK_MASK ) \
| P_Fld( (DFS(group_id)->data_rate>=3733) , MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE ) \
| P_Fld( (DFS(group_id)->data_rate>=3733) , MISC_SHU_DQSG_RETRY1_RETRY_USE_NON_EXTEND ) \
| P_Fld( (DFS(group_id)->data_rate>=3733) , MISC_SHU_DQSG_RETRY1_RETRY_USE_CG_GATING ) \
| P_Fld( 1 , MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_RANKSEL_FROM_PHY) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_PA_DISABLE ) \
| P_Fld( 0 , MISC_SHU_DQSG_RETRY1_RETRY_STBEN_RESET_MSK ) \
| P_Fld( (DFS(group_id)->data_rate>=3733) , MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE ));
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id=%2d \n", group_id));
}
static void DIG_CONFIG_SHUF_DBI(DRAMC_CTX_T *p, int ch_id, int group_id)
{
U8 RD_DBI_EN = 1;//TODO
U8 WR_DBI_EN = 1;//TODO
LP4_DRAM_CONFIG_T LP4_temp;
LP5_DRAM_CONFIG_T LP5_temp;
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] DBI >>>>>>, group_id=%2d \n", group_id));
if(LPDDR4_EN_S)
{
LP4_DRAM_config(DFS(group_id)->data_rate,&LP4_temp);
RD_DBI_EN = LP4_temp.DBI_RD;
WR_DBI_EN = LP4_temp.DBI_WR;
}
else
{//TODO LPDDR5 and other dram type not ready
LP5_DRAM_config(DFS(group_id),&LP5_temp);
RD_DBI_EN = LP5_temp.DBI_RD;
WR_DBI_EN = LP5_temp.DBI_WR;
}
vSetPHY2ChannelMapping(p, ch_id);
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7), P_Fld(RD_DBI_EN, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0 ) \
| P_Fld(RD_DBI_EN, SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7), P_Fld(RD_DBI_EN, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1 ) \
| P_Fld(RD_DBI_EN, SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), P_Fld(WR_DBI_EN, SHU_TX_SET0_DBIWR ));
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] DBI <<<<<<, group_id=%2d \n", group_id));
}
//TODO LPDDR5
static void DIG_CONFIG_SHUF_DVFSWLRL(DRAMC_CTX_T *p, int ch_id, int group_id)
{
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
LP4_DRAM_CONFIG_T LP4_temp;
U8 HWSET_MR13_OP_Value =0;
U8 HWSET_VRCG_OP_Value =0;
U8 HWSET_MR2_OP_Value =0;
mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id=%2d \n", group_id));
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
if(LPDDR4_EN_S)
{
LP4_DRAM_config (DFS(group_id)->data_rate,&LP4_temp);
HWSET_MR13_OP_Value = ((LP4_temp.WORK_FSP & 1) << 7) | ((LP4_temp.WORK_FSP & 1) << 6) | (( 0 << 5) | 8); //DMI default enable
HWSET_VRCG_OP_Value = ((LP4_temp.WORK_FSP & 1) << 7) | ((LP4_temp.WORK_FSP & 1) << 6);
HWSET_MR2_OP_Value = ((LP4_temp.MR_WL & 7) << 3) | (LP4_temp.MR_WL & 7);
} else {
mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] LPDDR5 have to use Run-time MRW to support DVFS! Do not Use HWSET_MR serial Registers."));
}
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), P_Fld(HWSET_MR13_OP_Value, SHU_HWSET_MR13_HWSET_MR13_OP ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), P_Fld(HWSET_VRCG_OP_Value, SHU_HWSET_VRCG_HWSET_VRCG_OP ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), P_Fld(0xb , SHU_HWSET_VRCG_VRCGDIS_PRDCNT));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR2 ), P_Fld(HWSET_MR2_OP_Value , SHU_HWSET_MR2_HWSET_MR2_OP ));
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
mcSHOW_DBG_MSG(("[test_sa.c]====>ch_id:%2d, group_id:%2d, DPI_TBA_DVFS_WLRL_setting Exit\n", ch_id, group_id));
}
//=================================================
//Jump ratio calculate and setting
//------------------------------------------------
//notice: 400 800 not support tracking TODO
// should confirm it with DQ_SEMI_OPEN =1 or not but not data_rate as condition
//
//================================================
#if 0
void TX_RX_jumpratio_calculate(DRAMC_CTX_T *p,int ch_id,int group_id)
{
int tar;
int ratio = 32;
int result[DFS_GROUP_NUM];
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
vSetPHY2ChannelMapping(p, ch_id);
mcSHOW_DBG_MSG(("[TX_RX_jumpratio_calculate]>>>>>>>> group_id = %1d",group_id));
for(tar = 0; tar<DFS_GROUP_NUM;tar++)
{
if(((DFS(group_id)->data_rate == 800) || (DFS(group_id)->data_rate == 400)) || ((DFS(tar)->data_rate == 800) || (DFS(tar)->data_rate == 400))) //TODO wihtout tracking
{
result[tar] = 0;
}
else
{
result[tar] = (int)(((float)(DFS(tar)->data_rate) * (float)ratio) / (float)(DFS(group_id)->data_rate) + 0.5); //+0.5 for roundup
}
mcSHOW_DBG_MSG(("\n[TXRX_jumpratio]current_group data_rate=%1d,tar_data_rate=%1d,jumpratio=%1d;\n",DFS(group_id)->data_rate,DFS(tar)->data_rate,result[tar]));
}
//=============================
//setting
//=============================
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_FREQ_RATIO_SET0), P_Fld( result[0] , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0) \
| P_Fld( result[1] , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1) \
| P_Fld( result[2] , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2) \
| P_Fld( result[3] , SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_FREQ_RATIO_SET1), P_Fld( result[4] , SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4) \
| P_Fld( result[5] , SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5) \
| P_Fld( result[6] , SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6) \
| P_Fld( result[7] , SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_FREQ_RATIO_SET2), P_Fld( result[8] , SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8) \
| P_Fld( result[9] , SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9));
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
mcSHOW_DBG_MSG(("[TX_RX_jumpratio_calculate]<<<<<<< group_id = %1d",group_id));
}
#endif
static void DIG_CONFIG_DVFS_DEPENDENCE(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
{
DIG_CONFIG_SHUF_DVFSWLRL(p,ch_id,group_id);
//TX_RX_jumpratio_calculate(p,ch_id,group_id);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_DVFSDLL ) , P_Fld((LPDDR4_EN_S==1)?0x37:0x37 , MISC_SHU_DVFSDLL_R_DLL_IDLE )\
| P_Fld((LPDDR4_EN_S==1)?0x4d:0x37 , MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE )\
| P_Fld( ana_top_p.ALL_SLAVE_EN , MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL )\
| P_Fld( 0 , MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL ));
}
//====================================
// Digital shuffle configuration entry
//------------------------------------
//Notice:
//
//====================================
void DIG_CONFIG_SHUF(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
{
DIG_CONFIG_SHUF_ALG_TXCA(p,ch_id,group_id);
DIG_CONFIG_SHUF_IMP(p,ch_id,group_id);
DIG_CONFIG_SHUF_RXINPUT(p,ch_id,group_id);
DIG_CONFIG_SHUF_MISC_FIX(p,ch_id,group_id);
DIG_CONFIG_SHUF_DQSGRETRY(p,ch_id,group_id);
DIG_CONFIG_SHUF_DBI(p,ch_id,group_id);
DIG_CONFIG_DVFS_DEPENDENCE(p,ch_id,group_id);
}
#if 0
void DIG_CONFIG_SHUF_init(void)
{
mysetscope();
DIG_CONFIG_SHUF(DramcConfig,0,0); //temp ch0 group 0
}
void OTHER_GP_INIT(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
{
U8 backup_ch_id = p->channel;
U8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
//notice here. Replace the A_D A_T with new frequency auto-generation
ANA_TOP_FUNCTION_CFG(A_T,DFS(group_id)->data_rate);
ANA_CLK_DIV_config(A_D,DFS(group_id));
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
ANA_sequence_shuffle_colletion(p,A_D);//these RG will be set during flow,but for DV another GP should be set directly
ANA_Config_shuffle(p,A_T,group_id);
DIG_CONFIG_SHUF(p,ch_id,group_id);
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
}
void DPI_OTHER_GP_INIT(U32 ch_id, U32 group_id)
{
mysetscope();
DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
OTHER_GP_INIT(DramcConfig,ch_id,group_id);
DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
conf_to_sram_sudo(0,group_id,1);
conf_to_sram_sudo(1,group_id,1);
//DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
//vSetPHY2ChannelMapping(DramcConfig, CHANNEL_A);
//DRAMC_DMA_CONF_to_SRAM(DramcConfig,group_id,1);
//vSetPHY2ChannelMapping(DramcConfig, CHANNEL_B);
//DRAMC_DMA_CONF_to_SRAM(DramcConfig,group_id,1);
//vSetPHY2ChannelMapping(DramcConfig, CHANNEL_A);
//DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
}
#endif

320
src/vendorcode/mediatek/mt8192/dramc/DRAMC_SUBSYS_config.c Normal file
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@ -0,0 +1,320 @@
/* SPDX-License-Identifier: BSD-3-Clause */
#include "dramc_dv_init.h"
DRAM_TYPE_T MEM_TYPE = LPDDR4;
LP4_DRAM_CONFIG_T LP4_INIT;
LP5_DRAM_CONFIG_T LP5_INIT;
ANA_top_config_T ana_top_p;
ANA_DVFS_CORE_T ANA_option;
DRAMC_DVFS_GROUP_CONFIG_T DFS_TOP[DFS_GROUP_NUM];
DRAMC_SUBSYS_CONFIG_T DV_p;
void ANA_TOP_FUNCTION_CFG(ANA_top_config_T *tr,U16 data_rate)
{
// tr-> DLL_ASYNC_EN = 0 ; //from DV random
// tr-> NEW_RANK_MODE = 1 ; //from DV random
// tr-> DLL_IDLE_MODE = 1 ; //from DV random
// tr-> LP45_APHY_COMB_EN= 1 ; //from DV define
// tr-> NEW_8X_MODE = 1 ;
tr->ALL_SLAVE_EN = (data_rate <= 1866)?1:0;
if(LPDDR5_EN_S == 1)
{
tr->TX_ODT_DIS = (data_rate <=3200) ? 1 : 0 ;
} else {
tr->TX_ODT_DIS = (data_rate <=2400) ? 1 : 0 ;
}
mcSHOW_DBG_MSG(("=================================== \n"));
mcSHOW_DBG_MSG(("ANA top config\n" ));
mcSHOW_DBG_MSG(("=================================== \n"));
mcSHOW_DBG_MSG(("DLL_ASYNC_EN = %2d\n",tr->DLL_ASYNC_EN ));
mcSHOW_DBG_MSG(("ALL_SLAVE_EN = %2d\n",tr->ALL_SLAVE_EN ));
mcSHOW_DBG_MSG(("NEW_RANK_MODE = %2d\n",tr->NEW_RANK_MODE ));
mcSHOW_DBG_MSG(("DLL_IDLE_MODE = %2d\n",tr->DLL_IDLE_MODE ));
mcSHOW_DBG_MSG(("LP45_APHY_COMB_EN = %2d\n",tr->LP45_APHY_COMB_EN));
mcSHOW_DBG_MSG(("TX_ODT_DIS = %2d\n",tr->TX_ODT_DIS ));
mcSHOW_DBG_MSG(("NEW_8X_MODE = %2d\n",tr->NEW_8X_MODE ));
mcSHOW_DBG_MSG(("=================================== \n"));
}
void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs)
{
U32 SEMI_OPEN_FMIN = 300;
U32 SEMI_OPEN_FMAX = 500;//lp4 600
U32 PI_FMIN = 600;
U32 DQ_PICK;
U32 CA_PICK; //U
U32 CA_MCKIO; //S
U32 MCKIO_SEMI; //Q
U16 data_rate;
data_rate = dfs->data_rate;
tr->DQ_P2S_RATIO = dfs->DQ_P2S_RATIO;
tr->CKR = dfs->CKR;
//tr->CA_P2S_RATIO
tr->CA_P2S_RATIO = tr->DQ_P2S_RATIO/tr->CKR;
//tr->DQ_CA_OPEN
tr->DQ_CA_OPEN = ( data_rate < (SEMI_OPEN_FMIN * 2) ) ? 1 : 0;
tr->DQ_SEMI_OPEN = ( data_rate/2 < PI_FMIN ) ? (1-tr->DQ_CA_OPEN) : ((data_rate <= SEMI_OPEN_FMAX*2) ? (1-tr->DQ_CA_OPEN) : 0);
tr->CA_SEMI_OPEN = (( data_rate/(tr->CKR*2) < PI_FMIN ) ? ((data_rate/(tr->CKR*2) > SEMI_OPEN_FMAX) ? 0 : (((tr->CA_P2S_RATIO>2)||(tr->DQ_SEMI_OPEN))*(1-tr->DQ_CA_OPEN))) : tr->DQ_SEMI_OPEN);
tr->CA_FULL_RATE = (tr->DQ_CA_OPEN == 1) ? ((tr->CKR>1)?1:0) : ((tr->DQ_SEMI_OPEN*tr->CA_SEMI_OPEN*(tr->CKR>>1)) + (( data_rate/(tr->CKR*2) < PI_FMIN) ? (1-tr->CA_SEMI_OPEN) : 0 ));
tr->DQ_CKDIV4_EN = ( tr->DQ_SEMI_OPEN == 1) ? DONT_CARE_VALUE : ((( (data_rate/2) < 1200 ) ? 1 : 0 ) * (1-tr->DQ_CA_OPEN)) ;
CA_MCKIO = (data_rate/(tr->CKR*2))*(1+tr->CA_FULL_RATE);
DQ_PICK = (tr->DQ_SEMI_OPEN == 1) ? 0 : (data_rate/2) ;
CA_PICK = (tr->CA_SEMI_OPEN == 1) ? CA_MCKIO*2 : ((CA_MCKIO>=PI_FMIN) ? CA_MCKIO : (( CA_MCKIO >= (PI_FMIN/2) ) ? CA_MCKIO*2 : CA_MCKIO *4 ));
tr->CA_CKDIV4_EN = ((CA_PICK < 1200 ) ? 1 : 0 ) * ( 1- tr->DQ_CA_OPEN) ;
tr->CA_PREDIV_EN = (data_rate >= 4800) ? 1 : 0 ;
#if SA_CONFIG_EN
if(LPDDR4_EN_S)
{
// @Darren, for LP4 8PH Delay
if (data_rate <= 1866)
tr->PH8_DLY = 0;
else if (data_rate <= 2400)
tr->PH8_DLY = 0x11;
else if (data_rate <= 3200)
tr->PH8_DLY = 0xc;
else if (data_rate <= 3733)
tr->PH8_DLY = 0x9;
else
tr->PH8_DLY = 0x7;
}
else
#endif
{
tr->PH8_DLY = ((tr->DQ_CA_OPEN == 0) && (tr->DQ_SEMI_OPEN == 0) && (tr->DQ_CKDIV4_EN == 0)) ? ( (1000000>>4)/data_rate -4) : DONT_CARE_VALUE;
}
MCKIO_SEMI = (tr->DQ_SEMI_OPEN * tr->CA_SEMI_OPEN * (data_rate/2)) + (1-tr->DQ_SEMI_OPEN) * tr->CA_SEMI_OPEN * CA_MCKIO;
tr->SEMI_OPEN_CA_PICK_MCK_RATIO = ( MCKIO_SEMI == 0) ? DONT_CARE_VALUE : (CA_PICK*tr->DQ_P2S_RATIO)/data_rate ; //need to be improved
tr->DQ_AAMCK_DIV = (tr->DQ_SEMI_OPEN == 0) ? ((tr->DQ_P2S_RATIO/2)*(1-tr->DQ_SEMI_OPEN)) : DONT_CARE_VALUE;
tr->CA_AAMCK_DIV = (tr->CA_SEMI_OPEN == 0) ? ((tr->DQ_P2S_RATIO/(2*tr->CKR))*(1+tr->CA_FULL_RATE)) : DONT_CARE_VALUE;
tr->CA_ADMCK_DIV = CA_PICK/(data_rate/tr->DQ_P2S_RATIO); //need to be improved
//tr->DQ_TRACK_CA_EN = ((data_rate/2) >= 2133) ? 1 : 0 ; //for Alucary confirm that 'interface timing' sign NOT OK.
tr->DQ_TRACK_CA_EN = 0 ;
tr->PLL_FREQ = ((DQ_PICK*2*(tr->DQ_CKDIV4_EN+1)) > (CA_PICK*2*(tr->CA_CKDIV4_EN+1))) ? (DQ_PICK*2*(tr->DQ_CKDIV4_EN+1)) : (CA_PICK*2*(tr->CA_CKDIV4_EN+1));
#if SA_CONFIG_EN
//de-sense
if(data_rate==2400)
tr->PLL_FREQ = 2366; //DDR2366
else if(data_rate==1200)
tr->PLL_FREQ = 2288; //DDR1144
else if(data_rate==3200 || data_rate==1600)
tr->PLL_FREQ = 3068; //DDR3068 DDR1534
else if(data_rate==800)
tr->PLL_FREQ = 3016; //DDR754
else if(data_rate==400)
tr->PLL_FREQ = 4000; //DDR250 Op
#endif
tr->DQ_UI_PI_RATIO = 32; //TODO:notice here. infact if DQ_SEMI_OPEM == 1 UI_PI_RATIO will only 4 lower 2bit wihtout use
tr->CA_UI_PI_RATIO = (tr->CA_SEMI_OPEN == 0) ? ((tr->CA_FULL_RATE == 1)? 64 : DONT_CARE_VALUE) : 32;
mcSHOW_DBG_MSG(("=================================== \n"));
mcSHOW_DBG_MSG(("data_rate = %4d\n" ,data_rate ));
mcSHOW_DBG_MSG(("CKR = %1d\n" ,tr->CKR ));
mcSHOW_DBG_MSG(("DQ_P2S_RATIO = %1d\n" ,tr->DQ_P2S_RATIO ));
mcSHOW_DBG_MSG(("=================================== \n"));
mcSHOW_DBG_MSG(("CA_P2S_RATIO = %1d\n" ,tr->CA_P2S_RATIO ));
mcSHOW_DBG_MSG(("DQ_CA_OPEN = %1d\n" ,tr->DQ_CA_OPEN ));
mcSHOW_DBG_MSG(("DQ_SEMI_OPEN = %1d\n" ,tr->DQ_SEMI_OPEN ));
mcSHOW_DBG_MSG(("CA_SEMI_OPEN = %1d\n" ,tr->CA_SEMI_OPEN ));
mcSHOW_DBG_MSG(("CA_FULL_RATE = %1d\n" ,tr->CA_FULL_RATE ));
mcSHOW_DBG_MSG(("DQ_CKDIV4_EN = %1d\n" ,tr->DQ_CKDIV4_EN ));
mcSHOW_DBG_MSG(("CA_CKDIV4_EN = %1d\n" ,tr->CA_CKDIV4_EN ));
mcSHOW_DBG_MSG(("CA_PREDIV_EN = %1d\n" ,tr->CA_PREDIV_EN ));
mcSHOW_DBG_MSG(("PH8_DLY = %1d\n" ,tr->PH8_DLY ));
mcSHOW_DBG_MSG(("SEMI_OPEN_CA_PICK_MCK_RATIO= %1d\n" ,tr->SEMI_OPEN_CA_PICK_MCK_RATIO));
mcSHOW_DBG_MSG(("DQ_AAMCK_DIV = %1d\n" ,tr->DQ_AAMCK_DIV ));
mcSHOW_DBG_MSG(("CA_AAMCK_DIV = %1d\n" ,tr->CA_AAMCK_DIV ));
mcSHOW_DBG_MSG(("CA_ADMCK_DIV = %1d\n" ,tr->CA_ADMCK_DIV ));
mcSHOW_DBG_MSG(("DQ_TRACK_CA_EN = %1d\n" ,tr->DQ_TRACK_CA_EN ));
mcSHOW_DBG_MSG(("CA_PICK = %2d\n" ,CA_PICK ));
mcSHOW_DBG_MSG(("CA_MCKIO = %1d\n" ,CA_MCKIO ));
mcSHOW_DBG_MSG(("MCKIO_SEMI = %1d\n" ,MCKIO_SEMI ));
mcSHOW_DBG_MSG(("PLL_FREQ = %1d\n" ,tr->PLL_FREQ ));
mcSHOW_DBG_MSG(("DQ_UI_PI_RATIO = %1d\n" ,tr->DQ_UI_PI_RATIO ));
mcSHOW_DBG_MSG(("CA_UI_PI_RATIO = %1d\n" ,tr->CA_UI_PI_RATIO ));
mcSHOW_DBG_MSG(("=================================== \n"));
}
void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr)
{
U8 gp_id;
tr->SRAM_EN = 1;
tr->MD32_EN = 1;
tr->a_cfg = &ana_top_p;
tr->a_opt = &ANA_option;
tr->lp4_init = &LP4_INIT;
tr->lp5_init = &LP5_INIT;
for(gp_id = 0; gp_id < DFS_GROUP_NUM; gp_id++)
{
tr->DFS_GP[gp_id] = &DFS_TOP[gp_id];
}
if(LPDDR4_EN_S)
{
(tr->DFS_GP[0])->data_rate = 4266; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
(tr->DFS_GP[1])->data_rate = 3200; (tr->DFS_GP[1])->DQ_P2S_RATIO = 8;
(tr->DFS_GP[2])->data_rate = 2400; (tr->DFS_GP[2])->DQ_P2S_RATIO = 8;
(tr->DFS_GP[3])->data_rate = 1866; (tr->DFS_GP[3])->DQ_P2S_RATIO = 8;
(tr->DFS_GP[4])->data_rate = 1600; (tr->DFS_GP[4])->DQ_P2S_RATIO = 4;
(tr->DFS_GP[5])->data_rate = 1200; (tr->DFS_GP[5])->DQ_P2S_RATIO = 4;
(tr->DFS_GP[6])->data_rate = 800 ; (tr->DFS_GP[6])->DQ_P2S_RATIO = 4;
(tr->DFS_GP[7])->data_rate = 400 ; (tr->DFS_GP[7])->DQ_P2S_RATIO = 4;
(tr->DFS_GP[8])->data_rate = 4266; (tr->DFS_GP[8])->DQ_P2S_RATIO = 4;
(tr->DFS_GP[9])->data_rate = 1600; (tr->DFS_GP[9])->DQ_P2S_RATIO = 4;
for(gp_id = 0; gp_id < DFS_GROUP_NUM; gp_id++)
{
(tr->DFS_GP[gp_id])->CKR = 1;
(tr->DFS_GP[gp_id])->DQSIEN_MODE = 1;
}
#if 0//DV_CONFIG_EN==1
tr->lp4_init->LP4Y_EN = DUT_p.LP4Y_EN ;
tr->lp4_init->WR_PST = DUT_p.LP4_WR_PST ;
tr->lp4_init->OTF = DUT_p.LP4_OTF ;
tr->a_cfg->NEW_8X_MODE = DUT_p.NEW_8X_MODE ;
tr->a_cfg->LP45_APHY_COMB_EN = 1 ;
tr->a_cfg->DLL_IDLE_MODE = DUT_p.DLL_IDLE_MODE ;
tr->a_cfg->NEW_RANK_MODE = DUT_p.NEW_RANK_MODE ;
tr->a_cfg->DLL_ASYNC_EN = DUT_p.DLL_ASYNC_EN ;
tr->MD32_EN = DUT_p.MD32_EN ;
tr->SRAM_EN = DUT_p.SRAM_EN ;
tr->GP_NUM = DUT_p.GP_NUM ;
for(gp_id = 0; gp_id < DV_p.GP_NUM; gp_id++)
{
tr->DFS_GP[gp_id]->data_rate = DUT_shu_p[gp_id].data_rate ;
tr->DFS_GP[gp_id]->DQSIEN_MODE = DUT_shu_p[gp_id].DQSIEN_MODE ;
tr->DFS_GP[gp_id]->DQ_P2S_RATIO = DUT_shu_p[gp_id].DQ_P2S_RATIO;
tr->DFS_GP[gp_id]->CKR = DUT_shu_p[gp_id].CKR ;
}
#endif
#if SA_CONFIG_EN
tr->lp4_init->EX_ROW_EN[0] = p->u110GBEn[RANK_0] ;
tr->lp4_init->EX_ROW_EN[1] = p->u110GBEn[RANK_1] ;
tr->lp4_init->BYTE_MODE[0] = 0 ;
tr->lp4_init->BYTE_MODE[1] = 0 ;
tr->lp4_init->LP4Y_EN = 0;//DUT_p.LP4Y_EN ;
tr->lp4_init->WR_PST = 1;//DUT_p.LP4_WR_PST ;
tr->lp4_init->OTF = 1;//DUT_p.LP4_OTF ;
tr->a_cfg->NEW_8X_MODE = 1;//DUT_p.NEW_8X_MODE ;
tr->a_cfg->LP45_APHY_COMB_EN = 1 ;
tr->a_cfg->DLL_IDLE_MODE = 1;//DUT_p.DLL_IDLE_MODE ;
tr->a_cfg->NEW_RANK_MODE = 1;//DUT_p.NEW_RANK_MODE ;
tr->a_cfg->DLL_ASYNC_EN = 0;//DUT_p.DLL_ASYNC_EN ;
tr->MD32_EN = 0;//DUT_p.MD32_EN ;
tr->SRAM_EN = 1;//DUT_p.SRAM_EN ;
tr->GP_NUM = 10;//DUT_p.GP_NUM ;
if(p->freq_sel==LP4_DDR4266)
{
(tr->DFS_GP[0])->data_rate = 4266; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
}
else if(p->freq_sel==LP4_DDR3733)
{
(tr->DFS_GP[0])->data_rate = 3733; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
}
else if(p->freq_sel==LP4_DDR3200)
{
(tr->DFS_GP[0])->data_rate = 3200; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
}
else if(p->freq_sel==LP4_DDR2400)
{
(tr->DFS_GP[0])->data_rate = 2400; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
}
else if(p->freq_sel==LP4_DDR1866)
{
(tr->DFS_GP[0])->data_rate = 1866; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
}
else if(p->freq_sel==LP4_DDR1600)
{
(tr->DFS_GP[0])->data_rate = 1600; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
}
else if(p->freq_sel==LP4_DDR1200)
{
(tr->DFS_GP[0])->data_rate = 1200; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8;
}
else if(p->freq_sel==LP4_DDR800)
{
(tr->DFS_GP[0])->data_rate = 800; (tr->DFS_GP[0])->DQ_P2S_RATIO = 4;
}
else if(p->freq_sel==LP4_DDR400)
{
(tr->DFS_GP[0])->data_rate = 400; (tr->DFS_GP[0])->DQ_P2S_RATIO = 4;
}
#endif
//==============================================
//Oterwise, SA should rebuild Top configuration.
//==============================================
LP4_DRAM_config(tr->DFS_GP[0]->data_rate,tr->lp4_init);
}
//TODO for LPDDR5
//data_rate DQ_P2S_RATIO
//[4800:6400] 16
//[1600:4800) 8
//[400 :1600] 4
//=========================
//data_rate CKR
//[3733:6400] 4
//[400 :3733) 2
else if (MEM_TYPE == LPDDR5)
{
#if SA_CONFIG_EN
if(p->freq_sel==LP5_DDR4266)
{
(tr->DFS_GP[0])->data_rate = 4266; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 2;
}
else if(p->freq_sel==LP5_DDR5500)
{
(tr->DFS_GP[0])->data_rate = 5500; (tr->DFS_GP[0])->DQ_P2S_RATIO = 16 ; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 2;
}
else
{
(tr->DFS_GP[0])->data_rate = 3200; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[0]->CKR = 2;tr->DFS_GP[0]->DQSIEN_MODE = 1;
}
#else
(tr->DFS_GP[0])->data_rate = 6400; (tr->DFS_GP[0])->DQ_P2S_RATIO = 16; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 1;
#endif
(tr->DFS_GP[1])->data_rate = 3200; (tr->DFS_GP[1])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[1]->CKR = 2;tr->DFS_GP[1]->DQSIEN_MODE = 1;
(tr->DFS_GP[2])->data_rate = 1600; (tr->DFS_GP[2])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[2]->CKR = 2;tr->DFS_GP[2]->DQSIEN_MODE = 1;
(tr->DFS_GP[3])->data_rate = 4266; (tr->DFS_GP[3])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[3]->CKR = 4;tr->DFS_GP[3]->DQSIEN_MODE = 1;
(tr->DFS_GP[4])->data_rate = 3733; (tr->DFS_GP[4])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[4]->CKR = 4;tr->DFS_GP[4]->DQSIEN_MODE = 1;
(tr->DFS_GP[5])->data_rate = 1600; (tr->DFS_GP[5])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[5]->CKR = 2;tr->DFS_GP[5]->DQSIEN_MODE = 1;
(tr->DFS_GP[6])->data_rate = 1200; (tr->DFS_GP[6])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[6]->CKR = 2;tr->DFS_GP[6]->DQSIEN_MODE = 1;
(tr->DFS_GP[7])->data_rate = 800 ; (tr->DFS_GP[7])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[7]->CKR = 2;tr->DFS_GP[7]->DQSIEN_MODE = 1;
(tr->DFS_GP[8])->data_rate = 400 ; (tr->DFS_GP[8])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[8]->CKR = 2;tr->DFS_GP[8]->DQSIEN_MODE = 1;
(tr->DFS_GP[9])->data_rate = 5500; (tr->DFS_GP[9])->DQ_P2S_RATIO = 16; tr->DFS_GP[9]->CKR = 4;tr->DFS_GP[9]->DQSIEN_MODE = 1;
LP5_DRAM_config(tr->DFS_GP[0],tr->lp5_init);
}
ANA_TOP_FUNCTION_CFG(tr->a_cfg,tr->DFS_GP[0]->data_rate);
ANA_CLK_DIV_config(tr->a_opt,tr->DFS_GP[0]);
mcSHOW_DBG_MSG(("=================================== \n"));
mcSHOW_DBG_MSG(("memory_type:%s \n",LPDDR5_EN_S?"LPDDR5":"LPDDR4" ));
mcSHOW_DBG_MSG(("GP_NUM : %1d \n",tr->GP_NUM ));
mcSHOW_DBG_MSG(("SRAM_EN : %1d \n",tr->SRAM_EN ));
mcSHOW_DBG_MSG(("MD32_EN : %1d \n",tr->MD32_EN ));
mcSHOW_DBG_MSG(("=================================== \n"));
}

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src/vendorcode/mediatek/mt8192/dramc/DRAM_config_collctioin.c Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
#include "dramc_dv_init.h"
//DRAM LP4 initial configuration
void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr)
{
tr->BYTE_MODE[0] = 0;//TODO
tr->BYTE_MODE[1] = 0;//TODO
#if 0 // @Darren, remove it
#if SA_CONFIG_EN
tr->EX_ROW_EN[0] = 0;//TODO
tr->EX_ROW_EN[1] = 0;//TODO
#else
tr->EX_ROW_EN[0] = 1;//TODO
tr->EX_ROW_EN[1] = 0;//TODO
#endif
#endif
tr->MR_WL = LP4_DRAM_INIT_RLWL_MRfield_config(data_rate);
tr->MR_RL = tr->MR_WL;
tr->BL = 2;
tr->RPST = 0;
tr->RD_PRE = 0;
tr->WR_PRE = 1;
tr->WR_PST = (data_rate>=2667)?1:0; //TODO
#if SA_CONFIG_EN
tr->DBI_WR = 0;
tr->DBI_RD = 0;
#else
tr->DBI_WR = (data_rate>=2667)?1:0;
tr->DBI_RD = (data_rate>=2667)?1:0;
#endif
// tr->DMI = 1;
tr->OTF = 1;
#if ENABLE_LP4Y_DFS
tr->LP4Y_EN = (data_rate>=1866)?0:1; //TODO, @Darren for LP4Y
#else
tr->LP4Y_EN = 0;
#endif
tr->WORK_FSP = (data_rate>=2667)?1:0;
mcSHOW_DBG_MSG(("=================================== \n"));
mcSHOW_DBG_MSG(("LPDDR4 DRAM CONFIGURATION\n" ));
mcSHOW_DBG_MSG(("=================================== \n"));
// mcSHOW_DBG_MSG(("BYTE_MODE = B%1b\n",tr->BYTE_MODE));
mcSHOW_DBG_MSG(("EX_ROW_EN[0] = 0x%1x\n",tr->EX_ROW_EN[0]));
mcSHOW_DBG_MSG(("EX_ROW_EN[1] = 0x%1x\n",tr->EX_ROW_EN[1]));
mcSHOW_DBG_MSG(("LP4Y_EN = 0x%1x\n",tr->LP4Y_EN ));
mcSHOW_DBG_MSG(("WORK_FSP = 0x%1x\n",tr->WORK_FSP ));
mcSHOW_DBG_MSG(("WL = 0x%1x\n",tr->MR_WL ));
mcSHOW_DBG_MSG(("RL = 0x%1x\n",tr->MR_RL ));
mcSHOW_DBG_MSG(("BL = 0x%1x\n",tr->BL ));
mcSHOW_DBG_MSG(("RPST = 0x%1x\n",tr->RPST ));
mcSHOW_DBG_MSG(("RD_PRE = 0x%1x\n",tr->RD_PRE ));
mcSHOW_DBG_MSG(("WR_PRE = 0x%1x\n",tr->WR_PRE ));
mcSHOW_DBG_MSG(("WR_PST = 0x%1x\n",tr->WR_PST ));
mcSHOW_DBG_MSG(("DBI_WR = 0x%1x\n",tr->DBI_WR ));
mcSHOW_DBG_MSG(("DBI_RD = 0x%1x\n",tr->DBI_RD ));
// mcSHOW_DBG_MSG(("DMI = 0x%1x\n",tr->DMI ));
mcSHOW_DBG_MSG(("OTF = 0x%1x\n",tr->OTF ));
mcSHOW_DBG_MSG(("=================================== \n"));
}
//LP4 dram initial ModeRegister setting
U8 LP4_DRAM_INIT_RLWL_MRfield_config(U32 data_rate)
{
U8 MR2_RLWL;
if ((data_rate<=4266) && (data_rate > 3733)) {MR2_RLWL = 7 ;}
else if ((data_rate<=3733) && (data_rate > 3200)) {MR2_RLWL = 6 ;}
else if ((data_rate<=3200) && (data_rate > 2667)) {MR2_RLWL = 5 ;}
else if ((data_rate<=2667) && (data_rate > 2400)) {MR2_RLWL = 4 ;}
else if ((data_rate<=2400) && (data_rate > 1866)) {MR2_RLWL = 4 ;}
else if ((data_rate<=1866) && (data_rate > 1600)) {MR2_RLWL = 3 ;}
else if ((data_rate<=1600) && (data_rate > 1200)) {MR2_RLWL = 2 ;}
else if ((data_rate<=1200) && (data_rate > 800 )) {MR2_RLWL = 2 ;}
else if ((data_rate<=800 ) && (data_rate > 400 )) {MR2_RLWL = 2 ;}
else if (data_rate<=400 ) {MR2_RLWL = 0 ;}
else {mcSHOW_DBG_MSG(("ERROR: Unexpected data_rate:%4d under LPDDR4 \n",data_rate));return -1;}
mcSHOW_DBG_MSG(("[ModeRegister RLWL Config] data_rate:%4d-MR2_RLWL:%1x\n",data_rate,MR2_RLWL));
return MR2_RLWL;
}
U32 Get_RL_by_MR_LP4(U8 BYTE_MODE_EN,U8 DBI_EN, U8 MR_RL_field_value)
{
U32 RL=0;
switch(MR_RL_field_value)
{
case 0: {RL = 6; break;}
case 1: {RL = (BYTE_MODE_EN == 1) ? ( 12 ) : ((DBI_EN == 1) ? 12 : 10); break;}
case 2: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 18 : 16 ) : ((DBI_EN == 1) ? 16 : 14); break;}
case 3: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 24 : 22 ) : ((DBI_EN == 1) ? 22 : 20); break;}
case 4: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 30 : 28 ) : ((DBI_EN == 1) ? 28 : 24); break;}
case 5: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 36 : 32 ) : ((DBI_EN == 1) ? 32 : 28); break;}
case 6: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 40 : 36 ) : ((DBI_EN == 1) ? 36 : 32); break;}
case 7: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 44 : 40 ) : ((DBI_EN == 1) ? 40 : 36); break;}
default:{mcSHOW_DBG_MSG(("ERROR: Unexpected MR_RL_field_value:%1x under LPDDR4 \n",MR_RL_field_value));}
}
mcSHOW_DBG_MSG(("[ReadLatency GET] BYTE_MODE_EN:%1d-DBI_EN:%1d-MR_RL_field_value:%1x-RL:%2d\n",BYTE_MODE_EN,DBI_EN,MR_RL_field_value,RL));
return RL;
}
U32 Get_WL_by_MR_LP4(U8 Version, U8 MR_WL_field_value)
{
U32 WL=0;
switch(MR_WL_field_value)
{
case 0: {WL = 4; break;}
case 1: {WL = ((Version == 0) ? 6 : 8 ); break;}
case 2: {WL = ((Version == 0) ? 8 : 12 ); break;}
case 3: {WL = ((Version == 0) ? 10 : 18 ); break;}
case 4: {WL = ((Version == 0) ? 12 : 22 ); break;}
case 5: {WL = ((Version == 0) ? 14 : 26 ); break;}
case 6: {WL = ((Version == 0) ? 16 : 30 ); break;}
case 7: {WL = ((Version == 0) ? 18 : 34 ); break;}
default:{mcSHOW_DBG_MSG(("ERROR: Unexpected MR_WL_field_value:%1x under LPDDR4 \n",MR_WL_field_value));}
}
mcSHOW_DBG_MSG(("[WriteLatency GET] Version:%1d-MR_RL_field_value:%1x-WL:%2d\n",Version,MR_WL_field_value,WL));
return WL;
}
//LP5 dram initial ModeRegister setting
static U8 LP5_DRAM_INIT_RLWL_MRfield_config(U32 data_rate)
{
U8 MR2_RLWL=0;
if ((data_rate<=6400) && (data_rate > 6000)) {MR2_RLWL = 11 ;}
else if ((data_rate<=6400) && (data_rate > 5500)) {MR2_RLWL = 10 ;}
else if ((data_rate<=5500) && (data_rate > 4800)) {MR2_RLWL = 9 ;}
else if ((data_rate<=4800) && (data_rate > 4266)) {MR2_RLWL = 8 ;}
else if ((data_rate<=4266) && (data_rate > 3733)) {MR2_RLWL = 7 ;}
else if ((data_rate<=3700) && (data_rate > 3200)) {MR2_RLWL = 6 ;}
else if ((data_rate<=3200) && (data_rate > 2400)) {MR2_RLWL = 5 ;}
else if ((data_rate<=2400) && (data_rate > 1866)) {MR2_RLWL = 4 ;}
else if ((data_rate<=1866) && (data_rate > 1600)) {MR2_RLWL = 3 ;}
else if ((data_rate<=1600) && (data_rate >= 800)) {MR2_RLWL = 2 ;}
else {mcSHOW_DBG_MSG(("ERROR: Unexpected data_rate:%4d under LPDDR5 \n",data_rate));return -1;}
mcSHOW_DBG_MSG(("[ModeRegister RLWL Config] data_rate:%4d-MR2_RLWL:%1x\n",data_rate,MR2_RLWL));
return MR2_RLWL;
}
void LP5_DRAM_config(DRAMC_DVFS_GROUP_CONFIG_T *dfs_tr, LP5_DRAM_CONFIG_T *tr)
{
tr->BYTE_MODE[0] = 0 ;
tr->BYTE_MODE[1] = 0 ;
tr->EX_ROW_EN[0] = 0 ;
tr->EX_ROW_EN[1] = 0 ;
tr->MR_WL = LP5_DRAM_INIT_RLWL_MRfield_config(dfs_tr->data_rate);
tr->MR_RL = tr->MR_WL;
tr->BL = 2;
tr->CK_Mode = (dfs_tr->data_rate>=2133)?0:1; //0:diff 1:SE
tr->RPST = 0;
tr->RD_PRE = 0;
tr->WR_PRE = 1;
tr->WR_PST = (dfs_tr->data_rate>=3200)?1:0 ;
#if SA_CONFIG_EN
tr->DBI_WR = 0;
#if LP5_DDR4266_RDBI_WORKAROUND
tr->DBI_RD = (dfs_tr->data_rate>=3733)?1:0 ;
#else
tr->DBI_RD = 0;
#endif
#else
tr->DBI_WR = (dfs_tr->data_rate>=3733)?1:0 ;
tr->DBI_RD = (dfs_tr->data_rate>=3733)?1:0 ;
#endif
tr->DMI = 1;
tr->OTF = 1;
tr->WCK_PST = (dfs_tr->data_rate>=3733)?1:0 ;
tr->RDQS_PST = 0;
tr->CA_ODT = 0;
tr->DQ_ODT = (dfs_tr->data_rate>=3733)?3:0 ;
tr->CKR = (dfs_tr->CKR==4)?0:1;
tr->WCK_ON = 0; //TODO
#if SA_CONFIG_EN
#if WCK_LEVELING_FM_WORKAROUND
tr->WCK_FM = 0;
#else
tr->WCK_FM = (dfs_tr->data_rate>=2133)?1:0;
#endif
#else
tr->WCK_FM = (dfs_tr->data_rate>=2133)?1:0;
#endif
tr->WCK_ODT = (dfs_tr->CKR==4)?3:0;
tr->DVFSQ = (dfs_tr->data_rate>=3733)?0:1;
tr->DVFSC = (dfs_tr->data_rate>=2133)?0:1;
tr->RDQSmode[0] = EN_both;//TODO --RK0 have to EN_t if SE enable
tr->RDQSmode[1] = EN_both;//TODO --RK1 have to EN_c if SE enable
tr->WCKmode[0] = (dfs_tr->data_rate>=1600)?0:1;
tr->WCKmode[1] = (dfs_tr->data_rate>=1600)?0:2;
tr->RECC = 0;//TODO
tr->WECC = 0;//TODO
tr->BankMode = (dfs_tr->data_rate>=3733)?BG4BK4:BK16;
tr->WORK_FSP = 0;//TODO
switch (dfs_tr->DQSIEN_MODE)
{
case 1: {tr->RDQS_PRE = 0;break;}
case 2: {tr->RDQS_PRE = 1;break;}
case 3: {tr->RDQS_PRE = 3;break;}
case 6: {tr->RDQS_PRE = 1;break;}
case 7: {tr->RDQS_PRE = 3;break;}
default : {mcSHOW_DBG_MSG(("ERROR: Unexpected DQSIEN_MODE :%d \n",dfs_tr->DQSIEN_MODE)); while(1);};
}
mcSHOW_DBG_MSG(("=================================== \n"));
mcSHOW_DBG_MSG(("LPDDR5 DRAM CONFIGURATION\n" ));
mcSHOW_DBG_MSG(("=================================== \n"));
mcSHOW_DBG_MSG(("MR_WL = 0x%1x\n",tr->MR_WL ));
mcSHOW_DBG_MSG(("MR_RL = 0x%1x\n",tr->MR_RL ));
mcSHOW_DBG_MSG(("BL = 0x%1x\n",tr->BL ));
mcSHOW_DBG_MSG(("CK_Mode = 0x%1x\n",tr->CK_Mode ));
mcSHOW_DBG_MSG(("RPST = 0x%1x\n",tr->RPST ));
mcSHOW_DBG_MSG(("RD_PRE = 0x%1x\n",tr->RD_PRE ));
mcSHOW_DBG_MSG(("RDQS_PRE = 0x%1x\n",tr->RDQS_PRE ));
mcSHOW_DBG_MSG(("WR_PRE = 0x%1x\n",tr->WR_PRE ));
mcSHOW_DBG_MSG(("WR_PST = 0x%1x\n",tr->WR_PST ));
mcSHOW_DBG_MSG(("DBI_WR = 0x%1x\n",tr->DBI_WR ));
mcSHOW_DBG_MSG(("DBI_RD = 0x%1x\n",tr->DBI_RD ));
mcSHOW_DBG_MSG(("DMI = 0x%1x\n",tr->DMI ));
mcSHOW_DBG_MSG(("OTF = 0x%1x\n",tr->OTF ));
mcSHOW_DBG_MSG(("WCK_PST = 0x%1x\n",tr->WCK_PST ));
mcSHOW_DBG_MSG(("RDQS_PST = 0x%1x\n",tr->RDQS_PST ));
mcSHOW_DBG_MSG(("CA_ODT = 0x%1x\n",tr->CA_ODT ));
mcSHOW_DBG_MSG(("DQ_ODT = 0x%1x\n",tr->DQ_ODT ));
mcSHOW_DBG_MSG(("CKR = 0x%1x\n",tr->CKR ));
mcSHOW_DBG_MSG(("WCK_ON = 0x%1x\n",tr->WCK_ON ));
mcSHOW_DBG_MSG(("WCK_FM = 0x%1x\n",tr->WCK_FM ));
mcSHOW_DBG_MSG(("WCK_ODT = 0x%1x\n",tr->WCK_ODT ));
mcSHOW_DBG_MSG(("DVFSQ = 0x%1x\n",tr->DVFSQ ));
mcSHOW_DBG_MSG(("DVFSC = 0x%1x\n",tr->DVFSC ));
mcSHOW_DBG_MSG(("RDQSmode[0] = 0x%1x\n",tr->RDQSmode[0] ));
mcSHOW_DBG_MSG(("RDQSmode[1] = 0x%1x\n",tr->RDQSmode[1] ));
mcSHOW_DBG_MSG(("WCKmode[0] = 0x%1x\n",tr->WCKmode[0] ));
mcSHOW_DBG_MSG(("WCKmode[1] = 0x%1x\n",tr->WCKmode[1] ));
mcSHOW_DBG_MSG(("RECC = 0x%1x\n",tr->RECC ));
mcSHOW_DBG_MSG(("WECC = 0x%1x\n",tr->WECC ));
mcSHOW_DBG_MSG(("BankMode = 0x%1x\n",tr->BankMode ));
mcSHOW_DBG_MSG(("WORK_FSP = 0x%1x\n",tr->WORK_FSP ));
mcSHOW_DBG_MSG(("=================================== \n"));
}

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src/vendorcode/mediatek/mt8192/dramc/Hal_io.c Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
#include "x_hal_io.h"
#include "dramc_common.h"
#include "dramc_int_global.h"
#if __ETT__
#include <barriers.h>
#endif
#ifdef DUMP_INIT_RG_LOG_TO_DE
U8 gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 0;
#endif
static U32 u4RegBaseAddrTraslate(DRAM_DFS_REG_SHU_T eShu, DRAM_RANK_T eRank, U32 u4reg_addr)
{
U32 u4Offset = u4reg_addr & 0xffff;
U32 u4RegType = ((u4reg_addr - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & 0xf;
U32 u4BaseAddr = 0;
if (u4reg_addr < Channel_A_DRAMC_NAO_BASE_VIRTUAL ||
u4reg_addr >= MAX_BASE_VIRTUAL)
{
return u4reg_addr;
}
if (u4RegType >= 2 && u4RegType <= 3)// ChA/B Dramc AO Register
{
if (u4Offset < DRAMC_REG_AO_SHUFFLE0_BASE_ADDR || u4Offset > DRAMC_REG_AO_SHUFFLE0_END_ADDR)
eShu = 0;
}
else if (u4RegType >= 6 && u4RegType <= 7)// ChA/B Dramc AO Register
{
if (u4Offset < DDRPHY_AO_SHUFFLE0_BASE_ADDR || u4Offset > DDRPHY_AO_SHUFFLE0_END_ADDR)
eShu = 0;
}
if (eRank == RANK_1)
{
if (u4RegType >= 2 && u4RegType <= 3)// ChA/B Dramc AO Register
{
if (u4Offset >= DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR &&
u4Offset <= DRAMC_REG_AO_RANK0_WO_SHUFFLE_END_ADDR)
{
u4Offset += DRAMC_REG_AO_RANK_OFFSET;
}
else if (u4Offset >= DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR &&
u4Offset <= DRAMC_REG_AO_RANK0_W_SHUFFLE0_END_ADDR)
{
u4Offset += DRAMC_REG_AO_RANK_OFFSET;
}
}
else if (u4RegType >= 6 && u4RegType <= 7)// PhyA/B AO Register
{
// 0x60~0xE0
if (u4Offset >= DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B0_NON_SHU_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x1E0~0x260
else if (u4Offset >= DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B1_NON_SHU_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x360~0x3E0
else if (u4Offset >= DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_CA_NON_SHU_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x760~0x7E0
else if (u4Offset >= DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B0_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0x8E0~0x960
else if (u4Offset >= DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_B1_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0xA60~0xAE0
else if (u4Offset >= DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_CA_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
// 0xBE0~0xC60
else if (u4Offset >= DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR &&
u4Offset <= DDRPHY_AO_RANK0_MISC_SHU0_END_ADDR)
{
u4Offset += DDRPHY_AO_RANK_OFFSET;
}
}
else if (u4RegType <= 1)// ChA/B Dramc NAO Register
{
if (u4Offset >= (DRAMC_REG_RK0_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS) &&
u4Offset < (DRAMC_REG_RK1_DQSOSC_STATUS - DRAMC_NAO_BASE_ADDRESS))
{
u4Offset += 0x100;
}
else if (u4Offset >= DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR &&
u4Offset <= DRAMC_REG_NAO_RANK0_ROW_OFFSET_END_ADDR)
{
u4Offset += DRAMC_REG_NAO_RANK_OFFSET;
}
}
else if (u4RegType >= 4 && u4RegType <= 5) // PhyA/B NAO Register
{
// PhyA/B NAO Register
if (u4Offset >= DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START &&
u4Offset < DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_END)
{
u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET;
}
else if (u4Offset >= DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START &&
u4Offset < DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_END)
{
u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET;
}
else if (u4Offset >= DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START &&
u4Offset < DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_END)
{
u4Offset += DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET;
}
else if (u4Offset >= DDRPHY_NAO_RANK0_GATING_STATUS_START &&
u4Offset < DDRPHY_NAO_RANK0_GATING_STATUS_END)
{
u4Offset += DDRPHY_NAO_GATING_STATUS_RK_OFFSET;
}
}
}
switch (u4RegType)
{
case 0:
u4BaseAddr = Channel_A_DRAMC_NAO_BASE_ADDRESS;
break;
case 1:
u4BaseAddr = Channel_B_DRAMC_NAO_BASE_ADDRESS;
break;
case 2:
u4BaseAddr = Channel_A_DRAMC_AO_BASE_ADDRESS + (eShu * DRAMC_REG_AO_SHU_OFFSET);
break;
case 3:
u4BaseAddr = Channel_B_DRAMC_AO_BASE_ADDRESS + (eShu * DRAMC_REG_AO_SHU_OFFSET);
break;
case 4:
u4BaseAddr = Channel_A_DDRPHY_NAO_BASE_ADDRESS;
break;
case 5:
u4BaseAddr = Channel_B_DDRPHY_NAO_BASE_ADDRESS;
break;
case 6:
u4BaseAddr = Channel_A_DDRPHY_AO_BASE_ADDRESS + (eShu * DDRPHY_AO_SHU_OFFSET);
break;
case 7:
u4BaseAddr = Channel_B_DDRPHY_AO_BASE_ADDRESS + (eShu * DDRPHY_AO_SHU_OFFSET);
break;
case 8:
u4BaseAddr = Channel_A_DDRPHY_DPM_BASE_ADDRESS;
break;
}
return (u4BaseAddr + u4Offset);
}
inline U32 _u4Dram_Register_Read(U64 u4reg_addr)
{
U32 u4reg_value;
#if (!__ETT__) && (FOR_DV_SIMULATION_USED == 0)
dsb();
#endif
#if QT_GUI_Tool
ucDramRegRead_1(u4reg_addr, &u4reg_value);
#elif (FOR_DV_SIMULATION_USED == 1) //DV
u4reg_value = register_read_c(u4reg_addr);
#else // real chip
u4reg_value = *((volatile unsigned int *)u4reg_addr);
#endif
return u4reg_value;
}
//-------------------------------------------------------------------------
/** ucDram_Register_Read
* DRAM register read (32-bit).
* @param u4reg_addr register address in 32-bit.
* @param pu4reg_value Pointer of register read value.
* @retval 0: OK, 1: FAIL
*/
//-------------------------------------------------------------------------
// This function need to be porting by BU requirement
U32 u4Dram_Register_Read(DRAMC_CTX_T *p, U32 u4reg_addr)
{
u4reg_addr = u4RegBaseAddrTraslate(p->ShuRGAccessIdx, p->rank, u4reg_addr);
return _u4Dram_Register_Read(u4reg_addr);
}
//-------------------------------------------------------------------------
/** ucDram_Register_Write
* DRAM register write (32-bit).
* @param u4reg_addr register address in 32-bit.
* @param u4reg_value register write value.
* @retval 0: OK, 1: FAIL
*/
//-------------------------------------------------------------------------
#if REG_ACCESS_NAO_DGB
#if (fcFOR_CHIP_ID == fcCervino)
U8 Check_RG_Not_AO(U32 u4reg_addr)
{
U8 RegNotAO = 0;
if ((u4reg_addr >= DRAMC_AO_BASE_ADDRESS) && (u4reg_addr <= DRAMC_REG_SHU4_DQSG_RETRY))
{
}
else if ((u4reg_addr >= DRAMC_AO_BASE_ADDRESS + SHIFT_TO_CHB_ADDR) && (u4reg_addr <= DRAMC_REG_SHU4_DQSG_RETRY + SHIFT_TO_CHB_ADDR))
{
}
else if ((u4reg_addr >= DDRPHY_AO_BASE_ADDR) && (u4reg_addr <= DDRPHY_RFU_0X1FCC))
{
}
else if ((u4reg_addr >= DDRPHY_AO_BASE_ADDR + SHIFT_TO_CHB_ADDR) && (u4reg_addr <= DDRPHY_RFU_0X1FCC + SHIFT_TO_CHB_ADDR))
{
}
else
{
RegNotAO = 1;
}
return RegNotAO;
}
#endif
#endif
inline void _ucDram_Register_Write(U64 u4reg_addr, U32 u4reg_value)
{
#if QT_GUI_Tool
ucDramRegWrite_1(u4reg_addr, u4reg_value);
#elif (FOR_DV_SIMULATION_USED == 1) //DV
register_write_c(u4reg_addr, u4reg_value);
#else // real chip
(*(volatile unsigned int *)u4reg_addr) = u4reg_value;//real chip
#if !defined(__MD32__)
dsb();
#endif
#endif
#ifdef DUMP_INIT_RG_LOG_TO_DE
if (gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag == 1)
{
mcSHOW_DUMP_INIT_RG_MSG(("*((UINT32P)(0x%x)) = 0x%x;\n",u4reg_addr,u4reg_value));
gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 0;
mcDELAY_MS(1); // to receive log for log
gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 1;
}
#endif
#if REG_ACCESS_PORTING_DGB
if (RegLogEnable)
{
mcSHOW_DBG_MSG(("\n[REG_ACCESS_PORTING_DBG] ucDramC_Register_Write Reg(0x%X) = 0x%X\n", u4reg_addr, u4reg_value));
}
#endif
}
//This function need to be porting by BU requirement
void ucDram_Register_Write(DRAMC_CTX_T *p, U32 u4reg_addr, U32 u4reg_value)
{
#if __ETT__
//CheckDramcWBR(u4reg_addr);
#endif
//mcSHOW_DBG_MSG(("\n[REG_ACCESS_PORTING_DBG] ucDramC_Register_Write Reg(0x%X) = 0x%X\n", u4reg_addr, u4reg_value));
u4reg_addr = u4RegBaseAddrTraslate(p->ShuRGAccessIdx, p->rank, u4reg_addr);
_ucDram_Register_Write(u4reg_addr, u4reg_value);
}
void vIO32Write4BMsk2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32)
{
U32 u4Val;
reg32 = u4RegBaseAddrTraslate(p->ShuRGAccessIdx, p->rank, reg32);
val32 &= msk32;
u4Val = _u4Dram_Register_Read(reg32);
u4Val = ((u4Val & ~msk32) | val32);
_ucDram_Register_Write(reg32, u4Val);
}
void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32)
{
U8 ii, u1AllCount;
U32 u4RegType = (reg32 & (0x1f << POS_BANK_NUM));
#if __ETT__
if (GetDramcBroadcast()==DRAMC_BROADCAST_ON)
{
mcSHOW_ERR_MSG(("Error! virtual address 0x%x don't have to use write_all when Dramc WBR is on\n", reg32));
while (1);
}
#endif
reg32 &= 0xffff; // remove channel information
u1AllCount = CHANNEL_NUM; // for all dramC and PHY
if (u4RegType >= Channel_A_DDRPHY_DPM_BASE_VIRTUAL)//DPM
{
reg32 += Channel_A_DDRPHY_DPM_BASE_VIRTUAL;
if (u1AllCount > 1)
u1AllCount >>= 1;
}
else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL)// PHY AO
{
reg32 += Channel_A_DDRPHY_AO_BASE_VIRTUAL;
}
else if (u4RegType >= Channel_A_DDRPHY_NAO_BASE_VIRTUAL)// PHY NAO
{
reg32 += Channel_A_DDRPHY_NAO_BASE_VIRTUAL;
}
else if (u4RegType >= Channel_A_DRAMC_AO_BASE_VIRTUAL)// DramC AO
{
reg32 += Channel_A_DRAMC_AO_BASE_VIRTUAL;
}
else // DramC NAO
{
reg32 += Channel_A_DRAMC_NAO_BASE_VIRTUAL;
}
for (ii = 0; ii < u1AllCount; ii++)
{
vIO32Write4B(reg32 + ((U32)ii << POS_BANK_NUM), val32);
}
}
void vIO32Write4BMsk_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32)
{
U32 u4Val, u4RegTmp;
U8 ii, u1AllCount;
U32 u4RegType = (reg32 & (0x1f << POS_BANK_NUM));
#if __ETT__
if (GetDramcBroadcast()==DRAMC_BROADCAST_ON)
{
mcSHOW_ERR_MSG(("Error! virtual address 0x%x don't have to use write_all when Dramc WBR is on\n", reg32));
while (1);
}
#endif
reg32 &= 0xffff; // remove channel information
u1AllCount = CHANNEL_NUM; // for all dramC and PHY
if (u4RegType >= Channel_A_DDRPHY_DPM_BASE_VIRTUAL)//DPM
{
reg32 += Channel_A_DDRPHY_DPM_BASE_VIRTUAL;
if (u1AllCount > 1)
u1AllCount >>= 1;
}
else if (u4RegType >= Channel_A_DDRPHY_AO_BASE_VIRTUAL)// PHY AO
{
reg32 += Channel_A_DDRPHY_AO_BASE_VIRTUAL;
}
else if (u4RegType >= Channel_A_DDRPHY_NAO_BASE_VIRTUAL)// PHY NAO
{
reg32 += Channel_A_DDRPHY_NAO_BASE_VIRTUAL;
}
else if (u4RegType >= Channel_A_DRAMC_AO_BASE_VIRTUAL)// DramC AO
{
reg32 += Channel_A_DRAMC_AO_BASE_VIRTUAL;
}
else // DramC NAO
{
reg32 += Channel_A_DRAMC_NAO_BASE_VIRTUAL;
}
for (ii = 0; ii < u1AllCount; ii++)
{
u4RegTmp = u4RegBaseAddrTraslate(p->ShuRGAccessIdx, p->rank, reg32 + ((U32)ii << POS_BANK_NUM));
u4Val = _u4Dram_Register_Read(u4RegTmp);
u4Val = ((u4Val & ~msk32) | val32);
_ucDram_Register_Write(u4RegTmp, u4Val);
}
}

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src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
#include "dramc_dv_init.h"
void CKE_FIX_ON(DRAMC_CTX_T *p, U8 EN, U8 rank)
{
switch(rank)
{
case 0 : vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), P_Fld(EN, CKECTRL_CKEFIXON)); break;
case 1 : vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), P_Fld(EN, CKECTRL_CKE1FIXON)); break;
default: mcSHOW_DBG_MSG(("ERROR: CKE FIX ON error. Unexpected Rank \n"));
}
}
//[SV] task LP4_MRS(bit [7:0] reg_addr, bit[7:0] reg_op, bit[1:0] rank);
static void LP4_MRS(DRAMC_CTX_T *p, U16 reg_addr, U8 reg_op, U8 rank)
{
U8 temp_MRS_RESPONSE ;
mcSHOW_DBG_MSG(("[LP4_DRAM_INIT_MRS] RK:%1d-MA:%2d-OP:0x%2x @Channle:%1d\n",rank,reg_addr,reg_op,vGetPHY2ChannelMapping(p)));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), P_Fld(rank , SWCMD_CTRL0_MRSRK ) \
| P_Fld(reg_addr, SWCMD_CTRL0_MRSMA ) \
| P_Fld(reg_op , SWCMD_CTRL0_MRSOP ));
vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), P_Fld(1, SWCMD_EN_MRWEN));
temp_MRS_RESPONSE = 0 ;
do
{
temp_MRS_RESPONSE = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_MRW_RESPONSE) ;
} while ( temp_MRS_RESPONSE != 1 );
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), P_Fld(0, SWCMD_EN_MRWEN));
}
static void LP4_FSP_WR_or_OP (DRAMC_CTX_T *p, U8 FSP_WR, U8 FSP_OP, U8 rank)
{
U8 MR13 = 0;
MR13 = ((FSP_OP & 1) << 7) | ((FSP_WR & 1) << 6) /*| ((LP4_DMI & 1) << 5)*/ | (1 << 4)/*[RRO] for MR4 refresh rate*/;
LP4_MRS(p, 13, MR13, rank);
}
//==================================
//uesage(constraint): DBI = 1 for FSPOP=1 if DBI=0 then FSP_OP =0
//==================================
static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 rank)
{
U8 MR1;
U8 MR2;
U8 MR3;
U8 MR51;
U8 MR11;
U8 MR12;
U8 MR14;
//default value for LP4 DRAM CONFIG
U8 nWR =5;
U8 WR_LEV =0;
U8 PDDS =5;
U8 PPRP =0;
U8 PU_CAL =0;
U8 WLS =0;
//Notice: DBI default = 0
//field & configuration adaption
MR1 = ((tr->RPST & 1)<<7) | ((nWR & 7)<<4) | ((tr->RD_PRE & 1)<<3) | ((tr->WR_PRE & 1)<<2) | ((tr->BL & 3)<<0);
MR2 = ((WR_LEV & 1)<<7) | ((WLS & 1)<<6) | ((tr->MR_WL & 7)<<3) | ((tr->MR_RL & 7)<<0);
MR3 = ((tr->DBI_WR & 1)<<7) | ((tr->DBI_RD & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0);
MR51= ((tr->LP4Y_EN & 1)<<3) | ((tr->LP4Y_EN & 1)<<2) | ((tr->LP4Y_EN & 1)<<1);
if(tr->WORK_FSP == 0)
{
MR11 = 0x0;
MR14 = 0x5d;
}
else
{
MR11 = 0x04;
MR14 = 0x18;
}
MR12= 0x5d;
#if FSP1_CLKCA_TERM
if(p->dram_fsp == FSP_1)
MR12 = 0x20;
#endif
//temp workaround for global variable of MR
u1MR02Value[tr->WORK_FSP] = MR2;
u1MR03Value[tr->WORK_FSP] = MR3;
#if ENABLE_LP4_ZQ_CAL
DramcZQCalibration(p, rank); //ZQ calobration should be done before CBT calibration by switching to low frequency
#endif
mcSHOW_DBG_MSG(("[LP4_DRAM_INIT] Channle:%1d-Rank:%1d >>>>>>\n",vGetPHY2ChannelMapping(p),rank));
//first FSP
if(tr->WORK_FSP == 0) {LP4_FSP_WR_or_OP(p, 0, 1, rank);}
else {LP4_FSP_WR_or_OP(p, 1, 0, rank);}
mcDELAY_XNS(15); //TCKFSPE
LP4_MRS(p, 1, MR1 , rank);
LP4_MRS(p, 2, MR2 , rank);
LP4_MRS(p, 3, MR3 , rank);
LP4_MRS(p, 11, MR11 , rank);
LP4_MRS(p, 12, MR12 , rank);
LP4_MRS(p, 14, MR14 , rank);
if(tr->LP4Y_EN == 1) { LP4_MRS(p, 51, MR51, rank); }
mcDELAY_XNS(15); //TCKFSPX
//2nd FSP
if(tr->WORK_FSP == 0) {LP4_FSP_WR_or_OP(p, 1, 0, rank);}
else {LP4_FSP_WR_or_OP(p, 0, 1, rank);}
mcDELAY_XNS(15); //TCKFSPE
LP4_MRS(p, 1, MR1 , rank);
LP4_MRS(p, 2, MR2 , rank);
//reverse the DBI
MR3 = ((!tr->DBI_WR & 1)<<7) | ((!tr->DBI_RD & 1)<<6) | (( PDDS & 7)<<3) | ((PPRP & 1)<<2) | ((tr->WR_PST & 1)<<1) | ((PU_CAL & 1)<<0);
LP4_MRS(p, 3, MR3 , rank);
LP4_MRS(p, 11, MR11 , rank);
LP4_MRS(p, 12, MR12 , rank);
LP4_MRS(p, 14, MR14 , rank);
LP4_FSP_WR_or_OP(p, tr->WORK_FSP, tr->WORK_FSP, rank);
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7) , P_Fld( 1 , CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7) , P_Fld( 1 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7) , P_Fld( 1 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y ));
mcSHOW_DBG_MSG(("[LP4_DRAM_INIT] Channle:%1d-Rank:%1d <<<<<<\n",vGetPHY2ChannelMapping(p),rank));
}
void LP4_single_end_DRAMC_post_config(DRAMC_CTX_T *p, U8 LP4Y_EN)
{
mcSHOW_DBG_MSG(("============ LP4 DIFF to SE enter ============\n"));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld( LP4Y_EN , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA ) \
| P_Fld( LP4Y_EN , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13) , P_Fld( LP4Y_EN , SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0 ) \
| P_Fld( LP4Y_EN , SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ13) , P_Fld( LP4Y_EN , SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1 ) \
| P_Fld( LP4Y_EN , SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD0) , P_Fld( 0 , SHU_CA_CMD0_R_LP4Y_WDN_MODE_CLK ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ0) , P_Fld( 0 , SHU_B0_DQ0_R_LP4Y_WDN_MODE_DQS0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ0) , P_Fld( 0 , SHU_B1_DQ0_R_LP4Y_WDN_MODE_DQS1 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD7) , P_Fld( 0 , SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK )); //@Darren, debugging for DFS stress fail
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ7) , P_Fld( LP4Y_EN , SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0 ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ7) , P_Fld( LP4Y_EN , SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1 ));
#if 1//ENABLE_LP4Y_DFS // @Darren, need confirm
// for strong pull low and normal mode
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7) , P_Fld( 0 , CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7) , P_Fld( 0 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7) , P_Fld( 0 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y ));
#else
// for weak pull low mode only
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD7) , P_Fld( 1 , CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7) , P_Fld( 1 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7) , P_Fld( 1 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y ));
#endif
mcSHOW_DBG_MSG(("============ LP4 DIFF to SE exit ============\n"));
}
void LP4_DRAM_INIT(DRAMC_CTX_T *p)
{
U8 RANK;
#if SA_CONFIG_EN && DV_SIMULATION_DFS// @Darren, temp workaround
DramcPowerOnSequence(p);
#endif
mcDELAY_XNS(200); //tINIT3 = 2ms for DV fastup to 200ns
for(RANK=0;RANK<2;RANK++)
{
CKE_FIX_ON(p,1,RANK);
mcDELAY_XNS(400); //tINIT5 fastup to 400ns
//step4 moderegister setting
lp4_dram_init_single_rank(p,DV_p.lp4_init,RANK);
CKE_FIX_ON(p,0,RANK);
}
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_REFCTRL0), P_Fld(0, REFCTRL0_REFDIS)); //TODO enable refresh
}

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src/vendorcode/mediatek/mt8192/dramc/Makefile.inc Normal file
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romstage-y += emi.c
romstage-y += ANA_init_config.c
romstage-y += DIG_NONSHUF_config.c
romstage-y += DIG_SHUF_config.c
romstage-y += dramc_actiming.c
romstage-y += dramc_dv_freq_related.c
romstage-y += dramc_dvfs.c
romstage-y += dramc_lowpower.c
romstage-y += DRAM_config_collctioin.c
romstage-y += dramc_pi_basic_api.c
romstage-y += dramc_pi_calibration_api.c
romstage-y += dramc_pi_main.c
romstage-y += DRAMC_SUBSYS_config.c
romstage-y += dramc_top.c
romstage-y += dramc_tracking.c
romstage-y += dramc_utility.c
romstage-y += Hal_io.c
romstage-y += LP4_dram_init.c
ramstage-y += emi.c

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src/vendorcode/mediatek/mt8192/dramc/dramc_actiming.c Normal file
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src/vendorcode/mediatek/mt8192/dramc/dramc_dv_freq_related.c Normal file
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src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c Normal file
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src/vendorcode/mediatek/mt8192/dramc/dramc_lowpower.c Normal file
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src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c Normal file
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src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c Normal file
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src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c Normal file
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src/vendorcode/mediatek/mt8192/dramc/dramc_top.c Normal file
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src/vendorcode/mediatek/mt8192/dramc/dramc_tracking.c Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
#include <assert.h>
#include <emi_hw.h>
#include <emi.h>
#include "dramc_reg_base_addr.h"
#include <dramc_top.h>
#include <soc/emi.h>
#ifdef LAST_EMI
static LAST_EMI_INFO_T* last_emi_info_ptr;
#endif
static inline unsigned int mt_emi_sync_read(unsigned long long addr)
{
dsb();
return *((volatile unsigned int *)addr);
}
#define mt_emi_sync_write(addr, value) \
do { \
*((volatile unsigned int *)(addr)) = value; \
dsb(); \
} while (0)
#define mt_emi_sync_write_or(addr, or_value) \
do { \
mt_emi_sync_write(addr, \
mt_emi_sync_read(addr) | or_value); \
} while (0)
static void emi_cen_config(void)
{
#ifndef ONE_CH
#ifdef RANK_512MB // => 2channel , dual rank , total=2G
mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xa053a154);
#else //RANK_1G => 2channel , dual rank , total=4G
mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xf053f154);
#endif
#else
#ifdef RANK_512MB
mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xa053a054);
#else
mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xf053f054);
#endif
#endif
// overhead: 20190821 item1 - synced
mt_emi_sync_write(EMI_APB_BASE+0x00000004,0x182e2d33); //3733 (1:8) r4 - r1 overhead // TBD - change to 4266
mt_emi_sync_write(EMI_APB_BASE+0x00000008,0x0f251025); //3733 (1:8) r8 - r5 overhead // TBD - change to 4266
mt_emi_sync_write(EMI_APB_BASE+0x0000000c,0x122a1027); //3733 (1:8) r12 - r9 overhead // TBD - change to 4266
mt_emi_sync_write(EMI_APB_BASE+0x00000010,0x1a31162d); //3733 (1:8) r16 - r13 overhead // TBD - change to 4266
mt_emi_sync_write(EMI_APB_BASE+0x000008b0,0x182e2d33); //3200 (1:8) r4 - r1 overhead
mt_emi_sync_write(EMI_APB_BASE+0x000008b4,0x0f251025); //3200 (1:8) r8 - r5 overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000001c,0x122a1027); //3200 (1:8) r12 - r9 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000024,0x1a31162d); //3200 (1:8) r16 - r13 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000034,0x1024202c); //2400 (1:8) r4 - r1 overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000006c,0x0b210c21); //2400 (1:8) r8 - r5 overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000013c,0x0f250d23); //2400 (1:8) r12 - r9 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000640,0x152b1228); //2400 (1:8) r16 - r13 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000044,0x0c201a28); //1866 (1:8) r4 - r1 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000074,0x0d230a20); //1866 (1:8) r8 - r5 overhead
mt_emi_sync_write(EMI_APB_BASE+0x000001e0,0x0e260d24); //1866 (1:8) r12 - r9 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000644,0x132d1229); //1866 (1:8) r16 - r13 overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000004c,0x0c201a28); //1600 (1:8) r4 - r1 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000084,0x0d230a20); //1600 (1:8) r8 - r5 overhead
mt_emi_sync_write(EMI_APB_BASE+0x000001e4,0x0e260d24); //1600 (1:8) r12 - r9 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000648,0x132d1229); //1600 (1:8) r16 - r13 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000054,0x0c201a28); //1200 (1:8) r4 - r1 overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000008c,0x0d230a20); //1200 (1:8) r8 - r5 overhead
mt_emi_sync_write(EMI_APB_BASE+0x000001e8,0x0e260d24); //1200 (1:8) r12 - r9 overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000064c,0x132d1229); //1200 (1:8) r16 - r13 overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000005c,0x0e290e28); //800 (1:4) r12 - r9 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000094,0x091e1322); //800 (1:4) r4 - r1 overhead
mt_emi_sync_write(EMI_APB_BASE+0x000001c8,0x0f29112a); //800 (1:4) r16 - r13 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000660,0x0c240a1f); //800 (1:4) r8 - r5 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000064,0x0e290e28); //800 (1:4) r12 - r9 overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000009c,0x091e1322); //800 (1:4) r4 - r1 overhead
mt_emi_sync_write(EMI_APB_BASE+0x000001f4,0x0f29112a); //800 (1:4) r16 - r13 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000664,0x0c240a1f); //800 (1:4) r8 - r5 overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000030,0x37373a57); //3733 (1:8) r8 - r2 non-align overhead // TBD - change to 4266
mt_emi_sync_write(EMI_APB_BASE+0x00000014,0x3f3f3c39); //3733 (1:8) r16 - r10 non-align overhead // TBD - change to 4266
mt_emi_sync_write(EMI_APB_BASE+0x000008b8,0x3836374e); //3200 (1:8) r8 - r2 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000002c,0x41413d3a); //3200 (1:8) r16 - r10 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x000000c4,0x33313241); //2400 (1:8) r8 - r2 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000668,0x3a3a3835); //2400 (1:8) r16 - r10 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x000000c8,0x34343542); //1866 (1:8) r8 - r2 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000066c,0x3b3b3835); //1866 (1:8) r16 - r10 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x000000cc,0x34343542); //1600 (1:8) r8 - r2 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000694,0x3b3b3835); //1600 (1:8) r16 - r10 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x000000e4,0x34343542); //1200 (1:8) r8 - r2 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000708,0x3b3b3835); //1200 (1:8) r16 - r10 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x000000f4,0x37333034); //800 (1:4) r8 - r2 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000070c,0x39393a39); //800 (1:4) r16 - r10 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x0000012c,0x37333034); //800 (1:4) r8 - r2 non-align overhead
mt_emi_sync_write(EMI_APB_BASE+0x00000748,0x39393a39); //800 (1:4) r16 - r10 non-align overhead
//
mt_emi_sync_write(EMI_APB_BASE+0x00000018,0x3657587a);
mt_emi_sync_write(EMI_APB_BASE+0x00000020,0x0000c042);
mt_emi_sync_write(EMI_APB_BASE+0x00000028,0x08421000);
mt_emi_sync_write(EMI_APB_BASE+0x00000038,0x00000083);
mt_emi_sync_write(EMI_APB_BASE+0x0000003c,0x00073210);
mt_emi_sync_write(EMI_APB_BASE+0x00000040,0x00008802);
mt_emi_sync_write(EMI_APB_BASE+0x00000048,0x00000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000060,0x007812ff); // reserved buffer to normal rea d/write :8/7
mt_emi_sync_write(EMI_APB_BASE+0x00000068,0x00000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000078,0x11120c1f); //22:20=ultra_w=1
mt_emi_sync_write(EMI_APB_BASE+0x00000710,0x11120c1f); //22:20=ultra_w=1
mt_emi_sync_write(EMI_APB_BASE+0x0000007c,0x00001123);
mt_emi_sync_write(EMI_APB_BASE+0x00000718,0x00001123);
mt_emi_sync_write(EMI_APB_BASE+0x000000d0,0xa8a8a8a8);
mt_emi_sync_write(EMI_APB_BASE+0x000000d4,0x25252525);
mt_emi_sync_write(EMI_APB_BASE+0x000000d8,0xa8a8a8a8);
mt_emi_sync_write(EMI_APB_BASE+0x000000dc,0x25252525);
mt_emi_sync_write(EMI_APB_BASE+0x000000e8,0x00060037); // initial starvation counter di v2, [4]=1
mt_emi_sync_write(EMI_APB_BASE+0x000000f0,0x384a0014);
mt_emi_sync_write(EMI_APB_BASE+0x000000f8,0xa0000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000100,0x20107244);
mt_emi_sync_write(EMI_APB_BASE+0x00000108,0x10107044);
mt_emi_sync_write(EMI_APB_BASE+0x00000110,0x343450df);
mt_emi_sync_write(EMI_APB_BASE+0x00000118,0x0000f0d0);
mt_emi_sync_write(EMI_APB_BASE+0x00000120,0x10106048);
mt_emi_sync_write(EMI_APB_BASE+0x00000128,0x343450df);
mt_emi_sync_write(EMI_APB_BASE+0x00000130,0x83837044);
mt_emi_sync_write(EMI_APB_BASE+0x00000138,0x83837044);
mt_emi_sync_write(EMI_APB_BASE+0x00000140,0x00007108);
mt_emi_sync_write(EMI_APB_BASE+0x00000144,0x00007108);
mt_emi_sync_write(EMI_APB_BASE+0x00000150,0x090a4000);
mt_emi_sync_write(EMI_APB_BASE+0x00000158,0xff0bff00);
mt_emi_sync_write(EMI_APB_BASE+0x00000400,0x00ff0001); //[27:20] enable monitor
mt_emi_sync_write(EMI_APB_BASE+0x0000071c,0x10000008);
mt_emi_sync_write(EMI_APB_BASE+0x00000800,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000820,0x24240101);
mt_emi_sync_write(EMI_APB_BASE+0x00000824,0x01012424);
mt_emi_sync_write(EMI_APB_BASE+0x00000828,0x50500101);
mt_emi_sync_write(EMI_APB_BASE+0x0000082c,0x01015050);
mt_emi_sync_write(EMI_APB_BASE+0x00000830,0x0fc39a30); // [6] MD_HRT_URGENT_MASK, if 1 -> mask MD_HRT_URGENT,
mt_emi_sync_write(EMI_APB_BASE+0x00000834,0x05050003);
mt_emi_sync_write(EMI_APB_BASE+0x00000838,0x254dffff);
mt_emi_sync_write(EMI_APB_BASE+0x0000083c,0x465a788c); //update
mt_emi_sync_write(EMI_APB_BASE+0x00000840,0x000003e8);
mt_emi_sync_write(EMI_APB_BASE+0x00000844,0x0000036b);
mt_emi_sync_write(EMI_APB_BASE+0x00000848,0x00000290);
mt_emi_sync_write(EMI_APB_BASE+0x0000084c,0x00000200);
mt_emi_sync_write(EMI_APB_BASE+0x00000850,0x00000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000854,0x00000000);
mt_emi_sync_write(EMI_APB_BASE+0x00000858,0x02531cff); //ignore rff threshold
mt_emi_sync_write(EMI_APB_BASE+0x0000085c,0x00002785);
mt_emi_sync_write(EMI_APB_BASE+0x00000874,0x000001b5);
mt_emi_sync_write(EMI_APB_BASE+0x00000878,0x003c0000); //update
mt_emi_sync_write(EMI_APB_BASE+0x0000087c,0x0255250d);
mt_emi_sync_write(EMI_APB_BASE+0x00000890,0xffff3c59);
mt_emi_sync_write(EMI_APB_BASE+0x00000894,0xffff00ff);
mt_emi_sync_write(EMI_APB_BASE+0x000008a0,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x000008a4,0x0000ffff);
mt_emi_sync_write(EMI_APB_BASE+0x000008c0,0x0000014b);
mt_emi_sync_write(EMI_APB_BASE+0x000008c4,0x002d0000); //update
mt_emi_sync_write(EMI_APB_BASE+0x000008c8,0x00000185);
mt_emi_sync_write(EMI_APB_BASE+0x000008cc,0x003c0000); //update
mt_emi_sync_write(EMI_APB_BASE+0x000008d0,0x00000185);
mt_emi_sync_write(EMI_APB_BASE+0x000008d4,0x003c0000); //update
mt_emi_sync_write(EMI_APB_BASE+0x000008e0,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x000008e4,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x000008e8,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000920,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000924,0x0000ffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000930,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000934,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000938,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x000009f0,0x41547082);
mt_emi_sync_write(EMI_APB_BASE+0x000009f4,0x38382a38);
mt_emi_sync_write(EMI_APB_BASE+0x000009f8,0x000001d4);
mt_emi_sync_write(EMI_APB_BASE+0x000009fc,0x00000190);
mt_emi_sync_write(EMI_APB_BASE+0x00000b00,0x0000012c);
mt_emi_sync_write(EMI_APB_BASE+0x00000b04,0x000000ed);
mt_emi_sync_write(EMI_APB_BASE+0x00000b08,0x000000c8);
mt_emi_sync_write(EMI_APB_BASE+0x00000b0c,0x00000096);
mt_emi_sync_write(EMI_APB_BASE+0x00000b10,0x000000c8);
mt_emi_sync_write(EMI_APB_BASE+0x00000b14,0x000000c8);
mt_emi_sync_write(EMI_APB_BASE+0x00000b28,0x26304048);
mt_emi_sync_write(EMI_APB_BASE+0x00000b2c,0x20201820);
mt_emi_sync_write(EMI_APB_BASE+0x00000b60,0x181e282f);
mt_emi_sync_write(EMI_APB_BASE+0x00000b64,0x14140f18);
mt_emi_sync_write(EMI_APB_BASE+0x00000b98,0x7496c8ea);
mt_emi_sync_write(EMI_APB_BASE+0x00000b9c,0x64644b64);
mt_emi_sync_write(EMI_APB_BASE+0x00000bd0,0x01010101);
mt_emi_sync_write(EMI_APB_BASE+0x00000bd4,0x01010101);
mt_emi_sync_write(EMI_APB_BASE+0x00000c08,0x7496c8ea); // 20190821 item3 - synced // TB D- 4266 may need changes
mt_emi_sync_write(EMI_APB_BASE+0x00000c0c,0x64644b64); // 20190821 item3 - synced // TB D- 4266 may need changes
mt_emi_sync_write(EMI_APB_BASE+0x00000c40,0x01010101);
mt_emi_sync_write(EMI_APB_BASE+0x00000c44,0x01010101);
mt_emi_sync_write(EMI_APB_BASE+0x00000c4c,0x300ff025); //ignore wff threshold
mt_emi_sync_write(EMI_APB_BASE+0x00000c80,0x000003e8);
mt_emi_sync_write(EMI_APB_BASE+0x00000c84,0x0000036b);
mt_emi_sync_write(EMI_APB_BASE+0x00000c88,0x00000290);
mt_emi_sync_write(EMI_APB_BASE+0x00000c8c,0x00000200);
mt_emi_sync_write(EMI_APB_BASE+0x00000c90,0x000001b5);
mt_emi_sync_write(EMI_APB_BASE+0x00000c94,0x0000014b);
mt_emi_sync_write(EMI_APB_BASE+0x00000c98,0x00000185);
mt_emi_sync_write(EMI_APB_BASE+0x00000c9c,0x00000185);
mt_emi_sync_write(EMI_APB_BASE+0x00000cb0,0x52698ca0);
mt_emi_sync_write(EMI_APB_BASE+0x00000cb4,0x46463546);
mt_emi_sync_write(EMI_APB_BASE+0x00000cf8,0x01010101);
mt_emi_sync_write(EMI_APB_BASE+0x00000cfc,0x01010101);
mt_emi_sync_write(EMI_APB_BASE+0x00000d04,0x00000009); //MDR shf0 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d0c,0x00000000); //MDR shf1 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d14,0x00730000); //MDR shf0
mt_emi_sync_write(EMI_APB_BASE+0x00000d18,0x00000808); //MDR shf1
mt_emi_sync_write(EMI_APB_BASE+0x00000d1c,0x00000028); //MDW shf0 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d24,0x00000000); //MDW shf1 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d2c,0x00730000); //MDW shf0
mt_emi_sync_write(EMI_APB_BASE+0x00000d30,0x00000808); //MDW shf1
mt_emi_sync_write(EMI_APB_BASE+0x00000d34,0x00000080); //APR shf0 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d3c,0x00000000); //APR shf1 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d44,0x30201008); //APR shf0/shf1
mt_emi_sync_write(EMI_APB_BASE+0x00000d48,0x00000800); //APW shf0 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d50,0x00000000); //APW shf1 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d58,0x00008000); //MMR shf0 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d60,0x00020000); //MMR shf1 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d64,0x00001000); //MMR shf1 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d68,0x00010000); //MMR shf2 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d6c,0x00000800); //MMR shf2 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d70,0x08080000); //MMR shf0
mt_emi_sync_write(EMI_APB_BASE+0x00000d74,0x00073030); //MMR shf1
mt_emi_sync_write(EMI_APB_BASE+0x00000d78,0x00040000); //MMW shf0 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d80,0x00100000); //MMW shf1 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d84,0x00004000); //MMW shf1 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d88,0x00080000); //MMW shf2 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d8c,0x00002000); //MMW shf2 event selet
mt_emi_sync_write(EMI_APB_BASE+0x00000d90,0x08080000); //MMW shf0
mt_emi_sync_write(EMI_APB_BASE+0x00000d94,0x00074040); //MMW shf1
mt_emi_sync_write(EMI_APB_BASE+0x00000d98,0x00400000); //MDHWR sh0 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000da0,0x00200000); //MDHWR sh1 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000da8,0x10100404); //MDHWWR sh
mt_emi_sync_write(EMI_APB_BASE+0x00000dac,0x01000000); //MDHWW sh0 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000db4,0x00800000); //MDHWW sh1 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000dbc,0x04000000); //GPUR sh0 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000dc4,0x02000000); //GPUR sh1 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000dcc,0x60602010); //GPUR
mt_emi_sync_write(EMI_APB_BASE+0x00000dd0,0x10000000); //GPUW sh0 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000dd8,0x08000000); //GPUW sh1 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000de0,0x00000009); //ARBR sh0 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000de8,0x04400080); //ARBR sh1 event select
mt_emi_sync_write(EMI_APB_BASE+0x00000df0,0x0f170f11); //ARB
mt_emi_sync_write(EMI_APB_BASE+0x00000df4,0x0303f7f7); //QOS control
mt_emi_sync_write(EMI_APB_BASE+0x00000e04,0x00000166);
mt_emi_sync_write(EMI_APB_BASE+0x00000e08,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000e0c,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000e14,0x00400166);
mt_emi_sync_write(EMI_APB_BASE+0x00000e18,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000e1c,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000e24,0x00000266);
mt_emi_sync_write(EMI_APB_BASE+0x00000e28,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000e2c,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000e34,0x00400266);
mt_emi_sync_write(EMI_APB_BASE+0x00000e38,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000e3c,0xffffffff);
// Added by Wei-Lun - START
// prtcl chker - golden setting
mt_emi_sync_write(EMI_APB_BASE+0x00000304,0xffffffff); // cyc
mt_emi_sync_write(EMI_APB_BASE+0x0000030c,0x001ffc85); // ctl
mt_emi_sync_write(EMI_APB_BASE+0x00000314,0xffffffff); // msk
mt_emi_sync_write(EMI_APB_BASE+0x0000034c,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000354,0x001ffc85);
mt_emi_sync_write(EMI_APB_BASE+0x0000035c,0xffffffff); // msk
mt_emi_sync_write(EMI_APB_BASE+0x00000394,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x0000039c,0x001ffc85);
mt_emi_sync_write(EMI_APB_BASE+0x000003a4,0xffffffff); // msk
mt_emi_sync_write(EMI_APB_BASE+0x000003d8,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x000003dc,0x001ffc85);
mt_emi_sync_write(EMI_APB_BASE+0x000003e0,0xffffffff); // msk
mt_emi_sync_write(EMI_APB_BASE+0x000003fc,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x0000040c,0x001ffc85);
mt_emi_sync_write(EMI_APB_BASE+0x00000414,0xffffffff); // msk
mt_emi_sync_write(EMI_APB_BASE+0x0000044c,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000454,0x001ffc85);
mt_emi_sync_write(EMI_APB_BASE+0x0000045c,0xffffffff); // msk
mt_emi_sync_write(EMI_APB_BASE+0x0000049c,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x000004a4,0x001ffc85);
mt_emi_sync_write(EMI_APB_BASE+0x000004ac,0xffffffff); // msk
mt_emi_sync_write(EMI_APB_BASE+0x0000050c,0xffffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000514,0x001ffc85);
mt_emi_sync_write(EMI_APB_BASE+0x0000051c,0xffffffff); // msk
// maxbw monitor - golden setting
// enable dbw0 cnter for max bw correlation (m3/4 no filters are enabled)
// Added by Wei-Lun - END
//weilun for new feature
mt_emi_sync_write(EMI_APB_BASE+0x00000714,0x00000000); // dvfs level setting for chn_em i rw switching shf
// cen_emi timeout value
mt_emi_sync_write(EMI_APB_BASE+0x00000628,0x60606060);
mt_emi_sync_write(EMI_APB_BASE+0x0000062c,0x60606060);
// fine-grained qos
mt_emi_sync_write(EMI_APB_BASE+0x00000050,0x00000000);
// ostd->bw
mt_emi_sync_write(EMI_APB_BASE+0x0000061c,0x08ffbbff);
mt_emi_sync_write(EMI_APB_BASE+0x00000624,0xffff5b3c);
mt_emi_sync_write(EMI_APB_BASE+0x00000774,0xffff00ff);
mt_emi_sync_write(EMI_APB_BASE+0x0000077c,0x00ffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000784,0xffff00ff);
mt_emi_sync_write(EMI_APB_BASE+0x0000078c,0x00ffffff);
mt_emi_sync_write(EMI_APB_BASE+0x00000958,0x00000000);
// hash rule
mt_emi_sync_write(EMI_APB_BASE+0x000007a4,0xC0000000);
}
static void emi_chn_config(void)
{
#ifdef RANK_512MB // => 2channel , dual rank , total=2G
mt_emi_sync_write(CHN0_EMI_BASE+0x00000000,0x0400a051);
#else //RANK_1G => 2channel , dual rank , total=4G
mt_emi_sync_write(CHN0_EMI_BASE+0x00000000,0x0400f051);
#endif
mt_emi_sync_write(CHN0_EMI_BASE+0x00000008,0x00ff6048);
mt_emi_sync_write(CHN0_EMI_BASE+0x00000010,0x00000004);
mt_emi_sync_write(CHN0_EMI_BASE+0x00000018,0x99f08c03);
mt_emi_sync_write(CHN0_EMI_BASE+0x00000710,0x9a508c17); // [24:20] = 0x2 : bank throttling (default=0x01f00000)
mt_emi_sync_write(CHN0_EMI_BASE+0x00000048,0x00038137); //RD_INORDER_THR[20:16]= 2
mt_emi_sync_write(CHN0_EMI_BASE+0x00000050,0x38460002); // [1] : MD_RD_AFT_WR_EN
mt_emi_sync_write(CHN0_EMI_BASE+0x00000058,0x00000000);
mt_emi_sync_write(CHN0_EMI_BASE+0x00000090,0x000002ff);
mt_emi_sync_write(CHN0_EMI_BASE+0x00000098,0x00003111); //mw2
mt_emi_sync_write(CHN0_EMI_BASE+0x00000140,0x22607188);
mt_emi_sync_write(CHN0_EMI_BASE+0x00000144,0x22607188);
mt_emi_sync_write(CHN0_EMI_BASE+0x00000148,0x3719595e); // chuan
mt_emi_sync_write(CHN0_EMI_BASE+0x0000014c,0x2719595e); // chuan
mt_emi_sync_write(CHN0_EMI_BASE+0x00000150,0x64f3ff79);
mt_emi_sync_write(CHN0_EMI_BASE+0x00000154,0x64f3ff79); // update timeout settin g: bit 12~15
mt_emi_sync_write(CHN0_EMI_BASE+0x00000158,0x011b0868);
// #ifdef SCN_ICFP
// mt_emi_sync_write(CHN0_EMI_BASE+0x0000015c,0x88410222); // Stop urgent read f irst when write command buffer remain < 8
// #else //SCN_UI
// mt_emi_sync_write(CHN0_EMI_BASE+0x0000015c,0x82410222); // Stop urgent read f irst when write command buffer remain < 2
// #endif
mt_emi_sync_write(CHN0_EMI_BASE+0x0000015c,0xa7414222); // Stop urgent read firs t when write command buffer remain < 7, [31] ultra_read_first, [30:28] wr_rsv_thr_l, [27: 24] wr_rsv_thr_h,
mt_emi_sync_write(CHN0_EMI_BASE+0x0000016c,0x0000f801);
mt_emi_sync_write(CHN0_EMI_BASE+0x00000170,0x40000000);
mt_emi_sync_write(CHN0_EMI_BASE+0x000001b0,0x000c802f); // Rank-Aware arbitration
mt_emi_sync_write(CHN0_EMI_BASE+0x000001b4,0xbd3f3f7e); // Rank-Aware arbitration
mt_emi_sync_write(CHN0_EMI_BASE+0x000001b8,0x7e003d7e); // Rank-Aware arbitration
mt_emi_sync_write(CHN0_EMI_BASE+0x000003fc,0x00000000); // Write M17_toggle_mask = 0
mt_emi_sync_write(CHN0_EMI_BASE+0x00000080,0xaa0148ff);
mt_emi_sync_write(CHN0_EMI_BASE+0x00000088,0xaa6168ff);
mt_emi_sync_write(CHN0_EMI_BASE+0x00000404,0xaa516cff);
mt_emi_sync_write(CHN0_EMI_BASE+0x00000408,0xaa0140ff);
mt_emi_sync_write(CHN0_EMI_BASE+0x0000040c,0x9f658633);
}
static void emi_sw_setting(void)
{
int emi_dcm;
/* Enable MPU violation interrupt to MD for D1 and D7 */
*((volatile unsigned int *)EMI_MPU_CTRL_D(1)) |= 0x10;
*((volatile unsigned int *)EMI_MPU_CTRL_D(7)) |= 0x10;
/* for DVFS BW monitor */
*((volatile unsigned int *) EMI_BWCT0) = 0x05008305;
*((volatile unsigned int *) EMI_BWCT0_6TH) = 0x08FF8705;
*((volatile unsigned int *) EMI_BWCT0_3RD) = 0x0DFF8A05;
*((volatile unsigned int *) EMI_THRO_CTRL1) |= 0x300;
#ifdef LAST_EMI
last_emi_info_ptr = (LAST_EMI_INFO_T *) get_dbg_info_base(KEY_LAST_EMI);
if (last_emi_info_ptr->isu_magic != LAST_EMI_MAGIC_PATTERN) {
last_emi_info_ptr->isu_magic = LAST_EMI_MAGIC_PATTERN;
last_emi_info_ptr->isu_version = 0xFFFFFFFF;
last_emi_info_ptr->isu_dram_type = 0;
last_emi_info_ptr->isu_diff_us = 0;
last_emi_info_ptr->os_flag_sspm = 0;
last_emi_info_ptr->os_flag_ap = 0;
}
emi_isu = atoi(dconfig_getenv("emi_isu"));
emi_log("[EMI DOE] emi_isu %d\n", emi_isu);
if (emi_isu == 1)
last_emi_info_ptr->isu_ctrl = 0xDECDDECD;
else if (emi_isu == 2)
last_emi_info_ptr->isu_ctrl = 0xDEC0DEC0;
else {
#if CFG_LAST_EMI_BW_DUMP
last_emi_info_ptr->isu_ctrl = 0xDECDDECD;
#else
last_emi_info_ptr->isu_ctrl = 0xDEC0DEC0;
#endif
}
#endif
*((volatile unsigned int *)0x10219858) |= 0x1 << 11;
emi_dcm = 0;//atoi(dconfig_getenv("emi_dcm"));
emi_log("[EMI DOE] emi_dcm %d\n", emi_dcm);
if (emi_dcm == 1) {
*((volatile unsigned int *)EMI_CONM) &= ~0xFF000000;
*((volatile unsigned int *)EMI_CONN) &= ~0xFF000000;
} else if (emi_dcm == 2) {
*((volatile unsigned int *)EMI_CONM) |= 0xFF000000;
*((volatile unsigned int *)EMI_CONN) |= 0xFF000000;
}
dsb();
}
void emi_init(void)
{
/* emi_config_lpddr4_2ch_golden_20191202_1000.c */
//Broadcast on
mt_emi_sync_write(INFRA_DRAMC_REG_CONFIG,0x0000007f);
emi_cen_config();
emi_chn_config();
//Broadcast off
mt_emi_sync_write(INFRA_DRAMC_REG_CONFIG,0x00000000);
}
void emi_init2(void)
{
unsigned int emi_temp_data;
//Broadcast on
mt_emi_sync_write(INFRA_DRAMC_REG_CONFIG, 0x0000007f);
mt_emi_sync_write_or(CHN0_EMI_BASE+0x00000010, 0x00000001); // [0] EMI enable
mt_emi_sync_write_or(EMI_BASE+0x00000060, 0x00000400); //[10] EMI enable
#ifdef MARGAUX_REAL_CHIP_EMI_GOLDEN_SETTING
mt_emi_sync_write_or(EMI_MPU_BASE+0x00000000,0x00000010); // [4] Disable emi_mpu_reg in terrupt
// Clear rank_arb_en
emi_temp_data = mt_emi_sync_read(CHN0_EMI_BASE+0x000001b0); // read ch0
emi_temp_data = emi_temp_data & ~(0x1);
mt_emi_sync_write(CHN0_EMI_BASE+0x000001b0, emi_temp_data); // broadcast to all channel
// auto-config rank_arb_en according to dual_rank_en setting
// assume all channel with same configuration
emi_temp_data = mt_emi_sync_read(CHN0_EMI_BASE+0x00000000); // read ch0
emi_temp_data = emi_temp_data & 0x1;
mt_emi_sync_write_or(CHN0_EMI_BASE+0x000001b0, emi_temp_data); // broadcast to a ll channel
// ----- from dcm_setting.c -----
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x100, 0xFFFFFFFF);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x104, 0xFFFFFFFF);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x108, 0xFFFFFFFF);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x10C, 0xFFFFFFFF);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x110, 0x01F00000);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x114, 0xC0040180);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x118, 0x00000000);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x11C, 0x00000003);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x120, 0x0C000000);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x124, 0x00C00000);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x128, 0x01F08000);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x12C, 0x00000000);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x130, 0x20003040);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x134, 0x00000000);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x138, 0x00001000);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x13C, 0x00000000);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x140, 0x10020F20);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x144, 0x00019000);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x148, 0x040A0818);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x14C, 0x00000370);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x150, 0xC001C080);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x154, 0x33000E01);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x158, 0x180067E1);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x15C, 0x000C008C);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x160, 0x020C0008);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x164, 0x0C00007E);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x168, 0x80050006);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x16C, 0x00030000);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x028, 0x0000000F);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x02C, 0x00000000);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x030, 0x001F0044);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x038, 0x200000FF);
mt_emi_sync_write_or(INFRACFG_AO_BASE+0x00000078, 0x08000000); // enable infra_local_cg
#ifdef MARGAUX_EMI_MP_SETTING
// Enable rdata_prty_gen & wdata_prty_chk
// emi bus parity workaround
emi_temp_data = mt_emi_sync_read(0x40000000);
mt_emi_sync_write(0x40000000, emi_temp_data);
emi_temp_data = mt_emi_sync_read(0x40000100);
mt_emi_sync_write(0x40000100, emi_temp_data);
emi_temp_data = mt_emi_sync_read(0x40000200);
mt_emi_sync_write(0x40000200, emi_temp_data);
emi_temp_data = mt_emi_sync_read(0x40000300);
mt_emi_sync_write(0x40000300, emi_temp_data);
mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00400000); // enable cen_emi parity (w)
mt_emi_sync_write_or(CHN0_EMI_BASE+0x00000050,0x00000004); // enable chn_emi par ity
/*TINFO="Enable APMCU Early CKE"*/
//mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, 0x00006000);
//emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x000007f4);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000007); // set disph_chn_en = 0x7
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000007); // set disph_chg_en = 0x1
/*TINFO="read emi_reg_pd then write apmcu config reg"*/
emi_temp_data = mt_emi_sync_read(INFRACFG_AO_MEM_BASE+0x050);
emi_temp_data = emi_temp_data & 0xf;
mt_emi_sync_write_or(EMI_BASE+0x07A4, emi_temp_data);
/*TINFO="Enable EMI wdata bus encode function"*/
mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00200000); // enable cen_emi wdata bus e ncode // *EMI_CONN |= (0x1 << 21);
mt_emi_sync_write_or(CHN0_EMI_BASE+0x00000050,0x00000010); // enable chn_emi wda ta bus encode // *CHN0_EMI_CHN_EMI_DFTC |= (0x1 <<4);
#else
// MP_dsim_v02 test (from v01) - all fr
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x028, 0x003F0000);
mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x02C, 0xA0000000);
#endif
#endif
mt_emi_sync_write(CHN0_EMI_BASE+0x0020, 0x00000040); // disable EBG
//Broadcast off
mt_emi_sync_write(INFRA_DRAMC_REG_CONFIG, 0x00000000);
emi_sw_setting();
}
int get_row_width_by_emi(unsigned int rank)
{
unsigned int emi_cona;
unsigned int shift_row, shift_ext;
int row_width;
if (rank == 0) {
shift_row = 12;
shift_ext = 22;
} else if (rank == 1) {
shift_row = 14;
shift_ext = 23;
} else
return -1;
emi_cona = mt_emi_sync_read(EMI_CONA);
row_width =
((emi_cona >> shift_row) & 0x3) |
((emi_cona >> shift_ext) & 0x4);
return (row_width + 13);
}
int get_channel_nr_by_emi(void)
{
int channel_nr;
channel_nr = 0x1 << ((mt_emi_sync_read(EMI_CONA) >> 8) & 0x3);
return channel_nr;
}
int get_rank_nr_by_emi(void)
{
unsigned int cen_emi_cona = mt_emi_sync_read(EMI_CONA);
if (cen_emi_cona & (0x3 << 16))
return 2;
else
return 1;
}
_Static_assert(DRAMC_MAX_RK > 1, "rank number is violated");
void get_rank_size_by_emi(unsigned long long dram_rank_size[DRAMC_MAX_RK])
{
unsigned int quad_ch_ratio;
unsigned long long ch0_rank0_size, ch0_rank1_size;
unsigned long long ch1_rank0_size, ch1_rank1_size;
unsigned int cen_emi_conh = mt_emi_sync_read(EMI_CONH);
unsigned long long dq_width;
dq_width = 2;
dram_rank_size[0] = 0;
dram_rank_size[1] = 0;
ch0_rank0_size = (cen_emi_conh >> 16) & 0xF;
ch0_rank1_size = (cen_emi_conh >> 20) & 0xF;
ch1_rank0_size = (cen_emi_conh >> 24) & 0xF;
ch1_rank1_size = (cen_emi_conh >> 28) & 0xF;
quad_ch_ratio = (get_rank_nr_by_emi() == 4)? 2 : 1;
ch0_rank0_size = (ch0_rank0_size * quad_ch_ratio) << 28;
ch0_rank1_size = (ch0_rank1_size * quad_ch_ratio) << 28;
ch1_rank0_size = (ch1_rank0_size * quad_ch_ratio) << 28;
ch1_rank1_size = (ch1_rank1_size * quad_ch_ratio) << 28;
if(ch0_rank0_size == 0) {
die("[EMI] undefined CONH for CH0 RANK0\n");
}
dram_rank_size[0] += ch0_rank0_size;
if (get_rank_nr_by_emi() > 1) {
if(ch0_rank1_size == 0) {
die("[EMI] undefined CONH for CH0 RANK1\n");
}
dram_rank_size[1] += ch0_rank1_size;
}
if(get_channel_nr_by_emi() > 1) {
if(ch1_rank0_size == 0) {
die("[EMI] undefined CONH for CH1 RANK0\n");
}
dram_rank_size[0] += ch1_rank0_size;
if (get_rank_nr_by_emi() > 1) {
if(ch1_rank1_size == 0) {
die("[EMI] undefined CONH for CH1 RANK1\n");
}
dram_rank_size[1] += ch1_rank1_size;
}
}
emi_log("DRAM rank0 size:0x%llx,\nDRAM rank1 size=0x%llx\n",
dram_rank_size[0], dram_rank_size[1]);
}
void set_cen_emi_cona(unsigned int cona_val)
{
mt_emi_sync_write(EMI_CONA, cona_val);
}
void set_cen_emi_conf(unsigned int conf_val)
{
mt_emi_sync_write(EMI_CONF, conf_val);
}
void set_cen_emi_conh(unsigned int conh_val)
{
mt_emi_sync_write(EMI_CONH, conh_val);
}
void set_chn_emi_cona(unsigned int cona_val)
{
mt_emi_sync_write(CHN_EMI_CONA(CHN0_EMI_BASE), cona_val);
mt_emi_sync_write(CHN_EMI_CONA(CHN1_EMI_BASE), cona_val);
}
void set_chn_emi_conc(unsigned int conc_val)
{
mt_emi_sync_write(CHN_EMI_CONC(CHN0_EMI_BASE), conc_val);
mt_emi_sync_write(CHN_EMI_CONC(CHN1_EMI_BASE), conc_val);
}
unsigned int get_cen_emi_cona(void)
{
return mt_emi_sync_read(EMI_CONA);
}
/* assume all chn emi setting are the same */
unsigned int get_chn_emi_cona(void)
{
unsigned int ch0_emi_cona;
ch0_emi_cona = mt_emi_sync_read(CHN0_EMI_BASE);
return ch0_emi_cona;
}
void phy_addr_to_dram_addr(dram_addr_t *dram_addr, unsigned long long phy_addr)
{
unsigned int cen_emi_cona, cen_emi_conf;
unsigned long long rank_size[DRAMC_MAX_RK];
unsigned int channel_num, rank_num;
unsigned int bit_scramble, bit_xor, bit_shift, channel_pos, channel_width;
unsigned int temp;
unsigned int index;
cen_emi_cona = mt_emi_sync_read(EMI_CONA);
cen_emi_conf = mt_emi_sync_read(EMI_CONF) >> 8;
get_rank_size_by_emi(rank_size);
rank_num = (unsigned int) get_rank_nr_by_emi();
channel_num = (unsigned int) get_channel_nr_by_emi();
phy_addr -= 0x40000000;
for (index = 0; index < rank_num; index++) {
if (phy_addr >= rank_size[index])
phy_addr -= rank_size[index];
else
break;
}
for (bit_scramble = 11; bit_scramble < 17; bit_scramble++) {
bit_xor = (cen_emi_conf >> (4 * (bit_scramble - 11))) & 0xf;
bit_xor &= phy_addr >> 16;
for (bit_shift = 0; bit_shift < 4; bit_shift++)
phy_addr ^= ((bit_xor>>bit_shift)&0x1) << bit_scramble;
}
if (channel_num > 1) {
channel_pos = ((cen_emi_cona >> 2) & 0x3) + 7;
for (channel_width = bit_shift = 0; bit_shift < 4; bit_shift++) {
if ((unsigned int)(1 << bit_shift) >= channel_num)
break;
channel_width++;
}
switch (channel_width) {
case 2:
dram_addr->addr = ((phy_addr & ~(((0x1 << 2) << channel_pos) - 1)) >> 2);
break;
default:
dram_addr->addr = ((phy_addr & ~(((0x1 << 1) << channel_pos) - 1)) >> 1);
break;
}
dram_addr->addr |= (phy_addr & ((0x1 << channel_pos) - 1));
}
temp = dram_addr->addr >> 1;
switch ((cen_emi_cona >> 4) & 0x3) {
case 0:
dram_addr->col = temp & 0x1FF;
temp = temp >> 9;
break;
case 1:
dram_addr->col = temp & 0x3FF;
temp = temp >> 10;
break;
case 2:
default:
dram_addr->col = temp & 0x7FF;
temp = temp >> 11;
break;
}
dram_addr->bk = temp & 0x7;
temp = temp >> 3;
dram_addr->row = temp;
emi_log("[EMI] ch%d, rk%d, dram addr: %x\n", dram_addr->ch, dram_addr->rk, dram_addr->addr);
emi_log("[EMI] bk%x, row%x, col%x\n", dram_addr->bk, dram_addr->row, dram_addr->col);
}
static unsigned int cen_emi_conh_backup = 0;
static unsigned int chn_emi_cona_backup = 0;
/* return the start address of rank1 */
unsigned int set_emi_before_rank1_mem_test(void)
{
cen_emi_conh_backup = mt_emi_sync_read(EMI_CONH);
chn_emi_cona_backup = get_chn_emi_cona();
if (get_rank_nr_by_emi() == 2) {
/* set the rank size to 1GB for 2 channels */
mt_emi_sync_write(EMI_CONH,
(cen_emi_conh_backup & 0x0000ffff) | 0x22220000);
set_chn_emi_cona(
(chn_emi_cona_backup & 0xff00ffff) | 0x00220000);
} else {
/* set the rank size to 1GB for 1 channel */
mt_emi_sync_write(EMI_CONH,
(cen_emi_conh_backup & 0x0000ffff) | 0x44440000);
set_chn_emi_cona(
(chn_emi_cona_backup & 0xff00ffff) | 0x00440000);
}
return 0x40000000;
}
void restore_emi_after_rank1_mem_test(void)
{
mt_emi_sync_write(EMI_CONH, cen_emi_conh_backup);
set_chn_emi_cona(chn_emi_cona_backup);
}
unsigned long long platform_memory_size(void)
{
static unsigned long long mem_size = 0;
int nr_rank;
int i;
unsigned long long rank_size[DRAMC_MAX_RK];
if (!mem_size) {
nr_rank = get_dram_rank_nr();
get_dram_rank_size(rank_size);
for (i = 0; i < nr_rank; i++)
mem_size += rank_size[i];
}
return mem_size;
}
size_t sdram_size(void)
{
int rank_num;
size_t dram_size = 0;
u64 rank_size[RANK_MAX];
get_rank_size_by_emi(rank_size);
rank_num = get_rank_nr_by_emi();
for (int i = 0; i < rank_num; i++)
dram_size += rank_size[i];
return dram_size;
}

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src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_AO.h Normal file
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src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_NAO.h Normal file
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src/vendorcode/mediatek/mt8192/include/addressmap.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef ADDRESSMAP_H
#define ADDRESSMAP_H
#include <soc/addressmap.h>
enum {
PWRAP_BASE = IO_PHYS + 0x00026000,
};
#endif

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src/vendorcode/mediatek/mt8192/include/custom_emi.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef __CUSTOM_EMI__
#define __CUSTOM_EMI__
#define __ETT__ 0
#include "dramc_pi_api.h"
#include "emi.h"
#define MT29VZZZBD9DQKPR
#ifdef MT29VZZZBD9DQKPR
EMI_SETTINGS default_emi_setting =
//MT29VZZZBD9DQKPR
{
0x1, /* sub_version */
0x0206, /* TYPE */
9, /* EMMC ID/FW ID checking length */
0, /* FW length */
{0x13,0x01,0x4E,0x53,0x30,0x4A,0x39,0x4D,0x39,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* NAND_EMMC_ID */
{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */
0x3530154, /* EMI_CONA_VAL */
0x66660033, /* EMI_CONH_VAL */
.DRAMC_ACTIME_UNION = {
0x00000000, /* U 00 */
0x00000000, /* U 01 */
0x00000000, /* U 02 */
0x00000000, /* U 03 */
0x00000000, /* U 04 */
0x00000000, /* U 05 */
0x00000000, /* U 06 */
0x00000000, /* U 07 */
},
{0xC0000000,0xC0000000,0,0}, /* DRAM RANK SIZE */
0x421000, /* EMI_CONF_VAL */
0x466005D, /* CHN0_EMI_CONA_VAL */
0x466005D, /* CHN1_EMI_CONA_VAL */
CBT_R0_R1_NORMAL, /* dram_cbt_mode_extern */
{0,0,0,0,0,0}, /* reserved 6 */
0x000000FF, /* LPDDR4X_MODE_REG5 */
0, /* PIN_MUX_TYPE for tablet */
};
#endif
EMI_SETTINGS emi_settings[] =
{
//H9HKNNNFBMMVAR - 4GB (2+2)
{
0x1, /* sub_version */
0x0006, /* TYPE */
0, /* EMMC ID/FW ID checking length */
0, /* FW length */
{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* NAND_EMMC_ID */
{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */
0xF053F154, /* EMI_CONA_VAL */
0x44440003, /* EMI_CONH_VAL */
.DRAMC_ACTIME_UNION = {
0x00000000, /* U 00 */
0x00000000, /* U 01 */
0x00000000, /* U 02 */
0x00000000, /* U 03 */
0x00000000, /* U 04 */
0x00000000, /* U 05 */
0x00000000, /* U 06 */
0x00000000, /* U 07 */
},
{0x80000000,0x80000000,0,0}, /* DRAM RANK SIZE */
0x421000, /* EMI_CONF_VAL */
0x444F051, /* CHN0_EMI_CONA_VAL */
0x444F051, /* CHN1_EMI_CONA_VAL */
CBT_R0_R1_NORMAL, /* dram_cbt_mode_extern */
{0,0,0,0,0,0}, /* reserved 6 */
0x00000006, /* LPDDR4X_MODE_REG5 */
0, /* PIN_MUX_TYPE for tablet */
} ,
//MT29VZZZBD9DQKPR - 6GB (3+3)
{
0x1, /* sub_version */
0x0206, /* TYPE */
9, /* EMMC ID/FW ID checking length */
0, /* FW length */
{0x13,0x01,0x4E,0x53,0x30,0x4A,0x39,0x4D,0x39,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* NAND_EMMC_ID */
{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */
0x3530154, /* EMI_CONA_VAL */
0x66660033, /* EMI_CONH_VAL */
.DRAMC_ACTIME_UNION = {
0x00000000, /* U 00 */
0x00000000, /* U 01 */
0x00000000, /* U 02 */
0x00000000, /* U 03 */
0x00000000, /* U 04 */
0x00000000, /* U 05 */
0x00000000, /* U 06 */
0x00000000, /* U 07 */
},
{0xC0000000,0xC0000000,0,0}, /* DRAM RANK SIZE */
0x421000, /* EMI_CONF_VAL */
0x466005D, /* CHN0_EMI_CONA_VAL */
0x466005D, /* CHN1_EMI_CONA_VAL */
CBT_R0_R1_NORMAL, /* dram_cbt_mode_extern */
{0,0,0,0,0,0}, /* reserved 6 */
0x000000FF, /* LPDDR4X_MODE_REG5 */
0, /* PIN_MUX_TYPE for tablet */
} ,
//H9HQ16AFAMMDAR / H9HCNNNFAMMLXR-NEE / K4UCE3Q4AA-MGCR - 8GB (4+4) Byte Mode
{
0x1, /* sub_version */
0x0306, /* TYPE */
14, /* EMMC ID/FW ID checking length */
0, /* FW length */
{0x48,0x39,0x48,0x51,0x31,0x36,0x41,0x46,0x41,0x4D,0x4D,0x44,0x41,0x52,0x0,0x0}, /* NAND_EMMC_ID */
{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */
0x3530154, /* EMI_CONA_VAL */
0x88880033, /* EMI_CONH_VAL */
.DRAMC_ACTIME_UNION = {
0x00000000, /* U 00 */
0x00000000, /* U 01 */
0x00000000, /* U 02 */
0x00000000, /* U 03 */
0x00000000, /* U 04 */
0x00000000, /* U 05 */
0x00000000, /* U 06 */
0x00000000, /* U 07 */
},
{0x100000000,0x100000000,0,0}, /* DRAM RANK SIZE */
0x421000, /* EMI_CONF_VAL */
0x488005D, /* CHN0_EMI_CONA_VAL */
0x488005D, /* CHN1_EMI_CONA_VAL */
CBT_R0_R1_BYTE, /* dram_cbt_mode_extern */
{0,0,0,0,0,0}, /* reserved 6 */
0x00000006, /* LPDDR4X_MODE_REG5 */
0, /* PIN_MUX_TYPE for tablet */
},
//MT29VZZZAD8GQFSL-046 - 4GB -Normal mode (4+0)
{
0x1, /* sub_version */
0x0006, /* TYPE */
0, /* EMMC ID/FW ID checking length */
0, /* FW length */
{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* NAND_EMMC_ID */
{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */
0x3500154, /* EMI_CONA_VAL */
0x88880033, /* EMI_CONH_VAL */
.DRAMC_ACTIME_UNION = {
0x00000000, /* U 00 */
0x00000000, /* U 01 */
0x00000000, /* U 02 */
0x00000000, /* U 03 */
0x00000000, /* U 04 */
0x00000000, /* U 05 */
0x00000000, /* U 06 */
0x00000000, /* U 07 */
},
{0x100000000,0,0,0}, /* DRAM RANK SIZE */
0x421000, /* EMI_CONF_VAL */
0x488005C, /* CHN0_EMI_CONA_VAL */
0x488005C, /* CHN1_EMI_CONA_VAL */
CBT_R0_R1_NORMAL, /* dram_cbt_mode_extern */
{0,0,0,0,0,0}, /* reserved 6 */
0x00000006, /* LPDDR4X_MODE_REG5 */
0, /* PIN_MUX_TYPE for tablet */
},
//KM2V8001CM_B707 - 6GB -byte mode (2+4)
{
0x1, /* sub_version */
0x0306, /* TYPE */
14, /* EMMC ID/FW ID checking length */
0, /* FW length */
{0x4b,0x4d,0x32,0x56,0x38,0x30,0x30,0x31,0x43,0x4d,0x2d,0x42,0x37,0x30,0x0,0x0}, /* NAND_EMMC_ID */
{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */
0x32533154, /* EMI_CONA_VAL */
0x84840023, /* EMI_CONH_VAL */
.DRAMC_ACTIME_UNION = {
0x00000000, /* U 00 */
0x00000000, /* U 01 */
0x00000000, /* U 02 */
0x00000000, /* U 03 */
0x00000000, /* U 04 */
0x00000000, /* U 05 */
0x00000000, /* U 06 */
0x00000000, /* U 07 */
},
{0x80000000,0x100000000,0,0}, /* DRAM RANK SIZE */
0x421000, /* EMI_CONF_VAL */
0x4843059, /* CHN0_EMI_CONA_VAL */
0x4843059, /* CHN1_EMI_CONA_VAL */
CBT_R0_NORMAL_R1_BYTE, /* dram_cbt_mode_extern */
{0,0,0,0,0,0}, /* reserved 6 */
0x00000001, /* LPDDR4X_MODE_REG5 */
0, /* PIN_MUX_TYPE for tablet */
} ,
//MT53E2G32D4 - 8GB (4+4) Normal Mode
{
0x1, /* sub_version */
0x0306, /* TYPE */
14, /* EMMC ID/FW ID checking length */
0, /* FW length */
{0x48,0x39,0x48,0x51,0x31,0x36,0x41,0x46,0x41,0x4D,0x4D,0x44,0x41,0x52,0x0,0x0}, /* NAND_EMMC_ID */
{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */
0x3530154, /* EMI_CONA_VAL */
0x88880033, /* EMI_CONH_VAL */
.DRAMC_ACTIME_UNION = {
0x00000000, /* U 00 */
0x00000000, /* U 01 */
0x00000000, /* U 02 */
0x00000000, /* U 03 */
0x00000000, /* U 04 */
0x00000000, /* U 05 */
0x00000000, /* U 06 */
0x00000000, /* U 07 */
},
{0x100000000,0x100000000,0,0}, /* DRAM RANK SIZE */
0x421000, /* EMI_CONF_VAL */
0x488005D, /* CHN0_EMI_CONA_VAL */
0x488005D, /* CHN1_EMI_CONA_VAL */
CBT_R0_R1_NORMAL, /* dram_cbt_mode_extern */
{0,0,0,0,0,0}, /* reserved 6 */
0x00000006, /* LPDDR4X_MODE_REG5 */
0, /* PIN_MUX_TYPE for tablet */
},
};
#define num_of_emi_records (sizeof(emi_settings) / sizeof(emi_settings[0]))
#endif /* __CUSTOM_EMI__ */

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src/vendorcode/mediatek/mt8192/include/ddrphy_nao_reg.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef __DDRPHY_NAO_REG_H__
#define __DDRPHY_NAO_REG_H__
/* ----------------- Register Definitions ------------------- */
#define MISC_STA_EXTLB0 0x00000000
#define MISC_STA_EXTLB0_STA_EXTLB_DONE GENMASK(31, 0)
#define MISC_STA_EXTLB1 0x00000004
#define MISC_STA_EXTLB1_STA_EXTLB_FAIL GENMASK(31, 0)
#define MISC_STA_EXTLB2 0x00000008
#define MISC_STA_EXTLB2_STA_EXTLB_DBG_INFO GENMASK(31, 0)
#define MISC_DQ_RXDLY_TRRO0 0x00000080
#define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LAG_CNT_OUT_B0 GENMASK(7, 0)
#define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LEAD_CNT_OUT_B0 GENMASK(15, 8)
#define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LAG_CNT_OUT_B1 GENMASK(23, 16)
#define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LEAD_CNT_OUT_B1 GENMASK(31, 24)
#define MISC_DQ_RXDLY_TRRO1 0x00000084
#define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LAG_CNT_OUT_B2 GENMASK(7, 0)
#define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LEAD_CNT_OUT_B2 GENMASK(15, 8)
#define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LAG_CNT_OUT_B3 GENMASK(23, 16)
#define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LEAD_CNT_OUT_B3 GENMASK(31, 24)
#define MISC_DQ_RXDLY_TRRO2 0x00000088
#define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LAG_CNT_OUT_B4 GENMASK(7, 0)
#define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LEAD_CNT_OUT_B4 GENMASK(15, 8)
#define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LAG_CNT_OUT_B5 GENMASK(23, 16)
#define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LEAD_CNT_OUT_B5 GENMASK(31, 24)
#define MISC_DQ_RXDLY_TRRO3 0x0000008c
#define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LAG_CNT_OUT_B6 GENMASK(7, 0)
#define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LEAD_CNT_OUT_B6 GENMASK(15, 8)
#define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LAG_CNT_OUT_B7 GENMASK(23, 16)
#define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LEAD_CNT_OUT_B7 GENMASK(31, 24)
#define MISC_DQ_RXDLY_TRRO4 0x00000090
#define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B0 GENMASK(7, 0)
#define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B1 GENMASK(15, 8)
#define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B2 GENMASK(23, 16)
#define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B3 GENMASK(31, 24)
#define MISC_DQ_RXDLY_TRRO5 0x00000094
#define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B4 GENMASK(7, 0)
#define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B5 GENMASK(15, 8)
#define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B6 GENMASK(23, 16)
#define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B7 GENMASK(31, 24)
#define MISC_DQ_RXDLY_TRRO6 0x00000098
#define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_SW_LAG_CNT_OUT_DQM0 GENMASK(7, 0)
#define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_SW_LEAD_CNT_OUT_DQM0 GENMASK(15, 8)
#define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_LEAD_LAG_CNT_OUT_DQM0 GENMASK(31, 24)
#define MISC_DQ_RXDLY_TRRO7 0x0000009c
#define MISC_DQ_RXDLY_TRRO7_DVS_RK0_B0_SW_UP_DONE BIT(0)
#define MISC_DQ_RXDLY_TRRO7_DVS_RK0_B1_SW_UP_DONE BIT(4)
#define MISC_DQ_RXDLY_TRRO7_DVS_RK1_B0_SW_UP_DONE BIT(8)
#define MISC_DQ_RXDLY_TRRO7_DVS_RK1_B1_SW_UP_DONE BIT(12)
#define MISC_DQ_RXDLY_TRRO7_DVS_RK2_B0_SW_UP_DONE BIT(16)
#define MISC_DQ_RXDLY_TRRO7_DVS_RK2_B1_SW_UP_DONE BIT(20)
#define MISC_DQ_RXDLY_TRRO8 0x000000a0
#define MISC_DQ_RXDLY_TRRO8_DVS_RKX_BX_TH_CNT_OUT_B0 GENMASK(8, 0)
#define MISC_DQ_RXDLY_TRRO8_DVS_RKX_BX_TH_CNT_OUT_B1 GENMASK(24, 16)
#define MISC_DQ_RXDLY_TRRO9 0x000000a4
#define MISC_DQ_RXDLY_TRRO9_DVS_RKX_BX_TH_CNT_OUT_B2 GENMASK(8, 0)
#define MISC_DQ_RXDLY_TRRO9_DVS_RKX_BX_TH_CNT_OUT_B3 GENMASK(24, 16)
#define MISC_DQ_RXDLY_TRRO10 0x000000a8
#define MISC_DQ_RXDLY_TRRO10_DVS_RKX_BX_TH_CNT_OUT_B4 GENMASK(8, 0)
#define MISC_DQ_RXDLY_TRRO10_DVS_RKX_BX_TH_CNT_OUT_B5 GENMASK(24, 16)
#define MISC_DQ_RXDLY_TRRO11 0x000000ac
#define MISC_DQ_RXDLY_TRRO11_DVS_RKX_BX_TH_CNT_OUT_B6 GENMASK(8, 0)
#define MISC_DQ_RXDLY_TRRO11_DVS_RKX_BX_TH_CNT_OUT_B7 GENMASK(24, 16)
#define MISC_DQ_RXDLY_TRRO12 0x000000b0
#define MISC_DQ_RXDLY_TRRO12_DVS_RKX_BX_TH_CNT_OUT_DQM0 GENMASK(8, 0)
#define MISC_DQ_RXDLY_TRRO13 0x000000b4
#define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQX_B0_R_DLY GENMASK(5, 0)
#define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQS0_R_DLY GENMASK(14, 8)
#define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQX_B1_R_DLY GENMASK(21, 16)
#define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQS1_R_DLY GENMASK(30, 24)
#define MISC_DQ_RXDLY_TRRO14 0x000000b8
#define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQX_B0_R_DLY GENMASK(5, 0)
#define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQS0_R_DLY GENMASK(14, 8)
#define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQX_B1_R_DLY GENMASK(21, 16)
#define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQS1_R_DLY GENMASK(30, 24)
#define MISC_DQ_RXDLY_TRRO15 0x000000bc
#define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQX_B0_R_DLY GENMASK(5, 0)
#define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQS0_R_DLY GENMASK(14, 8)
#define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQX_B1_R_DLY GENMASK(21, 16)
#define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQS1_R_DLY GENMASK(30, 24)
#define MISC_DQ_RXDLY_TRRO16 0x000000c0
#define MISC_DQ_RXDLY_TRRO16_DVS_RXDLY_STS_ERR_CNT_ALL GENMASK(31, 0)
#define MISC_DQ_RXDLY_TRRO17 0x000000c4
#define MISC_DQ_RXDLY_TRRO17_DVS_RXDLY_STS_ERR_CNT_ALL_47_32 GENMASK(15, 0)
#define MISC_DQ_RXDLY_TRRO17_PBYTE_LEADLAG_STUCK_B0 BIT(16)
#define MISC_DQ_RXDLY_TRRO17_PBYTE_LEADLAG_STUCK_B1 BIT(24)
#define MISC_DQ_RXDLY_TRRO18 0x000000c8
#define MISC_DQ_RXDLY_TRRO18_RXDLY_DBG_MON_VALID BIT(0)
#define MISC_DQ_RXDLY_TRRO18_RXDLY_RK0_FAIL_LAT BIT(1)
#define MISC_DQ_RXDLY_TRRO18_RXDLY_RK1_FAIL_LAT BIT(2)
#define MISC_DQ_RXDLY_TRRO18_RXDLY_RK2_FAIL_LAT BIT(3)
#define MISC_DQ_RXDLY_TRRO18_DFS_SHU_GP_FAIL_LAT GENMASK(5, 4)
#define MISC_DQ_RXDLY_TRRO19 0x000000cc
#define MISC_DQ_RXDLY_TRRO19_RESERVED_0X00C GENMASK(31, 0)
#define MISC_DQ_RXDLY_TRRO20 0x000000d0
#define MISC_DQ_RXDLY_TRRO20_RESERVED_0X0D0 GENMASK(31, 0)
#define MISC_DQ_RXDLY_TRRO21 0x000000d4
#define MISC_DQ_RXDLY_TRRO21_RESERVED_0X0D4 GENMASK(31, 0)
#define MISC_DQ_RXDLY_TRRO22 0x000000d8
#define MISC_DQ_RXDLY_TRRO22_RESERVED_0X0D8 GENMASK(31, 0)
#define MISC_DQ_RXDLY_TRRO23 0x000000dc
#define MISC_DQ_RXDLY_TRRO23_RESERVED_0X0DC GENMASK(31, 0)
#define MISC_DQ_RXDLY_TRRO24 0x000000e0
#define MISC_DQ_RXDLY_TRRO24_RESERVED_0X0E0 GENMASK(31, 0)
#define MISC_DQ_RXDLY_TRRO25 0x000000e4
#define MISC_DQ_RXDLY_TRRO25_RESERVED_0X0E4 GENMASK(31, 0)
#define MISC_DQ_RXDLY_TRRO26 0x000000e8
#define MISC_DQ_RXDLY_TRRO26_RESERVED_0X0E8 GENMASK(31, 0)
#define MISC_DQ_RXDLY_TRRO27 0x000000ec
#define MISC_DQ_RXDLY_TRRO27_RESERVED_0X0EC GENMASK(31, 0)
#define MISC_DQ_RXDLY_TRRO28 0x000000f0
#define MISC_DQ_RXDLY_TRRO28_RESERVED_0X0F0 GENMASK(31, 0)
#define MISC_DQ_RXDLY_TRRO29 0x000000f4
#define MISC_DQ_RXDLY_TRRO29_RESERVED_0X0F4 GENMASK(31, 0)
#define MISC_DQ_RXDLY_TRRO30 0x000000f8
#define MISC_DQ_RXDLY_TRRO30_RESERVED_0X0F8 GENMASK(31, 0)
#define MISC_DQ_RXDLY_TRRO31 0x000000fc
#define MISC_DQ_RXDLY_TRRO31_RESERVED_0X0FC GENMASK(31, 0)
#define MISC_CA_RXDLY_TRRO0 0x00000100
#define MISC_CA_RXDLY_TRRO0_DVS_RKX_CA_SW_LAG_CNT_OUT_CA0 GENMASK(7, 0)
#define MISC_CA_RXDLY_TRRO0_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA0 GENMASK(15, 8)
#define MISC_CA_RXDLY_TRRO0_DVS_RKX_CA_SW_LAG_CNT_OUT_CA1 GENMASK(23, 16)
#define MISC_CA_RXDLY_TRRO0_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA1 GENMASK(31, 24)
#define MISC_CA_RXDLY_TRRO1 0x00000104
#define MISC_CA_RXDLY_TRRO1_DVS_RKX_CA_SW_LAG_CNT_OUT_CA2 GENMASK(7, 0)
#define MISC_CA_RXDLY_TRRO1_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA2 GENMASK(15, 8)
#define MISC_CA_RXDLY_TRRO1_DVS_RKX_CA_SW_LAG_CNT_OUT_CA3 GENMASK(23, 16)
#define MISC_CA_RXDLY_TRRO1_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA3 GENMASK(31, 24)
#define MISC_CA_RXDLY_TRRO2 0x00000108
#define MISC_CA_RXDLY_TRRO2_DVS_RKX_CA_SW_LAG_CNT_OUT_CA4 GENMASK(7, 0)
#define MISC_CA_RXDLY_TRRO2_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA4 GENMASK(15, 8)
#define MISC_CA_RXDLY_TRRO2_DVS_RKX_CA_SW_LAG_CNT_OUT_CA5 GENMASK(23, 16)
#define MISC_CA_RXDLY_TRRO2_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA5 GENMASK(31, 24)
#define MISC_CA_RXDLY_TRRO3 0x0000010c
#define MISC_CA_RXDLY_TRRO3_DVS_RKX_CA_SW_LAG_CNT_OUT_CKE0 GENMASK(7, 0)
#define MISC_CA_RXDLY_TRRO3_DVS_RKX_CA_SW_LEAD_CNT_OUT_CKE0 GENMASK(15, 8)
#define MISC_CA_RXDLY_TRRO3_DVS_RKX_CA_SW_LAG_CNT_OUT_CKE1 GENMASK(23, 16)
#define MISC_CA_RXDLY_TRRO3_DVS_RKX_CA_SW_LEAD_CNT_OUT_CKE1 GENMASK(31, 24)
#define MISC_CA_RXDLY_TRRO4 0x00000110
#define MISC_CA_RXDLY_TRRO4_DVS_RKX_CA_SW_LAG_CNT_OUT_CKE2 GENMASK(7, 0)
#define MISC_CA_RXDLY_TRRO4_DVS_RKX_CA_SW_LEAD_CNT_OUT_CKE2 GENMASK(15, 8)
#define MISC_CA_RXDLY_TRRO4_DVS_RKX_CA_SW_LAG_CNT_OUT_CS0 GENMASK(23, 16)
#define MISC_CA_RXDLY_TRRO4_DVS_RKX_CA_SW_LEAD_CNT_OUT_CS0 GENMASK(31, 24)
#define MISC_CA_RXDLY_TRRO5 0x00000114
#define MISC_CA_RXDLY_TRRO5_DVS_RKX_CA_SW_LAG_CNT_OUT_CS1 GENMASK(7, 0)
#define MISC_CA_RXDLY_TRRO5_DVS_RKX_CA_SW_LEAD_CNT_OUT_CS1 GENMASK(15, 8)
#define MISC_CA_RXDLY_TRRO5_DVS_RKX_CA_SW_LAG_CNT_OUT_CS2 GENMASK(23, 16)
#define MISC_CA_RXDLY_TRRO5_DVS_RKX_CA_SW_LEAD_CNT_OUT_CS2 GENMASK(31, 24)
#define MISC_CA_RXDLY_TRRO6 0x00000118
#define MISC_CA_RXDLY_TRRO6_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA0 GENMASK(7, 0)
#define MISC_CA_RXDLY_TRRO6_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA1 GENMASK(15, 8)
#define MISC_CA_RXDLY_TRRO6_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA2 GENMASK(23, 16)
#define MISC_CA_RXDLY_TRRO6_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA3 GENMASK(31, 24)
#define MISC_CA_RXDLY_TRRO7 0x0000011c
#define MISC_CA_RXDLY_TRRO7_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA4 GENMASK(7, 0)
#define MISC_CA_RXDLY_TRRO7_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA5 GENMASK(15, 8)
#define MISC_CA_RXDLY_TRRO7_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CKE0 GENMASK(23, 16)
#define MISC_CA_RXDLY_TRRO7_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CKE1 GENMASK(31, 24)
#define MISC_CA_RXDLY_TRRO8 0x00000120
#define MISC_CA_RXDLY_TRRO8_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CKE2 GENMASK(7, 0)
#define MISC_CA_RXDLY_TRRO8_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CS0 GENMASK(15, 8)
#define MISC_CA_RXDLY_TRRO8_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CS1 GENMASK(23, 16)
#define MISC_CA_RXDLY_TRRO8_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CS2 GENMASK(31, 24)
#define MISC_CA_RXDLY_TRRO9 0x00000124
#define MISC_CA_RXDLY_TRRO9_DVS_RK0_CA_SW_UP_DONE BIT(0)
#define MISC_CA_RXDLY_TRRO9_DVS_RK1_CA_SW_UP_DONE BIT(8)
#define MISC_CA_RXDLY_TRRO9_DVS_RK2_CA_SW_UP_DONE BIT(16)
#define MISC_CA_RXDLY_TRRO10 0x00000128
#define MISC_CA_RXDLY_TRRO10_DVS_RKX_CA_TH_CNT_OUT_CA0 GENMASK(8, 0)
#define MISC_CA_RXDLY_TRRO10_DVS_RKX_CA_TH_CNT_OUT_CA1 GENMASK(24, 16)
#define MISC_CA_RXDLY_TRRO11 0x0000012c
#define MISC_CA_RXDLY_TRRO11_DVS_RKX_CA_TH_CNT_OUT_CA2 GENMASK(8, 0)
#define MISC_CA_RXDLY_TRRO11_DVS_RKX_CA_TH_CNT_OUT_CA3 GENMASK(24, 16)
#define MISC_CA_RXDLY_TRRO12 0x00000130
#define MISC_CA_RXDLY_TRRO12_DVS_RKX_CA_TH_CNT_OUT_CA4 GENMASK(8, 0)
#define MISC_CA_RXDLY_TRRO12_DVS_RKX_CA_TH_CNT_OUT_CA5 GENMASK(24, 16)
#define MISC_CA_RXDLY_TRRO13 0x00000134
#define MISC_CA_RXDLY_TRRO13_DVS_RKX_CA_TH_CNT_OUT_CKE0 GENMASK(8, 0)
#define MISC_CA_RXDLY_TRRO13_DVS_RKX_CA_TH_CNT_OUT_CKE1 GENMASK(24, 16)
#define MISC_CA_RXDLY_TRRO14 0x00000138
#define MISC_CA_RXDLY_TRRO14_DVS_RKX_CA_TH_CNT_OUT_CKE2 GENMASK(8, 0)
#define MISC_CA_RXDLY_TRRO14_DVS_RKX_CA_TH_CNT_OUT_CS0 GENMASK(24, 16)
#define MISC_CA_RXDLY_TRRO15 0x0000013c
#define MISC_CA_RXDLY_TRRO15_DVS_RKX_CA_TH_CNT_OUT_CS1 GENMASK(8, 0)
#define MISC_CA_RXDLY_TRRO15_DVS_RKX_CA_TH_CNT_OUT_CS2 GENMASK(24, 16)
#define MISC_CA_RXDLY_TRRO16 0x00000140
#define MISC_CA_RXDLY_TRRO16_DA_RK0_CAX_CA_R_DLY GENMASK(5, 0)
#define MISC_CA_RXDLY_TRRO16_DA_RK0_CLK_R_DLY GENMASK(15, 8)
#define MISC_CA_RXDLY_TRRO17 0x00000144
#define MISC_CA_RXDLY_TRRO17_DA_RK1_CAX_CA_R_DLY GENMASK(5, 0)
#define MISC_CA_RXDLY_TRRO17_DA_RK1_CLK_R_DLY GENMASK(15, 8)
#define MISC_CA_RXDLY_TRRO18 0x00000148
#define MISC_CA_RXDLY_TRRO18_DA_RK2_CAX_CA_R_DLY GENMASK(5, 0)
#define MISC_CA_RXDLY_TRRO18_DA_RK2_CLK_R_DLY GENMASK(15, 8)
#define MISC_CA_RXDLY_TRRO19 0x0000014c
#define MISC_CA_RXDLY_TRRO19_DVS_RXDLY_STS_ERR_CNT_ALL_CA GENMASK(23, 0)
#define MISC_CA_RXDLY_TRRO19_PBYTE_LEADLAG_STUCK_CA BIT(24)
#define MISC_CA_RXDLY_TRRO20 0x00000150
#define MISC_CA_RXDLY_TRRO20_RESERVED_0X150 GENMASK(31, 0)
#define MISC_CA_RXDLY_TRRO21 0x00000154
#define MISC_CA_RXDLY_TRRO21_RESERVED_0X154 GENMASK(31, 0)
#define MISC_CA_RXDLY_TRRO22 0x00000158
#define MISC_CA_RXDLY_TRRO22_RESERVED_0X158 GENMASK(31, 0)
#define MISC_CA_RXDLY_TRRO23 0x0000015c
#define MISC_CA_RXDLY_TRRO23_RESERVED_0X15C GENMASK(31, 0)
#define MISC_CA_RXDLY_TRRO24 0x00000160
#define MISC_CA_RXDLY_TRRO24_RESERVED_0X160 GENMASK(31, 0)
#define MISC_CA_RXDLY_TRRO25 0x00000164
#define MISC_CA_RXDLY_TRRO25_RESERVED_0X164 GENMASK(31, 0)
#define MISC_CA_RXDLY_TRRO26 0x00000168
#define MISC_CA_RXDLY_TRRO26_RESERVED_0X168 GENMASK(31, 0)
#define MISC_CA_RXDLY_TRRO27 0x0000016c
#define MISC_CA_RXDLY_TRRO27_RESERVED_0X16C GENMASK(31, 0)
#define MISC_CA_RXDLY_TRRO28 0x00000170
#define MISC_CA_RXDLY_TRRO28_RESERVED_0X170 GENMASK(31, 0)
#define MISC_CA_RXDLY_TRRO29 0x00000174
#define MISC_CA_RXDLY_TRRO29_RESERVED_0X174 GENMASK(31, 0)
#define MISC_CA_RXDLY_TRRO30 0x00000178
#define MISC_CA_RXDLY_TRRO30_RESERVED_0X178 GENMASK(31, 0)
#define MISC_CA_RXDLY_TRRO31 0x0000017c
#define MISC_CA_RXDLY_TRRO31_RESERVED_0X17C GENMASK(31, 0)
#define MISC_DQO1 0x00000180
#define MISC_DQO1_DQO1_RO GENMASK(31, 0)
#define MISC_CAO1 0x00000184
#define MISC_CAO1_RA0_O1 BIT(0)
#define MISC_CAO1_RA1_O1 BIT(1)
#define MISC_CAO1_RA2_O1 BIT(2)
#define MISC_CAO1_RA3_O1 BIT(3)
#define MISC_CAO1_RA4_O1 BIT(4)
#define MISC_CAO1_RA5_O1 BIT(5)
#define MISC_CAO1_RA6_O1 BIT(6)
#define MISC_CAO1_RA7_O1 BIT(7)
#define MISC_CAO1_RA8_O1 BIT(8)
#define MISC_CAO1_RA9_O1 BIT(9)
#define MISC_CAO1_CKEO1_RO BIT(10)
#define MISC_CAO1_CKE1O1_RO BIT(11)
#define MISC_CAO1_CKE2O1_RO BIT(12)
#define MISC_CAO1_CSO1_RO BIT(13)
#define MISC_CAO1_CS1O1_RO BIT(14)
#define MISC_CAO1_CS2O1_RO BIT(15)
#define MISC_CAO1_RESETO1_RO BIT(16)
#define MISC_CAO1_DQM0O1_RO BIT(24)
#define MISC_CAO1_DQM1O1_RO BIT(25)
#define MISC_CAO1_DQM2O1_RO BIT(26)
#define MISC_CAO1_DQM3O1_RO BIT(27)
#define MISC_AD_RX_DQ_O1 0x00000188
#define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B0 GENMASK(7, 0)
#define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B0_BIT2 BIT(2)//[2:2] //francis added
#define MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B0 BIT(8)
#define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B1 GENMASK(23, 16)
#define MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B1 BIT(24)
#define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B1_BIT2 BIT(18)//[18:18] //francis added
#define MISC_AD_RX_CMD_O1 0x0000018c
#define MISC_AD_RX_CMD_O1_AD_RX_ARCA0_O1 BIT(0)
#define MISC_AD_RX_CMD_O1_AD_RX_ARCA1_O1 BIT(1)
#define MISC_AD_RX_CMD_O1_AD_RX_ARCA2_O1 BIT(2)
#define MISC_AD_RX_CMD_O1_AD_RX_ARCA3_O1 BIT(3)
#define MISC_AD_RX_CMD_O1_AD_RX_ARCA4_O1 BIT(4)
#define MISC_AD_RX_CMD_O1_AD_RX_ARCA5_O1 BIT(5)
#define MISC_AD_RX_CMD_O1_AD_RX_ARCA6_O1 BIT(6)
#define MISC_AD_RX_CMD_O1_AD_RX_ARCA7_O1 BIT(7)
#define MISC_AD_RX_CMD_O1_AD_RX_ARCA8_O1 BIT(8)
#define MISC_AD_RX_CMD_O1_AD_RX_ARCA9_O1 BIT(9)
#define MISC_AD_RX_CMD_O1_AD_RX_ARCKE0_O1 BIT(10)
#define MISC_AD_RX_CMD_O1_AD_RX_ARCKE1_O1 BIT(11)
#define MISC_AD_RX_CMD_O1_AD_RX_ARCKE2_O1 BIT(12)
#define MISC_AD_RX_CMD_O1_AD_RX_ARCS0_O1 BIT(13)
#define MISC_AD_RX_CMD_O1_AD_RX_ARCS1_O1 BIT(14)
#define MISC_AD_RX_CMD_O1_AD_RX_ARCS2_O1 BIT(15)
#define MISC_PHY_RGS_DQ 0x00000190
#define MISC_PHY_RGS_DQ_RGS_ARDQ_OFFSET_FLAG_B0 GENMASK(7, 0)
#define MISC_PHY_RGS_DQ_RGS_ARDQM0_OFFSET_FLAG_B0 BIT(8)
#define MISC_PHY_RGS_DQ_RGS_RX_ARDQS0_RDY_EYE_B0 BIT(9)
#define MISC_PHY_RGS_DQ_RGS_ARDQ_OFFSET_FLAG_B1 GENMASK(23, 16)
#define MISC_PHY_RGS_DQ_RGS_ARDQM0_OFFSET_FLAG_B1 BIT(24)
#define MISC_PHY_RGS_DQ_RGS_RX_ARDQS0_RDY_EYE_B1 BIT(25)
#define MISC_PHY_RGS_DQ_DA_RPHYPLLGP_CK_SEL BIT(31)
#define MISC_PHY_RGS_CMD 0x00000194
#define MISC_PHY_RGS_CMD_RGS_ARCA0_OFFSET_FLAG BIT(0)
#define MISC_PHY_RGS_CMD_RGS_ARCA1_OFFSET_FLAG BIT(1)
#define MISC_PHY_RGS_CMD_RGS_ARCA2_OFFSET_FLAG BIT(2)
#define MISC_PHY_RGS_CMD_RGS_ARCA3_OFFSET_FLAG BIT(3)
#define MISC_PHY_RGS_CMD_RGS_ARCA4_OFFSET_FLAG BIT(4)
#define MISC_PHY_RGS_CMD_RGS_ARCA5_OFFSET_FLAG BIT(5)
#define MISC_PHY_RGS_CMD_RGS_ARCA6_OFFSET_FLAG BIT(6)
#define MISC_PHY_RGS_CMD_RGS_ARCA7_OFFSET_FLAG BIT(7)
#define MISC_PHY_RGS_CMD_RGS_ARCA8_OFFSET_FLAG BIT(8)
#define MISC_PHY_RGS_CMD_RGS_ARCA9_OFFSET_FLAG BIT(9)
#define MISC_PHY_RGS_CMD_RGS_ARCKE0_OFFSET_FLAG BIT(10)
#define MISC_PHY_RGS_CMD_RGS_ARCKE1_OFFSET_FLAG BIT(11)
#define MISC_PHY_RGS_CMD_RGS_ARCKE2_OFFSET_FLAG BIT(12)
#define MISC_PHY_RGS_CMD_RGS_ARCS0_OFFSET_FLAG BIT(13)
#define MISC_PHY_RGS_CMD_RGS_ARCS1_OFFSET_FLAG BIT(14)
#define MISC_PHY_RGS_CMD_RGS_ARCS2_OFFSET_FLAG BIT(15)
#define MISC_PHY_RGS_CMD_RGS_RX_ARCLK_RDY_EYE BIT(16)
#define MISC_PHY_RGS_CMD_RGS_RIMPCALOUT BIT(24)
#define MISC_PHY_RGS_STBEN_B0 0x00000198
#define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQ0_STBEN_B0 GENMASK(7, 0)
#define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQ4_STBEN_B0 GENMASK(15, 8)
#define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LEAD_B0 BIT(16)
#define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LAG_B0 BIT(17)
#define MISC_PHY_RGS_STBEN_B0_AD_ARDLL_PD_EN_B0 BIT(18)
#define MISC_PHY_RGS_STBEN_B0_AD_ARDLL_MON_B0 GENMASK(31, 24)
#define MISC_PHY_RGS_STBEN_B1 0x0000019c
#define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQ0_STBEN_B1 GENMASK(7, 0)
#define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQ4_STBEN_B1 GENMASK(15, 8)
#define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LEAD_B1 BIT(16)
#define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LAG_B1 BIT(17)
#define MISC_PHY_RGS_STBEN_B1_AD_ARDLL_PD_EN_B1 BIT(18)
#define MISC_PHY_RGS_STBEN_B1_AD_ARDLL_MON_B1 GENMASK(31, 24)
#define MISC_PHY_RGS_STBEN_CMD 0x000001a0
#define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCA0_STBEN GENMASK(7, 0)
#define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCA4_STBEN GENMASK(15, 8)
#define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LEAD BIT(16)
#define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LAG BIT(17)
#define MISC_PHY_RGS_STBEN_CMD_AD_ARDLL_PD_EN_CA BIT(18)
#define MISC_PHY_RGS_STBEN_CMD_AD_ARDLL_MON_CA GENMASK(31, 24)
#define MISC_STA_TOGLB0 0x000001a4
#define MISC_STA_TOGLB0_STA_TOGLB_DONE GENMASK(31, 0)
#define MISC_STA_TOGLB1 0x000001a8
#define MISC_STA_TOGLB1_STA_TOGLB_FAIL GENMASK(31, 0)
#define MISC_STA_TOGLB2 0x000001ac
#define MISC_STA_TOGLB2_STA_TOGLB_PUHI_TIMEOUT GENMASK(31, 0)
#define MISC_STA_TOGLB3 0x000001b0
#define MISC_STA_TOGLB3_STA_TOGLB_PULO_TIMEOUT GENMASK(31, 0)
#define MISC_FT_STATUS_0 0x000001b4
#define MISC_FT_STATUS_0_AD_RX_ARDQ_DVS_R_LAG_B1 GENMASK(7, 0)
#define MISC_FT_STATUS_0_AD_RX_ARDQ_DVS_R_LEAD_B1 GENMASK(15, 8)
#define MISC_FT_STATUS_0_AD_RX_ARDQ_DVS_R_LAG_B0 GENMASK(23, 16)
#define MISC_FT_STATUS_0_AD_RX_ARDQ_DVS_R_LEAD_B0 GENMASK(31, 24)
#define MISC_FT_STATUS_1 0x000001b8
#define MISC_FT_STATUS_1_AD_RX_ARDQ_DVS_F_LAG_B1 GENMASK(7, 0)
#define MISC_FT_STATUS_1_AD_RX_ARDQ_DVS_F_LEAD_B1 GENMASK(15, 8)
#define MISC_FT_STATUS_1_AD_RX_ARDQ_DVS_F_LAG_B0 GENMASK(23, 16)
#define MISC_FT_STATUS_1_AD_RX_ARDQ_DVS_F_LEAD_B0 GENMASK(31, 24)
#define MISC_FT_STATUS_2 0x000001bc
#define MISC_FT_STATUS_2_AD_RRESETB_O BIT(0)
#define MISC_FT_STATUS_3 0x000001c0
#define MISC_FT_STATUS_3_AD_RX_ARCA0_DVS_R_LAG BIT(0)
#define MISC_FT_STATUS_3_AD_RX_ARCA1_DVS_R_LAG BIT(1)
#define MISC_FT_STATUS_3_AD_RX_ARCA2_DVS_R_LAG BIT(2)
#define MISC_FT_STATUS_3_AD_RX_ARCA3_DVS_R_LAG BIT(3)
#define MISC_FT_STATUS_3_AD_RX_ARCA4_DVS_R_LAG BIT(4)
#define MISC_FT_STATUS_3_AD_RX_ARCA5_DVS_R_LAG BIT(5)
#define MISC_FT_STATUS_3_AD_RX_ARCKE0_DVS_R_LAG BIT(6)
#define MISC_FT_STATUS_3_AD_RX_ARCKE1_DVS_R_LAG BIT(7)
#define MISC_FT_STATUS_3_AD_RX_ARCS0_DVS_R_LAG BIT(8)
#define MISC_FT_STATUS_3_AD_RX_ARCS1_DVS_R_LAG BIT(9)
#define MISC_FT_STATUS_3_AD_RX_ARCA0_DVS_R_LEAD BIT(16)
#define MISC_FT_STATUS_3_AD_RX_ARCA1_DVS_R_LEAD BIT(17)
#define MISC_FT_STATUS_3_AD_RX_ARCA2_DVS_R_LEAD BIT(18)
#define MISC_FT_STATUS_3_AD_RX_ARCA3_DVS_R_LEAD BIT(19)
#define MISC_FT_STATUS_3_AD_RX_ARCA4_DVS_R_LEAD BIT(20)
#define MISC_FT_STATUS_3_AD_RX_ARCA5_DVS_R_LEAD BIT(21)
#define MISC_FT_STATUS_3_AD_RX_ARCKE0_DVS_R_LEAD BIT(22)
#define MISC_FT_STATUS_3_AD_RX_ARCKE1_DVS_R_LEAD BIT(23)
#define MISC_FT_STATUS_3_AD_RX_ARCS0_DVS_R_LEAD BIT(24)
#define MISC_FT_STATUS_3_AD_RX_ARCS1_DVS_R_LEAD BIT(25)
#define MISC_FT_STATUS_4 0x000001c4
#define MISC_FT_STATUS_4_AD_RX_ARCA0_DVS_F_LAG BIT(0)
#define MISC_FT_STATUS_4_AD_RX_ARCA1_DVS_F_LAG BIT(1)
#define MISC_FT_STATUS_4_AD_RX_ARCA2_DVS_F_LAG BIT(2)
#define MISC_FT_STATUS_4_AD_RX_ARCA3_DVS_F_LAG BIT(3)
#define MISC_FT_STATUS_4_AD_RX_ARCA4_DVS_F_LAG BIT(4)
#define MISC_FT_STATUS_4_AD_RX_ARCA5_DVS_F_LAG BIT(5)
#define MISC_FT_STATUS_4_AD_RX_ARCKE0_DVS_F_LAG BIT(6)
#define MISC_FT_STATUS_4_AD_RX_ARCKE1_DVS_F_LAG BIT(7)
#define MISC_FT_STATUS_4_AD_RX_ARCS0_DVS_F_LAG BIT(8)
#define MISC_FT_STATUS_4_AD_RX_ARCS1_DVS_F_LAG BIT(9)
#define MISC_FT_STATUS_4_AD_RX_ARCA0_DVS_F_LEAD BIT(16)
#define MISC_FT_STATUS_4_AD_RX_ARCA1_DVS_F_LEAD BIT(17)
#define MISC_FT_STATUS_4_AD_RX_ARCA2_DVS_F_LEAD BIT(18)
#define MISC_FT_STATUS_4_AD_RX_ARCA3_DVS_F_LEAD BIT(19)
#define MISC_FT_STATUS_4_AD_RX_ARCA4_DVS_F_LEAD BIT(20)
#define MISC_FT_STATUS_4_AD_RX_ARCA5_DVS_F_LEAD BIT(21)
#define MISC_FT_STATUS_4_AD_RX_ARCKE0_DVS_F_LEAD BIT(22)
#define MISC_FT_STATUS_4_AD_RX_ARCKE1_DVS_F_LEAD BIT(23)
#define MISC_FT_STATUS_4_AD_RX_ARCS0_DVS_F_LEAD BIT(24)
#define MISC_FT_STATUS_4_AD_RX_ARCS1_DVS_F_LEAD BIT(25)
#define MISC_STA_EXTLB_DBG0 0x000001c8
#define MISC_STA_EXTLB_DBG0_STA_EXTLB_DVS_LEAD_0TO1 GENMASK(31, 0)
#define MISC_STA_EXTLB_DBG1 0x000001cc
#define MISC_STA_EXTLB_DBG1_STA_EXTLB_DVS_LEAD_1TO0 GENMASK(31, 0)
#define MISC_STA_EXTLB_DBG2 0x000001d0
#define MISC_STA_EXTLB_DBG2_STA_EXTLB_DVS_LAG_0TO1 GENMASK(31, 0)
#define MISC_STA_EXTLB_DBG3 0x000001d4
#define MISC_STA_EXTLB_DBG3_STA_EXTLB_DVS_LAG_1TO0 GENMASK(31, 0)
#endif /*__DDRPHY_NAO_REG_H__*/

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src/vendorcode/mediatek/mt8192/include/ddrphy_pll_reg.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef __DDRPHY_PLL_REG_H__
#define __DDRPHY_PLL_REG_H__
/* ----------------- Register Definitions ------------------- */
#define PLL1 0x00000000
#define PLL1_RG_RPHYPLL_SDM_SSC_EN BIT(2)
#define PLL1_RG_RPHYPLL_EN BIT(31)
#define PLL2 0x00000004
#define PLL2_RG_RCLRPLL_SDM_SSC_EN BIT(2)
#define PLL2_RG_RCLRPLL_EN BIT(31)
#define PLL3 0x00000008
#define PLL3_RG_RPHYPLL_TSTOP_EN BIT(0)
#define PLL3_RG_RPHYPLL_TSTOD_EN BIT(1)
#define PLL3_RG_RPHYPLL_TSTFM_EN BIT(2)
#define PLL3_RG_RPHYPLL_TSTCK_EN BIT(3)
#define PLL3_RG_RPHYPLL_TST_EN BIT(4)
#define PLL3_RG_RPHYPLL_TSTLVROD_EN BIT(5)
#define PLL3_RG_RPHYPLL_TST_SEL GENMASK(11, 8)
#define PLL4 0x0000000c
#define PLL4_RG_RPHYPLL_RESETB BIT(16)
#define PLL4_RG_RPHYPLL_ATPG_EN BIT(17)
#define PLL4_RG_RPHYPLL_MCK8X_SEL BIT(18)
#define PLL4_PLL4_RFU BIT(19)
#define PLL4_RG_RPHYPLL_SER_MODE BIT(20)
#define PLL4_RG_RPHYPLL_AD_MCK8X_EN BIT(21)
#define PLL4_RG_RPHYPLL_ADA_MCK8X_EN BIT(22)
#define PLL4_RESERVED_0X0C BIT(24)
#define PLL5 0x00000010
#define PLL5_RESERVED_0X010 GENMASK(31, 0)
#define PLL6 0x00000014
#define PLL6_RESERVED_0X014 GENMASK(31, 0)
#define PLL7 0x00000018
#define PLL7_RESERVED_0X018 GENMASK(31, 0)
#define PLL8 0x0000001c
#define PLL8_RESERVED_0X01C GENMASK(31, 0)
#define PLL9 0x00000020
#define PLL9_RESERVED_0X020 GENMASK(31, 0)
#define PLL10 0x00000024
#define PLL10_RESERVED_0X024 GENMASK(31, 0)
#define PLL11 0x00000028
#define PLL11_RESERVED_0X028 GENMASK(31, 0)
#define PLL12 0x0000002c
#define PLL12_RESERVED_0X02C GENMASK(31, 0)
#define PLL13 0x00000030
#define PLL13_RESERVED_0X030 GENMASK(31, 0)
#define PLL14 0x00000034
#define PLL14_RESERVED_0X034 GENMASK(31, 0)
#define PLL15 0x00000038
#define PLL15_RESERVED_0X038 GENMASK(31, 0)
#define PLL16 0x0000003c
#define PLL16_RESERVED_0X03C GENMASK(31, 0)
#define SHU1_PLL0 0x00000d80
#define SHU1_PLL0_RG_RPHYPLL_TOP_REV GENMASK(15, 0)
#define SHU1_PLL0_RG_RPHYPLL_LOAD_EN BIT(19)
#define SHU1_PLL1 0x00000d84
#define SHU1_PLL1_RG_RPHYPLLGP_CK_SEL BIT(0)
#define SHU1_PLL1_SHU1_PLL1_RFU GENMASK(3, 1)
#define SHU1_PLL1_R_SHU_AUTO_PLL_MUX BIT(4)
#define SHU1_PLL1_RESERVED_0XD84 GENMASK(31, 5)
#define SHU1_PLL2 0x00000d88
#define SHU1_PLL2_RG_RCLRPLL_LOAD_EN BIT(19)
#define SHU1_PLL3 0x00000d8c
#define SHU1_PLL3_RESERVED_0XD8C GENMASK(31, 0)
#define SHU1_PLL4 0x00000d90
#define SHU1_PLL4_RG_RPHYPLL_RESERVED GENMASK(15, 0)
#define SHU1_PLL4_RG_RPHYPLL_FS GENMASK(19, 18)
#define SHU1_PLL4_RG_RPHYPLL_BW GENMASK(22, 20)
#define SHU1_PLL4_RG_RPHYPLL_ICHP GENMASK(25, 24)
#define SHU1_PLL4_RG_RPHYPLL_IBIAS GENMASK(27, 26)
#define SHU1_PLL4_RG_RPHYPLL_BLP BIT(29)
#define SHU1_PLL4_RG_RPHYPLL_BR BIT(30)
#define SHU1_PLL4_RG_RPHYPLL_BP BIT(31)
#define SHU1_PLL5 0x00000d94
#define SHU1_PLL5_RG_RPHYPLL_SDM_FRA_EN BIT(0)
#define SHU1_PLL5_RG_RPHYPLL_SDM_PCW_CHG BIT(1)
#define SHU1_PLL5_RG_RPHYPLL_SDM_PCW GENMASK(31, 16)
#define SHU1_PLL6 0x00000d98
#define SHU1_PLL6_RG_RCLRPLL_RESERVED GENMASK(15, 0)
#define SHU1_PLL6_RG_RCLRPLL_FS GENMASK(19, 18)
#define SHU1_PLL6_RG_RCLRPLL_BW GENMASK(22, 20)
#define SHU1_PLL6_RG_RCLRPLL_ICHP GENMASK(25, 24)
#define SHU1_PLL6_RG_RCLRPLL_IBIAS GENMASK(27, 26)
#define SHU1_PLL6_RG_RCLRPLL_BLP BIT(29)
#define SHU1_PLL6_RG_RCLRPLL_BR BIT(30)
#define SHU1_PLL6_RG_RCLRPLL_BP BIT(31)
#define SHU1_PLL7 0x00000d9c
#define SHU1_PLL7_RG_RCLRPLL_SDM_FRA_EN BIT(0)
#define SHU1_PLL7_RG_RCLRPLL_SDM_PCW_CHG BIT(1)
#define SHU1_PLL7_RG_RCLRPLL_SDM_PCW GENMASK(31, 16)
#define SHU1_PLL8 0x00000da0
#define SHU1_PLL8_RG_RPHYPLL_POSDIV GENMASK(2, 0)
#define SHU1_PLL8_RG_RPHYPLL_PREDIV GENMASK(19, 18)
#define SHU1_PLL9 0x00000da4
#define SHU1_PLL9_RG_RPHYPLL_RST_DLY GENMASK(9, 8)
#define SHU1_PLL9_RG_RPHYPLL_LVROD_EN BIT(12)
#define SHU1_PLL9_RG_RPHYPLL_MONREF_EN BIT(13)
#define SHU1_PLL9_RG_RPHYPLL_MONVC_EN GENMASK(15, 14)
#define SHU1_PLL9_RG_RPHYPLL_MONCK_EN BIT(16)
#define SHU1_PLL10 0x00000da8
#define SHU1_PLL10_RG_RCLRPLL_POSDIV GENMASK(2, 0)
#define SHU1_PLL10_RG_RCLRPLL_PREDIV GENMASK(19, 18)
#define SHU1_PLL11 0x00000dac
#define SHU1_PLL11_RG_RCLRPLL_RST_DLY GENMASK(9, 8)
#define SHU1_PLL11_RG_RCLRPLL_LVROD_EN BIT(12)
#define SHU1_PLL11_RG_RCLRPLL_MONREF_EN BIT(13)
#define SHU1_PLL11_RG_RCLRPLL_MONVC_EN GENMASK(15, 14)
#define SHU1_PLL11_RG_RCLRPLL_MONCK_EN BIT(16)
#define SHU1_PLL12 0x00000db0
#define SHU1_PLL12_RG_RCLRPLL_EXT_PODIV GENMASK(5, 0)
#define SHU1_PLL12_RG_RCLRPLL_BYPASS BIT(6)
#define SHU1_PLL12_RG_RCLRPLL_EXTPODIV_EN BIT(7)
#define SHU1_PLL12_RG_RCLRPLL_EXT_FBDIV GENMASK(13, 8)
#define SHU1_PLL12_RG_RCLRPLL_EXTFBDIV_EN BIT(15)
#define SHU1_PLL12_RG_RPHYPLL_EXT_FBDIV GENMASK(21, 16)
#define SHU1_PLL12_RG_RPHYPLL_EXTFBDIV_EN BIT(22)
#define SHU1_PLL13 0x00000db4
#define SHU1_PLL13_RG_RCLRPLL_FB_DL GENMASK(5, 0)
#define SHU1_PLL13_RG_RCLRPLL_REF_DL GENMASK(13, 8)
#define SHU1_PLL13_RG_RPHYPLL_FB_DL GENMASK(21, 16)
#define SHU1_PLL13_RG_RPHYPLL_REF_DL GENMASK(29, 24)
#define SHU1_PLL14 0x00000db8
#define SHU1_PLL14_RG_RPHYPLL_SDM_HREN BIT(0)
#define SHU1_PLL14_RG_RPHYPLL_SDM_SSC_PH_INIT BIT(1)
#define SHU1_PLL14_RG_RPHYPLL_SDM_SSC_PRD GENMASK(31, 16)
#define SHU1_PLL15 0x00000dbc
#define SHU1_PLL15_RG_RPHYPLL_SDM_SSC_DELTA GENMASK(15, 0)
#define SHU1_PLL15_RG_RPHYPLL_SDM_SSC_DELTA1 GENMASK(31, 16)
#define SHU1_PLL20 0x00000dd0
#define SHU1_PLL20_RG_RCLRPLL_SDM_HREN BIT(0)
#define SHU1_PLL20_RG_RCLRPLL_SDM_SSC_PH_INIT BIT(1)
#define SHU1_PLL20_RG_RCLRPLL_SDM_SSC_PRD GENMASK(31, 16)
#define SHU1_PLL21 0x00000dd4
#define SHU1_PLL21_RG_RCLRPLL_SDM_SSC_DELTA GENMASK(15, 0)
#define SHU1_PLL21_RG_RCLRPLL_SDM_SSC_DELTA1 GENMASK(31, 16)
#define SHU2_PLL0 0x00001280
#define SHU2_PLL0_RG_RPHYPLL_TOP_REV GENMASK(15, 0)
#define SHU2_PLL0_RG_RPHYPLL_LOAD_EN BIT(19)
#define SHU2_PLL1 0x00001284
#define SHU2_PLL1_RG_RPHYPLLGP_CK_SEL BIT(0)
#define SHU2_PLL1_SHU2_PLL1_RFU GENMASK(3, 1)
#define SHU2_PLL1_R_SHU_AUTO_PLL_MUX BIT(4)
#define SHU2_PLL1_RESERVED_0X1284 GENMASK(31, 5)
#define SHU2_PLL2 0x00001288
#define SHU2_PLL2_RG_RCLRPLL_LOAD_EN BIT(19)
#define SHU2_PLL3 0x0000128c
#define SHU2_PLL3_RESERVED_0X128C GENMASK(31, 0)
#define SHU2_PLL4 0x00001290
#define SHU2_PLL4_RG_RPHYPLL_RESERVED GENMASK(15, 0)
#define SHU2_PLL4_RG_RPHYPLL_FS GENMASK(19, 18)
#define SHU2_PLL4_RG_RPHYPLL_BW GENMASK(22, 20)
#define SHU2_PLL4_RG_RPHYPLL_ICHP GENMASK(25, 24)
#define SHU2_PLL4_RG_RPHYPLL_IBIAS GENMASK(27, 26)
#define SHU2_PLL4_RG_RPHYPLL_BLP BIT(29)
#define SHU2_PLL4_RG_RPHYPLL_BR BIT(30)
#define SHU2_PLL4_RG_RPHYPLL_BP BIT(31)
#define SHU2_PLL5 0x00001294
#define SHU2_PLL5_RG_RPHYPLL_SDM_FRA_EN BIT(0)
#define SHU2_PLL5_RG_RPHYPLL_SDM_PCW_CHG BIT(1)
#define SHU2_PLL5_RG_RPHYPLL_SDM_PCW GENMASK(31, 16)
#define SHU2_PLL6 0x00001298
#define SHU2_PLL6_RG_RCLRPLL_RESERVED GENMASK(15, 0)
#define SHU2_PLL6_RG_RCLRPLL_FS GENMASK(19, 18)
#define SHU2_PLL6_RG_RCLRPLL_BW GENMASK(22, 20)
#define SHU2_PLL6_RG_RCLRPLL_ICHP GENMASK(25, 24)
#define SHU2_PLL6_RG_RCLRPLL_IBIAS GENMASK(27, 26)
#define SHU2_PLL6_RG_RCLRPLL_BLP BIT(29)
#define SHU2_PLL6_RG_RCLRPLL_BR BIT(30)
#define SHU2_PLL6_RG_RCLRPLL_BP BIT(31)
#define SHU2_PLL7 0x0000129c
#define SHU2_PLL7_RG_RCLRPLL_SDM_FRA_EN BIT(0)
#define SHU2_PLL7_RG_RCLRPLL_SDM_PCW_CHG BIT(1)
#define SHU2_PLL7_RG_RCLRPLL_SDM_PCW GENMASK(31, 16)
#define SHU2_PLL8 0x000012a0
#define SHU2_PLL8_RG_RPHYPLL_POSDIV GENMASK(2, 0)
#define SHU2_PLL8_RG_RPHYPLL_PREDIV GENMASK(19, 18)
#define SHU2_PLL9 0x000012a4
#define SHU2_PLL9_RG_RPHYPLL_RST_DLY GENMASK(9, 8)
#define SHU2_PLL9_RG_RPHYPLL_LVROD_EN BIT(12)
#define SHU2_PLL9_RG_RPHYPLL_MONREF_EN BIT(13)
#define SHU2_PLL9_RG_RPHYPLL_MONVC_EN GENMASK(15, 14)
#define SHU2_PLL9_RG_RPHYPLL_MONCK_EN BIT(16)
#define SHU2_PLL10 0x000012a8
#define SHU2_PLL10_RG_RCLRPLL_POSDIV GENMASK(2, 0)
#define SHU2_PLL10_RG_RCLRPLL_PREDIV GENMASK(19, 18)
#define SHU2_PLL11 0x000012ac
#define SHU2_PLL11_RG_RCLRPLL_RST_DLY GENMASK(9, 8)
#define SHU2_PLL11_RG_RCLRPLL_LVROD_EN BIT(12)
#define SHU2_PLL11_RG_RCLRPLL_MONREF_EN BIT(13)
#define SHU2_PLL11_RG_RCLRPLL_MONVC_EN GENMASK(15, 14)
#define SHU2_PLL11_RG_RCLRPLL_MONCK_EN BIT(16)
#define SHU2_PLL12 0x000012b0
#define SHU2_PLL12_RG_RCLRPLL_EXT_PODIV GENMASK(5, 0)
#define SHU2_PLL12_RG_RCLRPLL_BYPASS BIT(6)
#define SHU2_PLL12_RG_RCLRPLL_EXTPODIV_EN BIT(7)
#define SHU2_PLL12_RG_RCLRPLL_EXT_FBDIV GENMASK(13, 8)
#define SHU2_PLL12_RG_RCLRPLL_EXTFBDIV_EN BIT(15)
#define SHU2_PLL12_RG_RPHYPLL_EXT_FBDIV GENMASK(21, 16)
#define SHU2_PLL12_RG_RPHYPLL_EXTFBDIV_EN BIT(22)
#define SHU2_PLL13 0x000012b4
#define SHU2_PLL13_RG_RCLRPLL_FB_DL GENMASK(5, 0)
#define SHU2_PLL13_RG_RCLRPLL_REF_DL GENMASK(13, 8)
#define SHU2_PLL13_RG_RPHYPLL_FB_DL GENMASK(21, 16)
#define SHU2_PLL13_RG_RPHYPLL_REF_DL GENMASK(29, 24)
#define SHU2_PLL14 0x000012b8
#define SHU2_PLL14_RG_RPHYPLL_SDM_HREN BIT(0)
#define SHU2_PLL14_RG_RPHYPLL_SDM_SSC_PH_INIT BIT(1)
#define SHU2_PLL14_RG_RPHYPLL_SDM_SSC_PRD GENMASK(31, 16)
#define SHU2_PLL15 0x000012bc
#define SHU2_PLL15_RG_RPHYPLL_SDM_SSC_DELTA GENMASK(15, 0)
#define SHU2_PLL15_RG_RPHYPLL_SDM_SSC_DELTA1 GENMASK(31, 16)
#define SHU2_PLL20 0x000012d0
#define SHU2_PLL20_RG_RCLRPLL_SDM_HREN BIT(0)
#define SHU2_PLL20_RG_RCLRPLL_SDM_SSC_PH_INIT BIT(1)
#define SHU2_PLL20_RG_RCLRPLL_SDM_SSC_PRD GENMASK(31, 16)
#define SHU2_PLL21 0x000012d4
#define SHU2_PLL21_RG_RCLRPLL_SDM_SSC_DELTA GENMASK(15, 0)
#define SHU2_PLL21_RG_RCLRPLL_SDM_SSC_DELTA1 GENMASK(31, 16)
#define SHU3_PLL0 0x00001780
#define SHU3_PLL0_RG_RPHYPLL_TOP_REV GENMASK(15, 0)
#define SHU3_PLL0_RG_RPHYPLL_LOAD_EN BIT(19)
#define SHU3_PLL1 0x00001784
#define SHU3_PLL1_RG_RPHYPLLGP_CK_SEL BIT(0)
#define SHU3_PLL1_SHU3_PLL1_RFU GENMASK(3, 1)
#define SHU3_PLL1_R_SHU_AUTO_PLL_MUX BIT(4)
#define SHU3_PLL1_RESERVED_0X1784 GENMASK(31, 5)
#define SHU3_PLL2 0x00001788
#define SHU3_PLL2_RG_RCLRPLL_LOAD_EN BIT(19)
#define SHU3_PLL3 0x0000178c
#define SHU3_PLL3_RESERVED_0X178C GENMASK(31, 0)
#define SHU3_PLL4 0x00001790
#define SHU3_PLL4_RG_RPHYPLL_RESERVED GENMASK(15, 0)
#define SHU3_PLL4_RG_RPHYPLL_FS GENMASK(19, 18)
#define SHU3_PLL4_RG_RPHYPLL_BW GENMASK(22, 20)
#define SHU3_PLL4_RG_RPHYPLL_ICHP GENMASK(25, 24)
#define SHU3_PLL4_RG_RPHYPLL_IBIAS GENMASK(27, 26)
#define SHU3_PLL4_RG_RPHYPLL_BLP BIT(29)
#define SHU3_PLL4_RG_RPHYPLL_BR BIT(30)
#define SHU3_PLL4_RG_RPHYPLL_BP BIT(31)
#define SHU3_PLL5 0x00001794
#define SHU3_PLL5_RG_RPHYPLL_SDM_FRA_EN BIT(0)
#define SHU3_PLL5_RG_RPHYPLL_SDM_PCW_CHG BIT(1)
#define SHU3_PLL5_RG_RPHYPLL_SDM_PCW GENMASK(31, 16)
#define SHU3_PLL6 0x00001798
#define SHU3_PLL6_RG_RCLRPLL_RESERVED GENMASK(15, 0)
#define SHU3_PLL6_RG_RCLRPLL_FS GENMASK(19, 18)
#define SHU3_PLL6_RG_RCLRPLL_BW GENMASK(22, 20)
#define SHU3_PLL6_RG_RCLRPLL_ICHP GENMASK(25, 24)
#define SHU3_PLL6_RG_RCLRPLL_IBIAS GENMASK(27, 26)
#define SHU3_PLL6_RG_RCLRPLL_BLP BIT(29)
#define SHU3_PLL6_RG_RCLRPLL_BR BIT(30)
#define SHU3_PLL6_RG_RCLRPLL_BP BIT(31)
#define SHU3_PLL7 0x0000179c
#define SHU3_PLL7_RG_RCLRPLL_SDM_FRA_EN BIT(0)
#define SHU3_PLL7_RG_RCLRPLL_SDM_PCW_CHG BIT(1)
#define SHU3_PLL7_RG_RCLRPLL_SDM_PCW GENMASK(31, 16)
#define SHU3_PLL8 0x000017a0
#define SHU3_PLL8_RG_RPHYPLL_POSDIV GENMASK(2, 0)
#define SHU3_PLL8_RG_RPHYPLL_PREDIV GENMASK(19, 18)
#define SHU3_PLL9 0x000017a4
#define SHU3_PLL9_RG_RPHYPLL_RST_DLY GENMASK(9, 8)
#define SHU3_PLL9_RG_RPHYPLL_LVROD_EN BIT(12)
#define SHU3_PLL9_RG_RPHYPLL_MONREF_EN BIT(13)
#define SHU3_PLL9_RG_RPHYPLL_MONVC_EN GENMASK(15, 14)
#define SHU3_PLL9_RG_RPHYPLL_MONCK_EN BIT(16)
#define SHU3_PLL10 0x000017a8
#define SHU3_PLL10_RG_RCLRPLL_POSDIV GENMASK(2, 0)
#define SHU3_PLL10_RG_RCLRPLL_PREDIV GENMASK(19, 18)
#define SHU3_PLL11 0x000017ac
#define SHU3_PLL11_RG_RCLRPLL_RST_DLY GENMASK(9, 8)
#define SHU3_PLL11_RG_RCLRPLL_LVROD_EN BIT(12)
#define SHU3_PLL11_RG_RCLRPLL_MONREF_EN BIT(13)
#define SHU3_PLL11_RG_RCLRPLL_MONVC_EN GENMASK(15, 14)
#define SHU3_PLL11_RG_RCLRPLL_MONCK_EN BIT(16)
#define SHU3_PLL12 0x000017b0
#define SHU3_PLL12_RG_RCLRPLL_EXT_PODIV GENMASK(5, 0)
#define SHU3_PLL12_RG_RCLRPLL_BYPASS BIT(6)
#define SHU3_PLL12_RG_RCLRPLL_EXTPODIV_EN BIT(7)
#define SHU3_PLL12_RG_RCLRPLL_EXT_FBDIV GENMASK(13, 8)
#define SHU3_PLL12_RG_RCLRPLL_EXTFBDIV_EN BIT(15)
#define SHU3_PLL12_RG_RPHYPLL_EXT_FBDIV GENMASK(21, 16)
#define SHU3_PLL12_RG_RPHYPLL_EXTFBDIV_EN BIT(22)
#define SHU3_PLL13 0x000017b4
#define SHU3_PLL13_RG_RCLRPLL_FB_DL GENMASK(5, 0)
#define SHU3_PLL13_RG_RCLRPLL_REF_DL GENMASK(13, 8)
#define SHU3_PLL13_RG_RPHYPLL_FB_DL GENMASK(21, 16)
#define SHU3_PLL13_RG_RPHYPLL_REF_DL GENMASK(29, 24)
#define SHU3_PLL14 0x000017b8
#define SHU3_PLL14_RG_RPHYPLL_SDM_HREN BIT(0)
#define SHU3_PLL14_RG_RPHYPLL_SDM_SSC_PH_INIT BIT(1)
#define SHU3_PLL14_RG_RPHYPLL_SDM_SSC_PRD GENMASK(31, 16)
#define SHU3_PLL15 0x000017bc
#define SHU3_PLL15_RG_RPHYPLL_SDM_SSC_DELTA GENMASK(15, 0)
#define SHU3_PLL15_RG_RPHYPLL_SDM_SSC_DELTA1 GENMASK(31, 16)
#define SHU3_PLL20 0x000017d0
#define SHU3_PLL20_RG_RCLRPLL_SDM_HREN BIT(0)
#define SHU3_PLL20_RG_RCLRPLL_SDM_SSC_PH_INIT BIT(1)
#define SHU3_PLL20_RG_RCLRPLL_SDM_SSC_PRD GENMASK(31, 16)
#define SHU3_PLL21 0x000017d4
#define SHU3_PLL21_RG_RCLRPLL_SDM_SSC_DELTA GENMASK(15, 0)
#define SHU3_PLL21_RG_RCLRPLL_SDM_SSC_DELTA1 GENMASK(31, 16)
#define SHU4_PLL0 0x00001c80
#define SHU4_PLL0_RG_RPHYPLL_TOP_REV GENMASK(15, 0)
#define SHU4_PLL0_RG_RPHYPLL_LOAD_EN BIT(19)
#define SHU4_PLL1 0x00001c84
#define SHU4_PLL1_RG_RPHYPLLGP_CK_SEL BIT(0)
#define SHU4_PLL1_SHU4_PLL1_RFU GENMASK(3, 1)
#define SHU4_PLL1_R_SHU_AUTO_PLL_MUX BIT(4)
#define SHU4_PLL1_RESERVED_0X1C84 GENMASK(31, 5)
#define SHU4_PLL2 0x00001c88
#define SHU4_PLL2_RG_RCLRPLL_LOAD_EN BIT(19)
#define SHU4_PLL3 0x00001c8c
#define SHU4_PLL3_RESERVED_0X1C8C GENMASK(31, 0)
#define SHU4_PLL4 0x00001c90
#define SHU4_PLL4_RG_RPHYPLL_RESERVED GENMASK(15, 0)
#define SHU4_PLL4_RG_RPHYPLL_FS GENMASK(19, 18)
#define SHU4_PLL4_RG_RPHYPLL_BW GENMASK(22, 20)
#define SHU4_PLL4_RG_RPHYPLL_ICHP GENMASK(25, 24)
#define SHU4_PLL4_RG_RPHYPLL_IBIAS GENMASK(27, 26)
#define SHU4_PLL4_RG_RPHYPLL_BLP BIT(29)
#define SHU4_PLL4_RG_RPHYPLL_BR BIT(30)
#define SHU4_PLL4_RG_RPHYPLL_BP BIT(31)
#define SHU4_PLL5 0x00001c94
#define SHU4_PLL5_RG_RPHYPLL_SDM_FRA_EN BIT(0)
#define SHU4_PLL5_RG_RPHYPLL_SDM_PCW_CHG BIT(1)
#define SHU4_PLL5_RG_RPHYPLL_SDM_PCW GENMASK(31, 16)
#define SHU4_PLL6 0x00001c98
#define SHU4_PLL6_RG_RCLRPLL_RESERVED GENMASK(15, 0)
#define SHU4_PLL6_RG_RCLRPLL_FS GENMASK(19, 18)
#define SHU4_PLL6_RG_RCLRPLL_BW GENMASK(22, 20)
#define SHU4_PLL6_RG_RCLRPLL_ICHP GENMASK(25, 24)
#define SHU4_PLL6_RG_RCLRPLL_IBIAS GENMASK(27, 26)
#define SHU4_PLL6_RG_RCLRPLL_BLP BIT(29)
#define SHU4_PLL6_RG_RCLRPLL_BR BIT(30)
#define SHU4_PLL6_RG_RCLRPLL_BP BIT(31)
#define SHU4_PLL7 0x00001c9c
#define SHU4_PLL7_RG_RCLRPLL_SDM_FRA_EN BIT(0)
#define SHU4_PLL7_RG_RCLRPLL_SDM_PCW_CHG BIT(1)
#define SHU4_PLL7_RG_RCLRPLL_SDM_PCW GENMASK(31, 16)
#define SHU4_PLL8 0x00001ca0
#define SHU4_PLL8_RG_RPHYPLL_POSDIV GENMASK(2, 0)
#define SHU4_PLL8_RG_RPHYPLL_PREDIV GENMASK(19, 18)
#define SHU4_PLL9 0x00001ca4
#define SHU4_PLL9_RG_RPHYPLL_RST_DLY GENMASK(9, 8)
#define SHU4_PLL9_RG_RPHYPLL_LVROD_EN BIT(12)
#define SHU4_PLL9_RG_RPHYPLL_MONREF_EN BIT(13)
#define SHU4_PLL9_RG_RPHYPLL_MONVC_EN GENMASK(15, 14)
#define SHU4_PLL9_RG_RPHYPLL_MONCK_EN BIT(16)
#define SHU4_PLL10 0x00001ca8
#define SHU4_PLL10_RG_RCLRPLL_POSDIV GENMASK(2, 0)
#define SHU4_PLL10_RG_RCLRPLL_PREDIV GENMASK(19, 18)
#define SHU4_PLL11 0x00001cac
#define SHU4_PLL11_RG_RCLRPLL_RST_DLY GENMASK(9, 8)
#define SHU4_PLL11_RG_RCLRPLL_LVROD_EN BIT(12)
#define SHU4_PLL11_RG_RCLRPLL_MONREF_EN BIT(13)
#define SHU4_PLL11_RG_RCLRPLL_MONVC_EN GENMASK(15, 14)
#define SHU4_PLL11_RG_RCLRPLL_MONCK_EN BIT(16)
#define SHU4_PLL12 0x00001cb0
#define SHU4_PLL12_RG_RCLRPLL_EXT_PODIV GENMASK(5, 0)
#define SHU4_PLL12_RG_RCLRPLL_BYPASS BIT(6)
#define SHU4_PLL12_RG_RCLRPLL_EXTPODIV_EN BIT(7)
#define SHU4_PLL12_RG_RCLRPLL_EXT_FBDIV GENMASK(13, 8)
#define SHU4_PLL12_RG_RCLRPLL_EXTFBDIV_EN BIT(15)
#define SHU4_PLL12_RG_RPHYPLL_EXT_FBDIV GENMASK(21, 16)
#define SHU4_PLL12_RG_RPHYPLL_EXTFBDIV_EN BIT(22)
#define SHU4_PLL13 0x00001cb4
#define SHU4_PLL13_RG_RCLRPLL_FB_DL GENMASK(5, 0)
#define SHU4_PLL13_RG_RCLRPLL_REF_DL GENMASK(13, 8)
#define SHU4_PLL13_RG_RPHYPLL_FB_DL GENMASK(21, 16)
#define SHU4_PLL13_RG_RPHYPLL_REF_DL GENMASK(29, 24)
#define SHU4_PLL14 0x00001cb8
#define SHU4_PLL14_RG_RPHYPLL_SDM_HREN BIT(0)
#define SHU4_PLL14_RG_RPHYPLL_SDM_SSC_PH_INIT BIT(1)
#define SHU4_PLL14_RG_RPHYPLL_SDM_SSC_PRD GENMASK(31, 16)
#define SHU4_PLL15 0x00001cbc
#define SHU4_PLL15_RG_RPHYPLL_SDM_SSC_DELTA GENMASK(15, 0)
#define SHU4_PLL15_RG_RPHYPLL_SDM_SSC_DELTA1 GENMASK(31, 16)
#define SHU4_PLL20 0x00001cd0
#define SHU4_PLL20_RG_RCLRPLL_SDM_HREN BIT(0)
#define SHU4_PLL20_RG_RCLRPLL_SDM_SSC_PH_INIT BIT(1)
#define SHU4_PLL20_RG_RCLRPLL_SDM_SSC_PRD GENMASK(31, 16)
#define SHU4_PLL21 0x00001cd4
#define SHU4_PLL21_RG_RCLRPLL_SDM_SSC_DELTA GENMASK(15, 0)
#define SHU4_PLL21_RG_RCLRPLL_SDM_SSC_DELTA1 GENMASK(31, 16)
#endif /*__DDRPHY_PLL_REG_H__*/

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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef _ACTIMING_H
#define _ACTIMING_H
/***********************************************************************/
/* Includes */
/***********************************************************************/
#include "dramc_register.h"
//Definitions to enable specific freq's LP4 ACTiming support (To save code size)
#define SUPPORT_LP5_DDR6400_ACTIM 0
#define SUPPORT_LP5_DDR5500_ACTIM 0
#define SUPPORT_LP5_DDR4266_ACTIM 0
#define SUPPORT_LP5_DDR3200_ACTIM 0
#define SUPPORT_LP4_DDR4266_ACTIM 1
#define SUPPORT_LP4_DDR3733_ACTIM 1
#define SUPPORT_LP4_DDR3200_ACTIM 1
#define SUPPORT_LP4_DDR2667_ACTIM 0
#define SUPPORT_LP4_DDR2400_ACTIM 1
#define SUPPORT_LP4_DDR1866_ACTIM 1
#define SUPPORT_LP4_DDR1600_ACTIM 1
#define SUPPORT_LP4_DDR1333_ACTIM 0
#define SUPPORT_LP4_DDR1200_ACTIM 1
#define SUPPORT_LP4_DDR800_ACTIM 1
#define SUPPORT_LP4_DDR400_ACTIM 0
/* Used to keep track the total number of LP4 ACTimings */
/* Since READ_DBI is enable/disabled using preprocessor C define
* -> Save code size by excluding unneeded ACTimingTable entries
* Note 1: READ_DBI on/off is for (LP4 data rate >= DDR2667 (FSP1))
* Must make sure DDR3733 is the 1st entry (DMCATRAIN_INTV is used)
*/
typedef enum
{
#if SUPPORT_LP4_DDR4266_ACTIM
#if ENABLE_READ_DBI
AC_TIME_LP4_BYTE_DDR4266_RDBI_ON = 0,
AC_TIME_LP4_NORM_DDR4266_RDBI_ON,
#else //(ENABLE_READ_DBI == 0)
AC_TIME_LP4_BYTE_DDR4266_RDBI_OFF,
AC_TIME_LP4_NORM_DDR4266_RDBI_OFF,
#endif //ENABLE_READ_DBI
#endif
#if SUPPORT_LP4_DDR3733_ACTIM
#if ENABLE_READ_DBI
AC_TIME_LP4_BYTE_DDR3733_RDBI_ON,
AC_TIME_LP4_NORM_DDR3733_RDBI_ON,
#else //(ENABLE_READ_DBI == 0)
AC_TIME_LP4_BYTE_DDR3733_RDBI_OFF,
AC_TIME_LP4_NORM_DDR3733_RDBI_OFF,
#endif //ENABLE_READ_DBI
#endif
#if SUPPORT_LP4_DDR3200_ACTIM
#if ENABLE_READ_DBI
AC_TIME_LP4_BYTE_DDR3200_RDBI_ON,
AC_TIME_LP4_NORM_DDR3200_RDBI_ON,
#else //(ENABLE_READ_DBI == 0)
AC_TIME_LP4_BYTE_DDR3200_RDBI_OFF,
AC_TIME_LP4_NORM_DDR3200_RDBI_OFF,
#endif //ENABLE_READ_DBI
#endif
#if SUPPORT_LP4_DDR2667_ACTIM
#if ENABLE_READ_DBI
AC_TIME_LP4_BYTE_DDR2667_RDBI_ON,
AC_TIME_LP4_NORM_DDR2667_RDBI_ON,
#else //(ENABLE_READ_DBI == 0)
AC_TIME_LP4_BYTE_DDR2667_RDBI_OFF,
AC_TIME_LP4_NORM_DDR2667_RDBI_OFF,
#endif //ENABLE_READ_DBI
#endif
#if SUPPORT_LP4_DDR2400_ACTIM
AC_TIME_LP4_BYTE_DDR2400_RDBI_OFF,
AC_TIME_LP4_NORM_DDR2400_RDBI_OFF,
#endif
#if SUPPORT_LP4_DDR1866_ACTIM
AC_TIME_LP4_BYTE_DDR1866_RDBI_OFF,
AC_TIME_LP4_NORM_DDR1866_RDBI_OFF,
#endif
#if SUPPORT_LP4_DDR1600_ACTIM
AC_TIME_LP4_BYTE_DDR1600_RDBI_OFF,
AC_TIME_LP4_NORM_DDR1600_RDBI_OFF,
AC_TIME_LP4_BYTE_DDR1600_DIV4_RDBI_OFF,
AC_TIME_LP4_NORM_DDR1600_DIV4_RDBI_OFF,
#endif
#if SUPPORT_LP4_DDR1333_ACTIM
AC_TIME_LP4_BYTE_DDR1333_RDBI_OFF,
AC_TIME_LP4_NORM_DDR1333_RDBI_OFF,
#endif
#if SUPPORT_LP4_DDR1200_ACTIM
AC_TIME_LP4_BYTE_DDR1200_RDBI_OFF,
AC_TIME_LP4_NORM_DDR1200_RDBI_OFF,
AC_TIME_LP4_BYTE_DDR1200_DIV4_RDBI_OFF,
AC_TIME_LP4_NORM_DDR1200_DIV4_RDBI_OFF,
#endif
#if SUPPORT_LP4_DDR800_ACTIM
AC_TIME_LP4_BYTE_DDR800_RDBI_OFF,
AC_TIME_LP4_NORM_DDR800_RDBI_OFF,
AC_TIME_LP4_BYTE_DDR800_DIV4_RDBI_OFF,
AC_TIME_LP4_NORM_DDR800_DIV4_RDBI_OFF,
#endif
#if SUPPORT_LP4_DDR400_ACTIM
AC_TIME_LP4_BYTE_DDR400_RDBI_OFF,
AC_TIME_LP4_NORM_DDR400_RDBI_OFF,
#endif
AC_TIMING_NUMBER_LP4
} AC_TIMING_LP4_COUNT_TYPE_T;
#if (__LP5_COMBO__)
/* Used to keep track the total number of LP5 ACTimings */
typedef enum
{
#if SUPPORT_LP5_DDR6400_ACTIM
#if ENABLE_READ_DBI
AC_TIME_LP5_BYTE_DDR6400_RDBI_ON = 0,
AC_TIME_LP5_NORM_DDR6400_RDBI_ON,
#else //(ENABLE_READ_DBI == 0)
AC_TIME_LP5_BYTE_DDR6400_RDBI_OFF,
AC_TIME_LP5_NORM_DDR6400_RDBI_OFF,
#endif //ENABLE_READ_DBI
#endif
#if SUPPORT_LP5_DDR5500_ACTIM
#if ((ENABLE_READ_DBI) || (LP5_DDR4266_RDBI_WORKAROUND))
AC_TIME_LP5_BYTE_DDR5500_RDBI_ON,
AC_TIME_LP5_NORM_DDR5500_RDBI_ON,
#else
AC_TIME_LP5_BYTE_DDR5500_RDBI_OFF,
AC_TIME_LP5_NORM_DDR5500_RDBI_OFF,
#endif
#endif
#if SUPPORT_LP5_DDR4266_ACTIM
#if ((ENABLE_READ_DBI) || (LP5_DDR4266_RDBI_WORKAROUND))
AC_TIME_LP5_BYTE_DDR4266_RDBI_ON,
AC_TIME_LP5_NORM_DDR4266_RDBI_ON,
#else //(ENABLE_READ_DBI == 0)
AC_TIME_LP5_BYTE_DDR4266_RDBI_OFF,
AC_TIME_LP5_NORM_DDR4266_RDBI_OFF,
#endif //ENABLE_READ_DBI
#endif
#if SUPPORT_LP5_DDR3200_ACTIM
AC_TIME_LP5_BYTE_DDR3200_RDBI_OFF,
AC_TIME_LP5_NORM_DDR3200_RDBI_OFF,
#endif
AC_TIMING_NUMBER_LP5
} AC_TIMING_LP5_COUNT_TYPE_T;
#else
#define AC_TIMING_NUMBER_LP5 0
#endif
/* ACTiming struct declaration (declared here due Fld_wid for each register type)
* Should include all fields from ACTiming excel file (And update the correct values in UpdateACTimingReg()
* Note: DQSINCTL, DATLAT aren't in ACTiming excel file (internal delay parameters)
*/
typedef struct _ACTime_T_LP4
{
U8 dramType, cbtMode, readDBI;
U8 DivMode;
U16 freq;
U16 readLat, writeLat;
U16 dqsinctl, datlat; //DQSINCTL, DATLAT aren't in ACTiming excel file
U16 tras;
U16 trp;
U16 trpab;
U16 trc;
U16 trfc;
U16 trfcpb;
U16 txp;
U16 trtp;
U16 trcd;
U16 twr;
U16 twtr;
U16 tpbr2pbr;
U16 tpbr2act;
U16 tr2mrw;
U16 tw2mrw;
U16 tmrr2mrw;
U16 tmrw;
U16 tmrd;
U16 tmrwckel;
U16 tpde;
U16 tpdx;
U16 tmrri;
U16 trrd;
U16 trrd_4266;
U16 tfaw;
U16 tfaw_4266;
U16 trtw_odt_off;
U16 trtw_odt_on;
U16 txrefcnt;
U16 tzqcs;
U16 xrtw2w_new_mode;
U16 xrtw2w_old_mode;
U16 xrtw2r_odt_on;
U16 xrtw2r_odt_off;
U16 xrtr2w_odt_on;
U16 xrtr2w_odt_off;
U16 xrtr2r_new_mode;
U16 xrtr2r_old_mode;
U16 tr2mrr;
U16 vrcgdis_prdcnt;
U16 hwset_mr2_op;
U16 hwset_mr13_op;
U16 hwset_vrcg_op;
U16 trcd_derate;
U16 trc_derate;
U16 tras_derate;
U16 trpab_derate;
U16 trp_derate;
U16 trrd_derate;
U16 trtpd;
U16 twtpd;
U16 tmrr2w_odt_off;
U16 tmrr2w_odt_on;
U16 ckeprd;
U16 ckelckcnt;
U16 zqlat2;
//DRAMC_REG_SHU_AC_TIME_05T ===================================
U16 tras_05T;
U16 trp_05T;
U16 trpab_05T;
U16 trc_05T;
U16 trfc_05T;
U16 trfcpb_05T;
U16 txp_05T;
U16 trtp_05T;
U16 trcd_05T;
U16 twr_05T;
U16 twtr_05T;
U16 tpbr2pbr_05T;
U16 tpbr2act_05T;
U16 tr2mrw_05T;
U16 tw2mrw_05T;
U16 tmrr2mrw_05T;
U16 tmrw_05T;
U16 tmrd_05T;
U16 tmrwckel_05T;
U16 tpde_05T;
U16 tpdx_05T;
U16 tmrri_05T;
U16 trrd_05T;
U16 trrd_4266_05T;
U16 tfaw_05T;
U16 tfaw_4266_05T;
U16 trtw_odt_off_05T;
U16 trtw_odt_on_05T;
U16 trcd_derate_05T;
U16 trc_derate_05T;
U16 tras_derate_05T;
U16 trpab_derate_05T;
U16 trp_derate_05T;
U16 trrd_derate_05T;
U16 trtpd_05T;
U16 twtpd_05T;
} ACTime_T_LP4;
typedef struct _ACTime_T_LP5
{
U8 dramType, cbtMode, readDBI;
U8 DivMode;
U16 freq;
U16 readLat, writeLat;
U16 dqsinctl, datlat; //DQSINCTL, DATLAT aren't in ACTiming excel file
U16 tras;
U16 trp;
U16 trpab;
U16 trc;
U16 trfc;
U16 trfcpb;
U16 txp;
U16 trtp;
U16 trcd;
U16 twr;
U16 twtr;
U16 twtr_l;
U16 tpbr2pbr;
U16 tpbr2act;
U16 tr2mrw;
U16 tw2mrw;
U16 tmrr2mrw;
U16 tmrw;
U16 tmrd;
U16 tmrwckel;
U16 tpde;
U16 tpdx;
U16 tmrri;
U16 trrd;
U16 tfaw;
U16 tr2w_odt_off;
U16 tr2w_odt_on;
U16 txrefcnt;
U16 wckrdoff;
U16 wckwroff;
U16 tzqcs;
U16 xrtw2w_odt_off;
U16 xrtw2w_odt_on;
U16 xrtw2r_odt_off_otf_off;
U16 xrtw2r_odt_on_otf_off;
U16 xrtw2r_odt_off_otf_on;
U16 xrtw2r_odt_on_otf_on;
U16 xrtr2w_odt_on;
U16 xrtr2w_odt_off;
U16 xrtr2r_odt_off;
U16 xrtr2r_odt_on;
U16 xrtw2w_odt_off_wck;
U16 xrtw2w_odt_on_wck;
U16 xrtw2r_odt_off_wck;
U16 xrtw2r_odt_on_wck;
U16 xrtr2w_odt_off_wck;
U16 xrtr2w_odt_on_wck;
U16 xrtr2r_wck;
U16 tr2mrr;
U16 hwset_mr2_op;
U16 hwset_mr13_op;
U16 hwset_vrcg_op;
U16 vrcgdis_prdcnt;
U16 lp5_cmd1to2en;
U16 trtpd;
U16 twtpd;
U16 tmrr2w;
U16 ckeprd;
U16 ckelckcnt;
U16 tcsh_cscal;
U16 tcacsh;
U16 tcsh;
U16 trcd_derate;
U16 trc_derate;
U16 tras_derate;
U16 trpab_derate;
U16 trp_derate;
U16 trrd_derate;
U16 zqlat2;
//DRAMC_REG_SHU_AC_TIME_05T ===================================
U16 tras_05T;
U16 trp_05T;
U16 trpab_05T;
U16 trc_05T;
U16 trfc_05T;
U16 trfcpb_05T;
U16 txp_05T;
U16 trtp_05T;
U16 trcd_05T;
U16 twr_05T;
U16 twtr_05T;
U16 twtr_l_05T;
U16 tr2mrw_05T;
U16 tw2mrw_05T;
U16 tmrr2mrw_05T;
U16 tmrw_05T;
U16 tmrd_05T;
U16 tmrwckel_05T;
U16 tpde_05T;
U16 tpdx_05T;
U16 tmrri_05T;
U16 trrd_05T;
U16 tfaw_05T;
U16 tr2w_odt_off_05T;
U16 tr2w_odt_on_05T;
U16 wckrdoff_05T;
U16 wckwroff_05T;
U16 trtpd_05T;
U16 twtpd_05T;
U16 tpbr2pbr_05T;
U16 tpbr2act_05T;
U16 trcd_derate_05T;
U16 trc_derate_05T;
U16 tras_derate_05T;
U16 trpab_derate_05T;
U16 trp_derate_05T;
U16 trrd_derate_05T;
} ACTime_T_LP5;
//ACTimingTbl[] forward declaration
extern const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4];
extern const ACTime_T_LP5 ACTimingTbl_LP5[AC_TIMING_NUMBER_LP5];
extern U8 vDramcACTimingGetDatLat(DRAMC_CTX_T *p);
extern DRAM_STATUS_T DdrUpdateACTiming(DRAMC_CTX_T *p);
extern void vDramcACTimingOptimize(DRAMC_CTX_T *p);
extern DRAM_CBT_MODE_T vGet_Dram_CBT_Mode(DRAMC_CTX_T *p);
#endif

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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef _DRAMC_COMMON_H_
#define _DRAMC_COMMON_H_
#define __ETT__ 0
//#include <console/console.h>
#include <delay.h>
#include <device/mmio.h>
#include <stdint.h>
#include <types.h>
#include <reg.h>
#include <string.h>
#include <soc/dramc_common.h>
#include <timer.h>
#include <print.h>
#include "dramc_register.h"
#include "dramc_pi_api.h"
#include "dramc_int_slt.h"
#if FOR_DV_SIMULATION_USED == 1
#include "dramc_dv_init.h"
#endif
/***********************************************************************/
/* Public Types */
/***********************************************************************/
/*------------------------------------------------------------*/
/* macros, defines, typedefs, enums */
/*------------------------------------------------------------*/
/************************** Common Macro *********************/
#define dsb() asm volatile("dsb sy" : : : "memory")
#define DRV_Reg32(x) read32((const void *)((u64)(x)))
#define DRV_WriteReg32(x, y) write32((void *)((u64)(x)), (y))
#define mcDELAY_US(x) udelay(x)
#define mcDELAY_MS(x) udelay(x*1000)
#define mcDELAY_XUS(x) udelay(x)
#define mcDELAY_XNS(x) udelay(1)
/**********************************************/
/* Priority of debug log */
/*--------------------------------------------*/
/* mcSHOW_DBG_MSG: High */
/* mcSHOW_DBG_MSG2: Medium High */
/* mcSHOW_DBG_MSG3: Medium Low */
/* mcSHOW_DBG_MSG4: Low */
/**********************************************/
#define CALIBRATION_LOG 1
#if CALIBRATION_LOG
#define mcSHOW_DBG_MSG(_x_) {print _x_;}
#define mcSHOW_DBG_MSG2(_x_) //{print _x_;}
#define mcSHOW_ERR_MSG(_x_) {print _x_;}
#else
#define mcSHOW_DBG_MSG(_x_)
#define mcSHOW_DBG_MSG2(_x_)
#define mcSHOW_ERR_MSG(_x_)
#endif
#define mcSHOW_DBG_MSG3(_x_) // {print _x_;}
#define mcSHOW_DBG_MSG4(_x_)
#define mcSHOW_DBG_MSG5(_x_)
#define mcSHOW_JV_LOG_MSG(_x_)
#if EYESCAN_LOG
#define mcSHOW_EYESCAN_MSG(_x_) {print _x_;}
#else
#define mcSHOW_EYESCAN_MSG(_x_) //{print _x_;}
#endif
#define mcSHOW_DBG_MSG5(_x_)
#define mcSHOW_TIME_MSG(_x_)
#define mcDUMP_REG_MSG(_x_)
#define mcFPRINTF(_x_)
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof (x) / sizeof (x[0]))
#endif
#define enter_function() \
({mcSHOW_DBG_MSG(("enter %s\n", __FUNCTION__));})
#define exit_function() \
({mcSHOW_DBG_MSG(("exit %s\n", __FUNCTION__));})
extern int dump_log;
#endif // _DRAMC_COMMON_H_

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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef _DRAMC_DV_INIT_H_
#define _DRAMC_DV_INIT_H_
#include "dramc_common.h"
#include "dramc_int_global.h"
#include "x_hal_io.h"
#include "sv_c_data_traffic.h"
//=========================================================
//DRAM CONFIG ELEMENT COLLECTION
//=========================================================
typedef enum { DDR3, DDR4, LPDDR3, LPDDR4, LPDDR5, PSRAM } DRAM_TYPE_T;
typedef enum {BG4BK4, BK8, BK16, BKORG_RFU} e_BKORG;
typedef enum {DIS_both, EN_t, EN_both, EN_c} e_RDQSWCK;//MR20
#define SA_CONFIG_EN 1
#define DV_CONFIG_EN 1
//=========================================================
//Build Top configuration
//=========================================================
#define DFS_GROUP_NUM 10
#define CH_NUM 2
#define RK_NUM_PER_CH 2
#define DONT_CARE_VALUE 0
#define PULL_UP 1
#define PULL_DOWN 1
typedef struct Gating_config
{
U8 GAT_TRACK_EN ;
U8 RX_GATING_MODE ;
U8 RX_GATING_TRACK_MODE ;
U8 SELPH_MODE ;
U8 PICG_EARLY_EN ;
U8 VALID_LAT_VALUE ;
}Gating_confg_T;
//=========================================================
//DV configuration connection
//=========================================================
#if DV_CONFIG_EN==1
typedef struct DRAMC_DVFS_GROUP_transfer
{
U8 CKR ; //LPDDR5 CKR could be 4 and 2 other memory type should be 1
U8 DQSIEN_MODE ; //ANA DQSG mode config LPDDR4 = 1, LPDDR5 with other modes
U8 DQ_P2S_RATIO; //16-1 8-1 4-1 LPDDR5 could support 16-1 mode
U8 RESERVED_8BIT;
U32 data_rate ;
}DRAMC_DVFS_GROUP_transfer_T;
typedef struct DV_configuration
{
U8 EX_ROW_EN_1 ;
U8 EX_ROW_EN_0 ;
U8 BYTE_MODE_1 ;
U8 BYTE_MODE_0 ;
U8 LP4Y_EN ;
U8 LP4_WR_PST ;
U8 LP4_OTF ;
U8 NEW_8X_MODE ;
U8 LP45_APHY_COMB_EN;
U8 DLL_IDLE_MODE ;
U8 NEW_RANK_MODE ;
U8 DLL_ASYNC_EN ;
U8 MD32_EN ;
U8 SRAM_EN ;
U8 GP_NUM ;
} DV_new_config_T;
#endif
//=========================================================
//LPDDR4 DRAM config
//=========================================================
typedef struct LP4_DRAM_CONFIG
{
U8 BYTE_MODE[2]; //diff rank
U8 EX_ROW_EN[2]; //diff rank --density over 10G should 1
U8 MR_WL ;
U8 MR_RL ;
U8 BL ;
U8 RPST ;
U8 RD_PRE ;
U8 WR_PRE ;
U8 WR_PST ;
U8 DBI_WR ;
U8 DBI_RD ;
// U8 DMI ; //No use default enable
U8 OTF ;
U8 LP4Y_EN ;
U8 WORK_FSP ;
} LP4_DRAM_CONFIG_T;
//=========================================================
//LPDDR5 DRAM config
//=========================================================
typedef struct LP5_DRAM_CONFIG
{
U8 BYTE_MODE[2] ;
U8 EX_ROW_EN[2] ;
U8 MR_WL ;
U8 MR_RL ;
U8 BL ;
U8 CK_Mode ;
U8 RPST ;
U8 RD_PRE ;
U8 WR_PRE ;
U8 WR_PST ;
U8 DBI_WR ;
U8 DBI_RD ;
U8 DMI ;
U8 OTF ;
U8 WCK_PST ;
U8 RDQS_PRE ;
U8 RDQS_PST ;
U8 CA_ODT ;
U8 DQ_ODT ;
U8 CKR ;
U8 WCK_ON ;
U8 WCK_FM ;
U8 WCK_ODT ;
U8 DVFSQ ;
U8 DVFSC ;
e_RDQSWCK RDQSmode[2] ;
U8 WCKmode[2] ;
U8 RECC ;
U8 WECC ;
e_BKORG BankMode ;
U8 WORK_FSP ;
} LP5_DRAM_CONFIG_T;
//=========================================================
//Analog PHY config
//=========================================================
typedef struct ANA_top_function_config
{
U8 DLL_ASYNC_EN ;
U8 ALL_SLAVE_EN ;
U8 NEW_RANK_MODE ;
U8 DLL_IDLE_MODE ;
U8 LP45_APHY_COMB_EN;
U8 TX_ODT_DIS ;
U8 NEW_8X_MODE ;
}ANA_top_config_T;
typedef struct ANA_DVFS_core_config
{
U8 CKR;
U8 DQ_P2S_RATIO;
U8 LP5_1600_DQ_P2S_MODE;
U8 CA_P2S_RATIO;
U8 DQ_CA_OPEN;
U8 DQ_SEMI_OPEN;
U8 CA_SEMI_OPEN;
U8 CA_FULL_RATE;
U8 DQ_CKDIV4_EN;
U8 CA_CKDIV4_EN;
U8 CA_PREDIV_EN;
U8 PH8_DLY;
U8 SEMI_OPEN_CA_PICK_MCK_RATIO;
U8 DQ_AAMCK_DIV;
U8 CA_AAMCK_DIV;
U8 CA_ADMCK_DIV;
U8 DQ_TRACK_CA_EN;
U32 PLL_FREQ;
U8 DQ_UI_PI_RATIO;
U8 CA_UI_PI_RATIO;
} ANA_DVFS_CORE_T;
//=========================================================
//DVFS group configuration
//=========================================================
typedef struct DRAMC_DVFS_GROUP_CONFIG
{
U32 data_rate ;
U8 DQSIEN_MODE ; //ANA DQSG mode config LPDDR4 = 1, LPDDR5 with other modes
U8 DQ_P2S_RATIO; //16-1 8-1 4-1 LPDDR5 could support 16-1 mode
U8 CKR ; //LPDDR5 CKR could be 4 and 2 other memory type should be 1
}DRAMC_DVFS_GROUP_CONFIG_T;
//=========================================================
//DRAMC Subsystem config
//=========================================================
typedef struct DRAMC_SUBSYS_CONFIG
{
U8 GP_NUM ;
U8 SRAM_EN ;
U8 MD32_EN ;
ANA_top_config_T *a_cfg ;
ANA_DVFS_CORE_T *a_opt ;
LP4_DRAM_CONFIG_T *lp4_init ;
LP5_DRAM_CONFIG_T *lp5_init ;
DRAMC_DVFS_GROUP_CONFIG_T *DFS_GP[DFS_GROUP_NUM];
}DRAMC_SUBSYS_CONFIG_T;
typedef struct DUT_shuf_config_T {
U8 CKE_DBE_CNT ;
U8 FASTWAKE2 ;
U8 DMPGTIM ;
U8 ADVPREEN ;
U8 DLE_256EN ;
U8 LECC ;
U8 WPST1P5T_OPT ;
U8 LP4YEN ;
U8 LP5_CAS_MODE ;
U8 LP5_SEP_ACT ;
U8 LP5_BGOTF ;
U8 LP5_BGEN ;
U8 LP5_RDQS_SE_EN ;
U8 CKR ;
U8 DQSIEN_MODE ;
U8 DQ_P2S_RATIO ;
U32 data_rate ;
}__attribute__((packed)) DUT_shuf_config_T;
typedef struct DUT_top_set_T {
U8 DVFSRTMRWEN ;
U8 NO_QUEUEFLUSH_EN ;
U8 RG_SPM_MODE ;
U8 MD32_EN ;
U8 SRAM_EN ;
U8 RX_PIPE_BYPASS_EN ;
U8 TX_PIPE_BYPASS_EN ;
U32 WAIT_DLE_EXT_DLY ;
U32 RX_DCM_EXT_DLY ;
U8 old_dcm_mode ;
U8 DPHY_DCM_MODE ;
U8 TX_OE_EXT_OPT ;
U8 TXP_WORKAROUND_OPT ;
U32 VALID_LAT_VALUE ;
U8 RXTRACK_PBYTE_OPT ;
U8 TRACK_UP_MODE ;
U8 TREFBWIG_IGNORE ;
U8 SELPH_MODE ;
U8 RANK_SWAP ;
U8 BGPIPE_EN ;
U8 PICG_MODE ;
U8 RTMRR_MODE ;
U8 TMRRI_MODE ;
U8 DQS_OSC_AT_TIMER ;
U8 WPST1P5T_OPT ;
U8 LP5_ZQ_OPT ;
U8 LP5WRAPEN ;
U8 LP4_SE_MODE ;
U8 LP4Y_EN ;
U8 LP4_WR_PST ;
U8 LP4_OTF ;
U8 PLL_MODE_OPTION ;
U8 NEW_8X_MODE ;
U8 LP45_APHY_COMB_EN ;
U8 DLL_IDLE_MODE ;
U8 NEW_RANK_MODE ;
U8 DLL_ASYNC_EN ;
U32 memory_type ;
U32 GP_NUM ;
}__attribute__((packed)) DUT_top_set_T;
extern Gating_confg_T Gat_p;
extern DRAM_TYPE_T MEM_TYPE;
extern LP4_DRAM_CONFIG_T LP4_INIT;
extern LP5_DRAM_CONFIG_T LP5_INIT;
extern ANA_top_config_T ana_top_p;
extern ANA_DVFS_CORE_T ANA_option;
extern DRAMC_DVFS_GROUP_CONFIG_T DFS_TOP[DFS_GROUP_NUM];
extern DRAMC_SUBSYS_CONFIG_T DV_p;
extern DRAMC_CTX_T *DramcConfig;
extern DUT_top_set_T DUTTopSetGlobal;
extern DUT_shuf_config_T DUTShufConfigGlobal[10];
#define A_T DV_p.a_cfg
#define A_D DV_p.a_opt
#define M_LP4 DV_p.lp4_init
#define DFS(i) DV_p.DFS_GP[i]
#define LPDDR5_EN_S ((MEM_TYPE==LPDDR5) ? 1 : 0)
#define LPDDR4_EN_S ((MEM_TYPE==LPDDR4) ? 1 : 0)
#define DUT_p DUTTopSetGlobal
#define DUT_shu_p DUTShufConfigGlobal
#if FOR_DV_SIMULATION_USED==1
EXTERN void register_write(int address, int data);
EXTERN void register_read(int address, int * data);
EXTERN void delay_us(u32 delta);
EXTERN void delay_ns(u32 delta);
EXTERN void timestamp_show();
EXTERN void build_api_initial();
EXTERN void register_write_c(u32 address, u32 data);
EXTERN u32 register_read_c(u32 address);
EXTERN void conf_to_sram_sudo(int ch_id , int group_id, int conf_id);
//================ added by Lingyun Wu 11.14 =====================
EXTERN void broadcast_on(void);
EXTERN void broadcast_off(void);
//================ added by Lingyun Wu 11.14 =====================
EXTERN void mygetscope();
EXTERN void mysetscope();
#endif
#if DV_CONFIG_EN
extern void get_dfs_configuration_from_DV_random(DRAMC_DVFS_GROUP_transfer_T * tr, int group_id);
extern void get_top_configuration_from_DV_random(DV_new_config_T * tr);
#endif
//DRAM LP4 initial configuration
extern U8 LP4_DRAM_INIT_RLWL_MRfield_config(U32 data_rate);
extern void DPI_SW_main_LP4(DRAMC_CTX_T *p, cal_sv_rand_args_t *psra);
extern void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr);
extern void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr);
extern void LP5_DRAM_config(DRAMC_DVFS_GROUP_CONFIG_T *dfs_tr, LP5_DRAM_CONFIG_T *tr);
extern void ANA_TOP_FUNCTION_CFG(ANA_top_config_T *tr,U16 data_rate);
extern void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs);
extern void ANA_sequence_shuffle_colletion(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr);
extern void ANA_Config_shuffle(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 group_id);
#endif // _DRAMC_DV_INIT_H_

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src/vendorcode/mediatek/mt8192/include/dramc_int_global.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef _INT_GLOBAL_H
#define _INT_GLOBAL_H
#include "dramc_pi_api.h"
#include "dramc_int_slt.h"
/*
****************************************************************************************
** macro
****************************************************************************************
*/
#define DVT_TEST_DUMMY_RD_SIDEBAND_FROM_SPM 0
//#define DVT_TEST_DUMMY_READ_FOR_DQS_GATING_TRACKING
//#define DVT_TEST_RX_DLY_HW_TRACKING
/*
****************************************************************************************
** ANA_init_config.c
****************************************************************************************
*/
EXTERN void ANA_init(DRAMC_CTX_T *p);
EXTERN void RESETB_PULL_DN(DRAMC_CTX_T *p);
/*
****************************************************************************************
** DIG_NONSHUF_config.c
****************************************************************************************
*/
EXTERN void DIG_STATIC_SETTING(DRAMC_CTX_T *p);
/*
****************************************************************************************
*
** DIG_SHUF_config.c
****************************************************************************************
*/
EXTERN void DIG_CONFIG_SHUF(DRAMC_CTX_T *p,U32 ch_id, U32 group_id);
/*
****************************************************************************************
*
** dramc_debug.c
****************************************************************************************
*/
EXTERN U8 gFinalCBTVrefDQ[CHANNEL_NUM][RANK_MAX];
EXTERN U8 gFinalRXVrefDQ[CHANNEL_NUM][RANK_MAX][2];
EXTERN U8 gFinalTXVrefDQ[CHANNEL_NUM][RANK_MAX];
#ifdef FOR_HQA_REPORT_USED
EXTERN U8 gHQALog_flag;
EXTERN U16 gHQALOG_RX_delay_cell_ps_075V;
EXTERN int hqa_vmddr_class;
EXTERN void HQA_Log_Message_for_Report(DRAMC_CTX_T *p, U8 u1ChannelIdx, U8 u1RankIdx, U32 who_am_I, U8 *main_str, U8 *main_str2, U8 byte_bit_idx, S32 value1, U8 *ans_str);
#endif
// --- Eye scan variables -----
EXTERN U8 gCBT_EYE_Scan_flag;
EXTERN U8 gRX_EYE_Scan_flag;
EXTERN U8 gTX_EYE_Scan_flag;
EXTERN U8 gEye_Scan_color_flag;
EXTERN U8 gCBT_EYE_Scan_only_higheset_freq_flag;
EXTERN U8 gRX_EYE_Scan_only_higheset_freq_flag;
EXTERN U8 gTX_EYE_Scan_only_higheset_freq_flag;
EXTERN U8 gEye_Scan_unterm_highest_flag;
#if ENABLE_EYESCAN_GRAPH
#define VREF_TOTAL_NUM_WITH_RANGE (((51 + 30) + 1) / (EYESCAN_GRAPH_CATX_VREF_STEP < EYESCAN_GRAPH_RX_VREF_STEP ? EYESCAN_GRAPH_CATX_VREF_STEP : EYESCAN_GRAPH_RX_VREF_STEP)) //range0 0~50 + range1 21~50
#define EYESCAN_BROKEN_NUM 3
#define EYESCAN_DATA_INVALID 0x7f
EXTERN S16 gEyeScan_Min[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH_LP4][EYESCAN_BROKEN_NUM];
EXTERN S16 gEyeScan_Max[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH_LP4][EYESCAN_BROKEN_NUM];
EXTERN S16 gEyeScan_MinMax_store_delay[DQS_NUMBER];
EXTERN U16 gEyeScan_CaliDelay[DQS_NUMBER];
EXTERN U16 gEyeScan_WinSize[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH_LP4];
EXTERN S16 gEyeScan_DelayCellPI[DQ_DATA_WIDTH_LP4];
EXTERN U16 gEyeScan_ContinueVrefHeight[DQ_DATA_WIDTH_LP4];
EXTERN U16 gEyeScan_TotalPassCount[DQ_DATA_WIDTH_LP4];
EXTERN void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p);
EXTERN void print_EYESCAN_LOG_message(DRAMC_CTX_T *p, U8 print_type);
#endif
#if MRW_CHECK_ONLY || MRW_BACKUP
EXTERN U8 gFSPWR_Flag[RANK_MAX];
#endif
#ifdef FOR_HQA_TEST_USED
EXTERN void HQA_measure_message_reset_all_data(DRAMC_CTX_T *p);
#endif
#if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION
void DramcRunTimeShmooRG_BackupRestore(DRAMC_CTX_T *p);
#endif
/*
****************************************************************************************
** dramc_dvfs.c
****************************************************************************************
*/
EXTERN U8 get_shuffleIndex_by_Freq(DRAMC_CTX_T *p);
EXTERN void vInitMappingFreqArray(DRAMC_CTX_T *p);
EXTERN void vSetDFSTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable);
EXTERN DRAM_DFS_FREQUENCY_TABLE_T* get_FreqTbl_by_shuffleIndex(DRAMC_CTX_T *p, U8 index);
EXTERN void vSetDFSFreqSelByTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable);
EXTERN void DramcDFSDirectJump(DRAMC_CTX_T *p, U8 shu_level);
EXTERN void DramcSaveToShuffleSRAM(DRAMC_CTX_T *p, DRAM_DFS_SHUFFLE_TYPE_T srcRG, DRAM_DFS_SHUFFLE_TYPE_T dstRG);
EXTERN void LoadShuffleSRAMtoDramc(DRAMC_CTX_T *p, DRAM_DFS_SHUFFLE_TYPE_T srcRG, DRAM_DFS_SHUFFLE_TYPE_T dstRG);
EXTERN void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, U8 shu_level);
EXTERN void DVFSSettings(DRAMC_CTX_T *p);
EXTERN void DPMEnableTracking(DRAMC_CTX_T *p, U32 u4Reg, U32 u4Field, U8 u1ShuIdx, U8 u1Enable);
EXTERN void DPMInit(DRAMC_CTX_T *p);
EXTERN void TransferPLLToSPMControl(DRAMC_CTX_T *p, U32 MD32Offset);
EXTERN void DramcCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr);
EXTERN void DdrphyCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr);
EXTERN void EnableDFSHwModeClk(DRAMC_CTX_T *p);
EXTERN void DPHYSaveToSRAMShuWA(DRAMC_CTX_T *p, U8 shu_level);
EXTERN void DPHYSRAMShuWAToSHU1(DRAMC_CTX_T *p);
EXTERN void SRAMShuRestoreToDPHYWA(DRAMC_CTX_T *p, U8 sram_shu_level, U8 pingpong_shu_level);
/*
****************************************************************************************
** dramc_dv_freq_related.c
****************************************************************************************
*/
EXTERN void sv_algorithm_assistance_LP4_1600(DRAMC_CTX_T *p);
EXTERN void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p);
EXTERN void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p);
EXTERN void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p);
EXTERN void CInit_golden_mini_freq_related_vseq_LP4_4266(DRAMC_CTX_T *p);
EXTERN void CInit_golden_mini_freq_related_vseq_LP5_3200(DRAMC_CTX_T *p);
EXTERN void CInit_golden_mini_freq_related_vseq_LP5_3200_SHU1(DRAMC_CTX_T *p);
EXTERN void CInit_golden_mini_freq_related_vseq_LP5_4266(DRAMC_CTX_T *p);
EXTERN void CInit_golden_mini_freq_related_vseq_LP5_5500(DRAMC_CTX_T *p);
/*
****************************************************************************************
** dramc_dv_main.c
****************************************************************************************
*/
#if (FOR_DV_SIMULATION_USED == 1)
EXTERN void DPI_DRAMC_init_entry();
EXTERN void DPI_DRAM_INIT();
#endif
/*
****************************************************************************************
** dramc_pi_basic.c
****************************************************************************************
*/
EXTERN U8 u1PrintModeRegWrite;
EXTERN void vApplyConfigBeforeCalibration(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p);
EXTERN void SetCKE2RankIndependent(DRAMC_CTX_T *p);
EXTERN void DramcDQSPrecalculation_TrackingOff(DRAMC_CTX_T *p, U8 shu_level);
EXTERN void DramcDQSPrecalculation_TrackingOn(DRAMC_CTX_T *p, U8 shu_level);
EXTERN void DramcHWDQSGatingTracking_ModeSetting(DRAMC_CTX_T *p);
EXTERN void Set_MRR_Pinmux_Mapping(DRAMC_CTX_T *p);
EXTERN void Set_DQO1_Pinmux_Mapping(DRAMC_CTX_T *p);
#if CBT_MOVE_CA_INSTEAD_OF_CLK
EXTERN void DramcCmdUIDelaySetting(DRAMC_CTX_T *p, U8 value);
#endif
EXTERN void cbt_switch_freq(DRAMC_CTX_T *p, U8 freq);
EXTERN DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcModeRegInit_CATerm(DRAMC_CTX_T *p, U8 bWorkAround);
EXTERN void DramcPowerOnSequence(DRAMC_CTX_T *p);
EXTERN void Global_Option_Init(DRAMC_CTX_T *p);
EXTERN U16 u2DFSGetHighestFreq(DRAMC_CTX_T * p);
EXTERN void EnableDRAMModeRegWriteDBIAfterCalibration(DRAMC_CTX_T *p);
EXTERN void EnableDRAMModeRegReadDBIAfterCalibration(DRAMC_CTX_T *p);
EXTERN void ApplyWriteDBIPowerImprove(DRAMC_CTX_T *p, U8 onoff);
EXTERN void DramcHMR4_Presetting(DRAMC_CTX_T *p);
EXTERN void DramcEnablePerBankRefresh(DRAMC_CTX_T *p, bool en);
EXTERN void RXPICGSetting(DRAMC_CTX_T * p);
EXTERN void TXPICGNewModeEnable(DRAMC_CTX_T * p);
EXTERN unsigned int DDRPhyFreqMeter(void);
#ifndef DPM_CONTROL_AFTERK
EXTERN void dramc_exit_with_DFS_legacy_mode(DRAMC_CTX_T * p);
#endif
/*
****************************************************************************************
** dramc_pi_calibration_api.c
****************************************************************************************
*/
EXTERN U16 gu2MR0_Value[RANK_MAX]; //read only mode register
EXTERN U32 gDramcSwImpedanceResult[IMP_VREF_MAX][IMP_DRV_MAX]; //ODT_ON/OFF x DRVP/DRVN/ODTP/ODTN
EXTERN U16 u2g_num_dlycell_perT_all[DRAM_DFS_SHUFFLE_MAX][CHANNEL_NUM]; //TODO: to be removed by Francis
EXTERN U16 u2gdelay_cell_ps_all[DRAM_DFS_SHUFFLE_MAX][CHANNEL_NUM]; //TODO: to be removed by Francis
EXTERN U16 u2gdelay_cell_ps;
EXTERN U8 gCBT_VREF_RANGE_SEL;
EXTERN U32 u4gVcore[DRAM_DFS_SHUFFLE_MAX];
EXTERN U8 uiLPDDR4_O1_Mapping_POP[CHANNEL_NUM][16];
EXTERN const U8 uiLPDDR4_O1_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16];
EXTERN U8 uiLPDDR4_CA_Mapping_POP[CHANNEL_NUM][6];
EXTERN const U8 uiLPDDR4_CA_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][6];
#if __ETT__
EXTERN U8 gETT_WHILE_1_flag;
#endif
#ifdef FOR_HQA_REPORT_USED
extern U8 gHQALog_flag;
extern U16 gHQALOG_RX_delay_cell_ps_075V;
#endif
#ifdef FOR_HQA_TEST_USED
EXTERN U16 gFinalCBTVrefCA[CHANNEL_NUM][RANK_MAX];
EXTERN U16 gFinalCBTCA[CHANNEL_NUM][RANK_MAX][10];
EXTERN U16 gFinalRXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH];
EXTERN U16 gFinalTXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH];
EXTERN U16 gFinalTXPerbitWin_min_max[CHANNEL_NUM][RANK_MAX];
EXTERN U16 gFinalTXPerbitWin_min_margin[CHANNEL_NUM][RANK_MAX];
EXTERN U16 gFinalTXPerbitWin_min_margin_bit[CHANNEL_NUM][RANK_MAX];
EXTERN S8 gFinalClkDuty[CHANNEL_NUM];
EXTERN U32 gFinalClkDutyMinMax[CHANNEL_NUM][2];
EXTERN S8 gFinalDQSDuty[CHANNEL_NUM][DQS_NUMBER];
EXTERN U32 gFinalDQSDutyMinMax[CHANNEL_NUM][DQS_NUMBER][2];
#endif
EXTERN U8 u1MR01Value[FSP_MAX];
EXTERN U8 u1MR02Value[FSP_MAX];
EXTERN U8 u1MR03Value[FSP_MAX];
EXTERN U8 u1MR11Value[FSP_MAX];
EXTERN U8 u1MR18Value[FSP_MAX];
EXTERN U8 u1MR19Value[FSP_MAX];
EXTERN U8 u1MR20Value[FSP_MAX];
EXTERN U8 u1MR21Value[FSP_MAX];
EXTERN U8 u1MR22Value[FSP_MAX];
EXTERN U8 u1MR51Value[FSP_MAX];
EXTERN U8 u1MR04Value[RANK_MAX];
EXTERN U8 u1MR13Value[RANK_MAX];
EXTERN U8 u1MR26Value[RANK_MAX];
EXTERN U8 u1MR30Value[RANK_MAX];
EXTERN U8 u1MR12Value[CHANNEL_NUM][RANK_MAX][FSP_MAX];
EXTERN U8 u1MR14Value[CHANNEL_NUM][RANK_MAX][FSP_MAX];
#if PINMUX_AUTO_TEST_PER_BIT_RX
EXTERN U8 gRX_check_per_bit_flag;
EXTERN S16 gFinalRXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH];
#endif
#if PINMUX_AUTO_TEST_PER_BIT_TX
EXTERN U8 gTX_check_per_bit_flag;
EXTERN S16 gFinalTXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH];
#endif
EXTERN U8 u1IsLP4Div4DDR800(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 u1VrefScanEnable, u8 isAutoK);
EXTERN DRAM_STATUS_T DramcZQCalibration(DRAMC_CTX_T *p, U8 rank);
EXTERN DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok);
EXTERN DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T stDelayBase);
EXTERN DRAM_STATUS_T dramc_rx_dqs_gating_cal(DRAMC_CTX_T *p, u8 autok, U8 use_enhanced_rdqs);
EXTERN DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, RX_PATTERN_OPTION_T eRxPattern,
U8 *u1AssignedVref, u8 isAutoK);
EXTERN DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcSwImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_region);
EXTERN void DramcSwImpedanceSaveRegister(DRAMC_CTX_T *p, U8 ca_freq_option, U8 dq_freq_option, U8 save_to_where);
EXTERN void vBeforeCalibration(DRAMC_CTX_T *p);
EXTERN void vAfterCalibration(DRAMC_CTX_T *p);
EXTERN void DramcRunTimeConfig(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcMiockJmeter(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcDutyCycleMonitor(DRAMC_CTX_T *p);
EXTERN void DramcTxOECalibration(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p);
EXTERN void LP4_ShiftDQS_OENUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx);
EXTERN void ShiftDQ_OENUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx);
EXTERN void DramcMiockJmeterHQA(DRAMC_CTX_T *p);
EXTERN U8 u1IsPhaseMode(DRAMC_CTX_T *p);
EXTERN void RODTSettings(DRAMC_CTX_T *p);
EXTERN void DQSSTBSettings(DRAMC_CTX_T *p);
EXTERN void DramcWriteShiftMCKForWriteDBI(DRAMC_CTX_T *p, S8 iShiftMCK);
EXTERN void DramPhyReset(DRAMC_CTX_T *p);
EXTERN U32 DramcRxWinRDDQCInit(DRAMC_CTX_T *p);
EXTERN U32 DramcRxWinRDDQCRun(DRAMC_CTX_T *p);
EXTERN U32 DramcRxWinRDDQCEnd(DRAMC_CTX_T *p);
#if BYPASS_CALIBRATION
EXTERN void dle_factor_handler(DRAMC_CTX_T *p, U8 curr_val);
EXTERN void ShiftDQSWCK_UI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx);
EXTERN void ShiftDQUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx);
EXTERN void TXSetDelayReg_DQ(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdqm_ui_large[], U8 ucdqm_oen_ui_large[], U8 ucdqm_ui_small[], U8 ucdqm_oen_ui_small[], U8 ucdqm_pi[]);
EXTERN void TXSetDelayReg_DQM(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdqm_ui_large[], U8 ucdqm_oen_ui_large[], U8 ucdqm_ui_small[], U8 ucdqm_oen_ui_small[], U8 ucdqm_pi[]);
EXTERN void TXUpdateTXTracking(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 ucdq_pi[], U8 ucdqm_pi[]);
EXTERN void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p);
EXTERN void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p);
#endif
EXTERN void vInitGlobalVariablesByCondition(DRAMC_CTX_T *p);
EXTERN void DramcDramcRxDVSCalPostProcess(DRAMC_CTX_T *p);
EXTERN void CBTDelayCACLK(DRAMC_CTX_T *p, S32 iDelay);
#if __FLASH_TOOL_DA__
EXTERN void vPrintPinInfoResult(DRAMC_CTX_T *p);
EXTERN DEBUG_PIN_INF_FOR_FLASHTOOL_T PINInfo_flashtool;
#endif
/*
****************************************************************************************
** dramc_pi_main.c
****************************************************************************************
*/
EXTERN DRAMC_CTX_T gTimeProfilingDramCtx;
EXTERN U8 gHQA_Test_Freq_Vcore_Level;
#if (FOR_DV_SIMULATION_USED == 1)
EXTERN U8 gu1BroadcastIsLP4;
#endif
EXTERN bool gAndroid_DVFS_en;
EXTERN bool gUpdateHighestFreq;
EXTERN DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SHUFFLE_MAX];
EXTERN void dump_dramc_ctx(DRAMC_CTX_T *p);
#ifdef ENABLE_MIOCK_JMETER
EXTERN void PRE_MIOCK_JMETER_HQA_USED(DRAMC_CTX_T *p);
#endif
EXTERN void vCalibration_Flow_For_MDL(DRAMC_CTX_T *p);
EXTERN void vDramCalibrationAllChannel(DRAMC_CTX_T *p);
EXTERN U32 vGetVoltage(DRAMC_CTX_T *p, U32 get_voltage_type);
/*
****************************************************************************************
** dramc_slt.c
****************************************************************************************
*/
#if ENABLE_EMI_LPBK_TEST
EXTERN U8 gEmiLpbkTest;
#endif
EXTERN void SLT_DramcDFS(DRAMC_CTX_T *p, int iDoDMA);
EXTERN void SLT_DFSTestProgram(DRAMC_CTX_T *p, int iDoDMA);
EXTERN void SLT_Test_DFS_and_Memory_Test(DRAMC_CTX_T*p);
/*
****************************************************************************************
** dramc_temp_function.c
****************************************************************************************
*/
EXTERN DRAMC_CTX_T DramCtx_LPDDR4;
/*
****************************************************************************************
** dramc_tracking.c
****************************************************************************************
*/
EXTERN U8 gu1MR23[CHANNEL_NUM][RANK_MAX];
EXTERN void DramcHWGatingInit(DRAMC_CTX_T *p);
EXTERN void DramcHWGatingOnOff(DRAMC_CTX_T *p, U8 u1OnOff);
EXTERN void DramcHWGatingDebugOnOff(DRAMC_CTX_T *p, U8 u1OnOff);
EXTERN void DramcPrintHWGatingStatus(DRAMC_CTX_T *p, U8 u1Channel);
#if (ENABLE_TX_TRACKING || TDQSCK_PRECALCULATION_FOR_DVFS)
EXTERN void FreqJumpRatioCalculation(DRAMC_CTX_T *p);
#endif
#if TDQSCK_PRECALCULATION_FOR_DVFS
EXTERN void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p);
EXTERN void DramcDQSPrecalculation_enable(DRAMC_CTX_T *p);
#endif
EXTERN void DramcDQSOSCInit(void);
EXTERN DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p);
#if ENABLE_TX_TRACKING
EXTERN DRAM_STATUS_T DramcDQSOSCMR23(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcDQSOSCSetMR18MR19(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p);
EXTERN void DramcHwDQSOSC(DRAMC_CTX_T *p);
EXTERN void Enable_TX_Tracking(DRAMC_CTX_T *p, U32 u4DramcShuOffset);
#endif
#if RDSEL_TRACKING_EN
EXTERN void Enable_RDSEL_Tracking(DRAMC_CTX_T *p, U32 u4DramcShuOffset);
EXTERN void RDSELRunTimeTracking_preset(DRAMC_CTX_T *p);
#endif
#ifdef HW_GATING
EXTERN void Enable_Gating_Tracking(DRAMC_CTX_T *p, U32 u4DramcShuOffset);
#endif
EXTERN void DramcImpedanceHWSaving(DRAMC_CTX_T *p);
EXTERN void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p);
EXTERN void DramcRxInputDelayTrackingInit_Common(DRAMC_CTX_T *p);
EXTERN void DramcRxInputDelayTrackingHW(DRAMC_CTX_T *p);
EXTERN void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p);
/*
****************************************************************************************
** dramc_utility.c
****************************************************************************************
*/
EXTERN U16 gddrphyfmeter_value;
#if FOR_DV_SIMULATION_USED
EXTERN U8 u1BroadcastOnOff;
#endif
#if (fcFOR_CHIP_ID == fcA60868)
EXTERN U8 u1EnterRuntime;
#endif
EXTERN U8 u1MaType;
EXTERN void TA2_Test_Run_Time_HW_Set_Column_Num(DRAMC_CTX_T * p);
EXTERN void TA2_Test_Run_Time_HW_Presetting(DRAMC_CTX_T * p, U32 len, TA2_RKSEL_TYPE_T rksel_mode);
EXTERN void TA2_Test_Run_Time_Pat_Setting(DRAMC_CTX_T *p, U8 PatSwitch);
EXTERN void TA2_Test_Run_Time_HW_Write(DRAMC_CTX_T * p, U8 u1Enable);
EXTERN U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p);
EXTERN void TA2_Test_Run_Time_HW(DRAMC_CTX_T * p);
EXTERN void vAutoRefreshSwitch(DRAMC_CTX_T *p, U8 option);
EXTERN void vSetRank(DRAMC_CTX_T *p, U8 ucRank);
EXTERN void vSetPHY2ChannelMapping(DRAMC_CTX_T *p, U8 u1Channel);
EXTERN VREF_CALIBRATION_ENABLE_T Get_Vref_Calibration_OnOff(DRAMC_CTX_T *p);
EXTERN u8 lp5heff_save_disable(DRAMC_CTX_T *p);
EXTERN void lp5heff_restore(DRAMC_CTX_T *p);
EXTERN u8 is_lp5_family(DRAMC_CTX_T *p);
EXTERN U32 GetDramcBroadcast(void);
EXTERN void CKEFixOnOff(DRAMC_CTX_T *p, U8 u1RankIdx, CKE_FIX_OPTION option,
CKE_FIX_CHANNEL WriteChannelNUM);
EXTERN void DramcBackupRegisters(DRAMC_CTX_T *p, U32 *backup_addr, U32 backup_num);
EXTERN U8 u1GetRank(DRAMC_CTX_T *p);
EXTERN void vPrintCalibrationBasicInfo(DRAMC_CTX_T *p);
EXTERN void vPrintCalibrationBasicInfo_ForJV(DRAMC_CTX_T *p);
EXTERN U32 DramcEngine2Run(DRAMC_CTX_T *p, DRAM_TE_OP_T wr, U8 testaudpat);
EXTERN void DramcEngine2End(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcEngine2Init(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1TestPat, U8 u1LoopCnt, U8 u1EnableUiShift);
EXTERN void DramcRestoreRegisters(DRAMC_CTX_T *p, U32 *restore_addr, U32 restore_num);
EXTERN DDR800_MODE_T vGet_DDR_Loop_Mode(DRAMC_CTX_T *p);
EXTERN u8 is_heff_mode(DRAMC_CTX_T *p);
EXTERN void DramcEngine2SetPat(DRAMC_CTX_T *p, U8 u1TestPat, U8 u1LoopCnt, U8 u1Len1Flag, U8 u1EnableUiShift);
EXTERN void DramcSetRankEngine2(DRAMC_CTX_T *p, U8 u1RankSel);
EXTERN U16 GetFreqBySel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel);
EXTERN U8 GetEyeScanEnable(DRAMC_CTX_T * p, U8 get_type);
EXTERN U8 vGetPHY2ChannelMapping(DRAMC_CTX_T *p);
EXTERN DUTY_CALIBRATION_T Get_Duty_Calibration_Mode(DRAMC_CTX_T *p);
EXTERN void DDRPhyFreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel);
EXTERN DRAM_DFS_SRAM_SHU_T vGet_Current_ShuLevel(DRAMC_CTX_T *p);
EXTERN void vSetChannelNumber(DRAMC_CTX_T *p);
EXTERN void vSetRankNumber(DRAMC_CTX_T *p);
EXTERN void vSetFSPNumber(DRAMC_CTX_T *p);
EXTERN void vCKERankCtrl(DRAMC_CTX_T *p, CKE_CTRL_MODE_T CKECtrlMode);
EXTERN DRAM_PLL_FREQ_SEL_T vGet_PLL_FreqSel(DRAMC_CTX_T *p);
EXTERN void vSet_PLL_FreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel);
EXTERN void Temp_TA2_Test_After_K(DRAMC_CTX_T * p);
EXTERN void DramcBroadcastOnOff(U32 bOnOff);
EXTERN DIV_MODE_T vGet_Div_Mode(DRAMC_CTX_T *p);
EXTERN void DramcMRWriteFldMsk(DRAMC_CTX_T *p, U8 mr_idx, U8 listValue, U8 msk, U8 UpdateMode);
EXTERN void DramcMRWriteFldAlign(DRAMC_CTX_T *p, U8 mr_idx, U8 value, U32 mr_fld, U8 UpdateMode);
EXTERN void DramcModeRegReadByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U16 *u2pValue);
EXTERN void DramcModeRegRead(DRAMC_CTX_T *p, U8 u1MRIdx, U16 *u1pValue);
EXTERN void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value);
EXTERN void SetDramModeRegForWriteDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff);
EXTERN void SetDramModeRegForReadDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff);
#if MRW_CHECK_ONLY
EXTERN void vPrintFinalModeRegisterSetting(DRAMC_CTX_T *p);
#endif
#if MRW_BACKUP
EXTERN U8 DramcMRWriteBackup(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Rank);
#endif
#if QT_GUI_Tool
EXTERN void TA2_Test_Run_Time_SW_Presetting(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 testaudpat, U8 log2loopcount);
EXTERN U32 TestEngineCompare(DRAMC_CTX_T *p);
#endif
EXTERN void vSet_Div_Mode(DRAMC_CTX_T *p, DIV_MODE_T eMode);
EXTERN void vSet_Current_ShuLevel(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T u1ShuIndex);
EXTERN void GetPhyPllFrequency(DRAMC_CTX_T *p);
EXTERN void DramcWriteDBIOnOff(DRAMC_CTX_T *p, U8 onoff);
EXTERN void DramcReadDBIOnOff(DRAMC_CTX_T *p, U8 onoff);
EXTERN void CheckDramcWBR(U32 u4address);
EXTERN void DramcModeRegWriteByRank_RTMRW(DRAMC_CTX_T *p, U8 *u1Rank, U8 *u1MRIdx, U8 *u1Value, U8 u1Len);
#if PRINT_CALIBRATION_SUMMARY
EXTERN void vPrintCalibrationResult(DRAMC_CTX_T *p);
#endif
EXTERN int dramc_complex_mem_test (unsigned int start, unsigned int len);
EXTERN U16 DDRPhyFMeter(void);
#ifdef DDR_INIT_TIME_PROFILING
void TimeProfileBegin(void);
UINT32 TimeProfileEnd(void);
#endif
/*
****************************************************************************************
** Hal_IO.cpp
****************************************************************************************
*/
#ifdef DUMP_INIT_RG_LOG_TO_DE
EXTERN U8 gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag;
#endif
/*
****************************************************************************************
** dramc_utility.cpp
****************************************************************************************
*/
#if (QT_GUI_Tool == 1)
EXTERN MCK_TO_UI_SHIFT_T u1Lp5MCK2WCKUI_DivShift(DRAMC_CTX_T *p);
#endif
/*
****************************************************************************************
** dramc_debug.cpp
****************************************************************************************
*/
extern void HQA_Log_Message_for_Report(DRAMC_CTX_T *p, U8 u1ChannelIdx, U8 u1RankIdx, U32 who_am_I, U8 *main_str, U8 *main_str2, U8 byte_bit_idx, S32 value1, U8 *ans_str);
/*
****************************************************************************************
** dramc_utility_QT.cpp
****************************************************************************************
*/
#if (QT_GUI_Tool == 1)
EXTERN void QT_DRAMCTX_INIT(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcDDRPHYInit_FPGA_A60868(DRAMC_CTX_T *p);
EXTERN DRAM_STATUS_T DramcDDRPHYInit_LP5_FPGA_A60868(DRAMC_CTX_T *p);
EXTERN void TA2_Stress_Test(DRAMC_CTX_T *p);
EXTERN void TA2_Stress_Test_2(DRAMC_CTX_T *p);
EXTERN U32 QT_TestEngineCompare(DRAMC_CTX_T *p);
EXTERN void Write_Byte_Counter_Begin(DRAMC_CTX_T *p);
EXTERN U32 Write_Byte_Counter_End(DRAMC_CTX_T *p);
EXTERN void DDRPhyFMeter_Init(DRAMC_CTX_T *p);
EXTERN U32 DDRPhyFreqMeter(void);
#endif
/*
****************************************************************************************
** fake_engine.c
****************************************************************************************
*/
/*
****************************************************************************************
** low_power_test.c
****************************************************************************************
*/
EXTERN int global_which_test;
EXTERN void EnableDramcPhyDCMShuffle(DRAMC_CTX_T *p, bool bEn, U32 u4DramcShuOffset, U32 u4DDRPhyShuOffset);
EXTERN void Enter_Precharge_All(DRAMC_CTX_T *p);
EXTERN void EnableDramcPhyDCM(DRAMC_CTX_T *p, bool bEn);
EXTERN DRAM_STATUS_T CheckGoldenSetting(DRAMC_CTX_T *p);
EXTERN void Low_Power_Scenarios_Test(DRAMC_CTX_T *p);
#if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION
void DDR800semiPowerSavingOn(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff);
#endif
#define LOW_POWER_SCENARIO_PRECHARGE_ALL 3 //idle(all bank refresh)
#define LOW_POWER_SCENARIO_S1 5
#define LOW_POWER_SCENARIO_S0 6
#define LOW_POWER_SCENARIO_PASR 7
#define LOW_POWER_SCENARIO_ALL 8
#define LOW_POWER_SCENARIO_FAKE_ENGINE_READ 9
#define LOW_POWER_SCENARIO_FAKE_ENGINE_WRITE 10
#define LOW_POWER_SCENARIO_ONLY_SELF_REFRESH 12
#define LOW_POWER_SCENARIO_HW_AUTO_SAVE_S0 13
#define LOW_POWER_SCENARIO_HW_AUTO_SAVE_S0_METHOD_2 14
#define LOW_POWER_SCENARIO_PASR_1BANK 15
#define LOW_POWER_SCENARIO_PASR_2BANK 16
#define LOW_POWER_SCENARIO_PASR_4BANK 17
#define LOW_POWER_SCENARIO_PASR_8BANK 18
#define LOW_POWER_SCENARIO_FAKE_ENGINE_BW 19
#define LOW_POWER_SCENARIO_FAKE_ENGINE_READ_WRITE 21
#define AUTO_REFRESH_RESERVE_TEST 22
/*
****************************************************************************************
** low_power_test.c
****************************************************************************************
*/
EXTERN U8 u1StopMiniStress;
EXTERN void Ett_Mini_Strss_Test(DRAMC_CTX_T *p);
/*
****************************************************************************************
** LP4_dram_init.c
****************************************************************************************
*/
EXTERN void CKE_FIX_ON(DRAMC_CTX_T *p, U8 EN, U8 rank);
EXTERN void LP4_UpdateInitialSettings(DRAMC_CTX_T *p);
EXTERN void LP4_DRAM_INIT(DRAMC_CTX_T *p);
/*
****************************************************************************************
** LP5_dram_init.c
****************************************************************************************
*/
EXTERN void LP5_UpdateInitialSettings(DRAMC_CTX_T *p);
EXTERN void LP5_DRAM_INIT(DRAMC_CTX_T *p);
/*
****************************************************************************************
** system_init.c
****************************************************************************************
*/
#if (fcFOR_CHIP_ID == fcA60868)
EXTERN void syspll_init(DRAMC_CTX_T *p);
#endif
/*
****************************************************************************************
** dramc_utility_QT.cpp
****************************************************************************************
*/
#if (QT_GUI_Tool == 1)
EXTERN U8 ucDramRegRead_1(U32 reg_addr, U32 *reg_data);
EXTERN U8 ucDramRegWrite_1(U32 reg_addr, U32 reg_data);
#endif
/*
****************************************************************************************
** svsim_dummy.c
****************************************************************************************
*/
#if (FOR_DV_SIMULATION_USED == 0)
#define delay_us(x)
#define delay_ns(x)
#define mysetscope()
#define broadcast_on()
#define broadcast_off()
#define timestamp_show()
#define build_api_initial()
#define conf_to_sram_sudo(...)
#endif
/*
****************************************************************************************
** RS232.cpp
****************************************************************************************
*/
#if (QT_GUI_Tool == 1)
EXTERN U8 ucDramSetReg_1(U32 address, U32 *data, U16 count);
EXTERN U8 ucDramGetReg_1(U32 address, U32 *data, U16 count);
#endif
/*
****************************************************************************************
** ett_test.c
****************************************************************************************
*/
extern int hqa_vmddr_voltage, hqa_vmddr_class;
#endif //_INT_GLOBAL_H

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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef _INT_SLT_H
#define _INT_SLT_H
//======================== EMI LPBK TEST Definition =====================================
#if defined(SLT)
#define ENABLE_EMI_LPBK_TEST 1
#else
#define ENABLE_EMI_LPBK_TEST 0
#endif
#define EMI_LPBK_DRAM_USED !ENABLE_EMI_LPBK_TEST // 0: EMI LPBK test, 1: normal K, dram used
#define EMI_LPBK_USE_THROUGH_IO 0 //test through IO
#define EMI_INT_LPBK_WL_DQS_RINGCNT 0 //DQS Ring cnt: through io @ 800,1600,2400,3200, emi intlpbk wo rx/tx K window
#define EMI_LPBK_ADDRESS_DEFECT 0 //test address defect, MUST use CPU WRITE mode
#if ENABLE_EMI_LPBK_TEST
#define EMI_USE_TA2 0 // 0:CPU write, 1:TA2, DVsim/Dsim use TA2, but 1:4 mode must use cpu write(because TA2 not support 1:4 mode)
#else
#define EMI_USE_TA2 0
#endif
/****************************
Summary:
1W1R: address offset : 0, 4, 8, c (1:8 mode only), no support 1:4 mode
8W1R: address offset 0x0 ~ 0xC (8W1R), 0x10 ~ 0x1C, (10W1R) (1:8 & 1:4 mode)
****************************/
#define EMI_LPBK_1W1R 0 //CPU mode 0:8W1R, 1:1W1R
#define EMI_LPBK_S1 0
#define FREQ_METER 1
#define DQSG_COUNTER 1
#define ADJUST_TXDLY_SCAN_RX_WIN 0
#define EMI_LPBK_K_TX 0
#define ENABLE_PRE_POSTAMBLE !EMI_USE_TA2 //0: no pre/post-amble for TA2, 1: need pre/post-amble for cpu write
#define EMI_LPBK_DFS_32 0 //DFS 32<->32<->32
#define EMI_LPBK_DFS_24 0 //DFS 24<->24<->24
#define EMI_LPBK_DFS_16 0 //DFS 16<->16<->16
#define EMI_LPBK_USE_LP3_PINMUX 0
#define EMI_LPBK_8W1R 1
#if EMI_LPBK_1W1R
#undef EMI_LPBK_8W1R
#define EMI_LPBK_8W1R 0
#endif
#if EMI_LPBK_USE_THROUGH_IO
#define EMI_LPBK_USE_DDR_800 1
#else
#define EMI_LPBK_USE_DDR_800 0
#endif
//#define K_TX_DQS_DLY 0
#define LP4_4266_freq_meter 533 // //shu0 533
#define LP4_3733_freq_meter 464 // //shu0 464
#define LP4_3200_freq_meter 386 // //shu8 386 //shu9 386
#define LP4_2400_freq_meter 299 //shu6 299 shu5 299
#define LP4_1600_freq_meter 191 //199 //shu4 383 shu3 191
#define LP4_1200_freq_meter 299 //shu2 299 shu1 299
#define LP4_800_freq_meter 199 //shu7 199
#if ENABLE_EMI_LPBK_TEST //EMI_LPBK_DRAM_USED==0
/*
#define SLT
#undef ENABLE_TMRRI_NEW_MODE
#define ENABLE_TMRRI_NEW_MODE 0
#undef ENABLE_DUTY_SCAN_V2
#define ENABLE_DUTY_SCAN_V2 0
#undef ENABLE_RODT_TRACKING
#define ENABLE_RODT_TRACKING 0
#undef TX_K_DQM_WITH_WDBI
#define TX_K_DQM_WITH_WDBI 0
#undef ENABLE_WRITE_DBI
#define ENABLE_WRITE_DBI 0
*/
#if EMI_INT_LPBK_WL_DQS_RINGCNT
#undef EMI_LPBK_USE_THROUGH_IO
#define EMI_LPBK_USE_THROUGH_IO 1
#undef EMI_LPBK_USE_DDR_800
#define EMI_LPBK_USE_DDR_800 0
#endif
#endif
//#if (EMI_LPBK_DRAM_USED)
//#undef ENABLE_MIOCK_JMETER
//#define ENABLE_MIOCK_JMETER // for TX_PER_BIT_DELAY_CELL
//#endif
//=============================================================================
#endif //_INT_GLOBAL_H

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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef __REG_BASE_ADDR__
#define __REG_BASE_ADDR__
#include "soc/addressmap.h"
#include "emi_hw.h"
#ifndef __ETT__
#define __ETT__ 0
#endif
//#define DRAM_BASE 0x40000000ULL
//#define DDR_BASE DRAM_BASE
#define CQ_DMA_BASE (IO_PHYS + 0x212000)
//#define CKSYS_BASE IO_PHYS
//#define EMI_APB_BASE 0x10219000
//#define EMI_BASE EMI_APB_BASE
//#define EMI_MPU_BASE 0x10226000
#define CHN0_EMI_BASE (IO_PHYS + 0x235000)
#define CHN1_EMI_BASE (IO_PHYS + 0x245000)
#define INFRA_DRAMC_REG_CONFIG (INFRACFG_AO_BASE + 0xB4)
//#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
//#define APMIXED_BASE (IO_PHYS + 0x0000C000)
#define MPLL_CON0 (APMIXED_BASE + 0x390)
#define MPLL_CON1 (APMIXED_BASE + 0x394)
#define MPLL_CON3 (APMIXED_BASE + 0x39C)
#define PLLON_CON0 (APMIXED_BASE + 0x050)
#define PLLON_CON1 (APMIXED_BASE + 0x054)
#define PLLON_CON2 (APMIXED_BASE + 0x058)
#define PLLON_CON3 (APMIXED_BASE + 0x05C)
/* TOPCKGEN Register */
#define CLK_MISC_CFG_0 (CKSYS_BASE + 0x104)
#define CLK_MISC_CFG_1 (CKSYS_BASE + 0x108)
#define CLK_DBG_CFG (CKSYS_BASE + 0x10C)
#define CLK26CALI_0 (CKSYS_BASE + 0x220)
#define CLK26CALI_1 (CKSYS_BASE + 0x224)
#endif //__REG_BASE_ADDR__

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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef _A60868_REGISTER_H_
#define _A60868_REGISTER_H_
#include "dramc_pi_api.h"
#define POS_BANK_NUM 16 // SW Virtual base address position
#if (fcFOR_CHIP_ID == fcMargaux)
#include "Margaux_Register_DDRPHY_MD32.h"
#include "Margaux_Register_DDRPHY_NAO.h"
#include "Margaux_Register_DDRPHY_AO.h"
#include "Margaux_Register_DRAMC_AO.h"
#include "Margaux_Register_DRAMC_NAO.h"
#else
#include "Register_DDRPHY_MD32.h"
#include "Register_DDRPHY_NAO.h"
#include "Register_DDRPHY_AO.h"
#include "Register_DRAMC_AO.h"
#include "Register_DRAMC_NAO.h"
#include "Register_SYSTEM.h"
#endif
// SW Virtual base address
#define Channel_A_DRAMC_NAO_BASE_VIRTUAL 0x40000
#define Channel_B_DRAMC_NAO_BASE_VIRTUAL 0x50000
#define Channel_A_DRAMC_AO_BASE_VIRTUAL 0x60000
#define Channel_B_DRAMC_AO_BASE_VIRTUAL 0x70000
#define Channel_A_DDRPHY_NAO_BASE_VIRTUAL 0x80000
#define Channel_B_DDRPHY_NAO_BASE_VIRTUAL 0x90000
#define Channel_A_DDRPHY_AO_BASE_VIRTUAL 0xa0000
#define Channel_B_DDRPHY_AO_BASE_VIRTUAL 0xb0000
#define Channel_A_DDRPHY_DPM_BASE_VIRTUAL 0xc0000
#define MAX_BASE_VIRTUAL 0xd0000
#define DRAMC_WBR 0x100010B4
#if (CHANNEL_NUM==4)
#define DRAMC_BROADCAST_ON 0x27f7f //4CH
#else
#define DRAMC_BROADCAST_ON 0x7f //2CH
#endif
#define DRAMC_BROADCAST_OFF 0x0
//Definitions indicating DRAMC, DDRPHY register shuffle offset
#define SHU_GRP_DRAMC_OFFSET 0x700
#define SHU_GRP_DDRPHY_OFFSET 0x700
#define DRAMC_REG_AO_SHU_OFFSET (0x700)
#define DRAMC_REG_AO_RANK_OFFSET (0x200)
#define DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR (DRAMC_REG_RK_TEST2_A1 - DRAMC_AO_BASE_ADDRESS) // 0x0500
#define DRAMC_REG_AO_RANK0_WO_SHUFFLE_END_ADDR (DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR + DRAMC_REG_AO_RANK_OFFSET)
#define DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR (DRAMC_REG_SHURK_SELPH_DQ0 - DRAMC_AO_BASE_ADDRESS) // 0x1200
#define DRAMC_REG_AO_RANK0_W_SHUFFLE0_END_ADDR (DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR + DRAMC_REG_AO_RANK_OFFSET)
#define DRAMC_REG_AO_SHUFFLE0_BASE_ADDR (DRAMC_REG_SHURK_SELPH_DQ0 - DRAMC_AO_BASE_ADDRESS) // 0x1200
#define DRAMC_REG_AO_SHUFFLE0_END_ADDR (DRAMC_REG_SHU_ACTIM7 - DRAMC_AO_BASE_ADDRESS) // 0x16E8
#define DDRPHY_AO_B0_B1_OFFSET (0x180)
#define DDRPHY_AO_SHU_OFFSET (0x700)
#define DDRPHY_AO_RANK_OFFSET (0x80)
#define DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR (DDRPHY_REG_RK_B0_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x0060
#define DDRPHY_AO_RANK0_B0_NON_SHU_END_ADDR (DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
#define DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR (DDRPHY_REG_RK_B1_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x01E0
#define DDRPHY_AO_RANK0_B1_NON_SHU_END_ADDR (DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
#define DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR (DDRPHY_REG_RK_CA_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x0360
#define DDRPHY_AO_RANK0_CA_NON_SHU_END_ADDR (DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
#define DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR (DDRPHY_REG_SHU_R0_B0_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x0760
#define DDRPHY_AO_RANK0_B0_SHU0_END_ADDR (DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
#define DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR (DDRPHY_REG_SHU_R0_B1_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x08E0
#define DDRPHY_AO_RANK0_B1_SHU0_END_ADDR (DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
#define DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR (DDRPHY_REG_SHU_R0_CA_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x0A60
#define DDRPHY_AO_RANK0_CA_SHU0_END_ADDR (DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
#define DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR (DDRPHY_REG_MISC_SHU_RK_DQSCTL - DDRPHY_AO_BASE_ADDRESS) // 0x0BE0
#define DDRPHY_AO_RANK0_MISC_SHU0_END_ADDR (DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET)
#define DDRPHY_AO_SHUFFLE0_BASE_ADDR (DDRPHY_REG_SHU_PHYPLL0 - DDRPHY_AO_BASE_ADDRESS) // 0x700
#define DDRPHY_AO_SHUFFLE0_END_ADDR (DDRPHY_REG_MISC_SHU_CG_CTRL0 - DDRPHY_AO_BASE_ADDRESS) // 0xDA4
#define DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET (0x20)
#define DDRPHY_NAO_GATING_STATUS_RK_OFFSET (0x10)
#define DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START (DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0600
#define DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_END (DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET)
#define DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START (DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0640
#define DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_END (DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET)
#define DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START (DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0680
#define DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_END (DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET)
#define DDRPHY_NAO_RANK0_GATING_STATUS_START (DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0420
#define DDRPHY_NAO_RANK0_GATING_STATUS_END (DDRPHY_NAO_RANK0_GATING_STATUS_START + DDRPHY_NAO_GATING_STATUS_RK_OFFSET)
#define DRAMC_REG_NAO_RANK_OFFSET (0x200)
#define DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR (DRAMC_REG_MR_BACKUP_00_RK0_FSP0 - DRAMC_NAO_BASE_ADDRESS) // 0x0900
#define DRAMC_REG_NAO_RANK0_ROW_OFFSET_END_ADDR (DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR + DRAMC_REG_NAO_RANK_OFFSET)
// HW Physical base address
#if defined(__MD32__)
/* MD32 address */
#undef Channel_A_DRAMC_AO_BASE_ADDRESS
#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x300A2000
#undef Channel_B_DRAMC_AO_BASE_ADDRESS
#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x300B2000
#undef Channel_C_DRAMC_AO_BASE_ADDRESS
#define Channel_C_DRAMC_AO_BASE_ADDRESS 0x0
#undef Channel_D_DRAMC_AO_BASE_ADDRESS
#define Channel_D_DRAMC_AO_BASE_ADDRESS 0x0
#undef Channel_A_DRAMC_NAO_BASE_ADDRESS
#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x300A8000
#undef Channel_B_DRAMC_NAO_BASE_ADDRESS
#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x300B8000
#undef Channel_C_DRAMC_NAO_BASE_ADDRESS
#define Channel_C_DRAMC_NAO_BASE_ADDRESS 0x0
#undef Channel_D_DRAMC_NAO_BASE_ADDRESS
#define Channel_D_DRAMC_NAO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_AO_BASE_ADDRESS
#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x300A6000
#undef Channel_B_DDRPHY_AO_BASE_ADDRESS
#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x300B6000
#undef Channel_C_DDRPHY_AO_BASE_ADDRESS
#define Channel_C_DDRPHY_AO_BASE_ADDRESS 0x0
#undef Channel_D_DDRPHY_AO_BASE_ADDRESS
#define Channel_D_DDRPHY_AO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x300AA000
#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x300BA000
#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
#define Channel_C_DDRPHY_NAO_BASE_ADDRESS 0x0
#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
#define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0x30040000
#elif (FOR_DV_SIMULATION_USED)
#undef Channel_A_DRAMC_AO_BASE_ADDRESS
#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x10000
#undef Channel_B_DRAMC_AO_BASE_ADDRESS
#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x40000
#undef Channel_C_DRAMC_AO_BASE_ADDRESS
#define Channel_C_DRAMC_AO_BASE_ADDRESS 0x0
#undef Channel_D_DRAMC_AO_BASE_ADDRESS
#define Channel_D_DRAMC_AO_BASE_ADDRESS 0x0
#undef Channel_A_DRAMC_NAO_BASE_ADDRESS
#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x20000
#undef Channel_B_DRAMC_NAO_BASE_ADDRESS
#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x50000
#undef Channel_C_DRAMC_NAO_BASE_ADDRESS
#define Channel_C_DRAMC_NAO_BASE_ADDRESS 0x0
#undef Channel_D_DRAMC_NAO_BASE_ADDRESS
#define Channel_D_DRAMC_NAO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_AO_BASE_ADDRESS
#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x30000
#undef Channel_B_DDRPHY_AO_BASE_ADDRESS
#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x60000
#undef Channel_C_DDRPHY_AO_BASE_ADDRESS
#define Channel_C_DDRPHY_AO_BASE_ADDRESS 0x0
#undef Channel_D_DDRPHY_AO_BASE_ADDRESS
#define Channel_D_DDRPHY_AO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x70000
#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x80000
#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
#define Channel_C_DDRPHY_NAO_BASE_ADDRESS 0x0
#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
#define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0xD0000 //@Darren, 0x90000 + 0x40000 for DV sim
#elif(HAPS_FPFG_A60868 ==0)
#undef Channel_A_DRAMC_AO_BASE_ADDRESS
#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x10230000
#undef Channel_B_DRAMC_AO_BASE_ADDRESS
#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x10240000
#undef Channel_C_DRAMC_AO_BASE_ADDRESS
#define Channel_C_DRAMC_AO_BASE_ADDRESS 0x10250000
#undef Channel_D_DRAMC_AO_BASE_ADDRESS
#define Channel_D_DRAMC_AO_BASE_ADDRESS 0x10260000
#undef Channel_A_DRAMC_NAO_BASE_ADDRESS
#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x10234000
#undef Channel_B_DRAMC_NAO_BASE_ADDRESS
#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x10244000
#undef Channel_C_DRAMC_NAO_BASE_ADDRESS
#define Channel_C_DRAMC_NAO_BASE_ADDRESS 0x10254000
#undef Channel_D_DRAMC_NAO_BASE_ADDRESS
#define Channel_D_DRAMC_NAO_BASE_ADDRESS 0x10264000
#undef Channel_A_DDRPHY_AO_BASE_ADDRESS
#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x10238000
#undef Channel_B_DDRPHY_AO_BASE_ADDRESS
#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x10248000
#undef Channel_C_DDRPHY_AO_BASE_ADDRESS
#define Channel_C_DDRPHY_AO_BASE_ADDRESS 0x10258000
#undef Channel_D_DDRPHY_AO_BASE_ADDRESS
#define Channel_D_DDRPHY_AO_BASE_ADDRESS 0x10268000
#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x10236000
#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x10246000
#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
#define Channel_C_DDRPHY_NAO_BASE_ADDRESS 0x10256000
#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
#define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x10266000
#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0x10940000
#undef Channel_B_DDRPHY_DPM_BASE_ADDRESS
#define Channel_B_DDRPHY_DPM_BASE_ADDRESS 0x10A40000
#else // A60868 FPGA Base Address
#undef Channel_A_DRAMC_AO_BASE_ADDRESS
#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x40000
#undef Channel_B_DRAMC_AO_BASE_ADDRESS
#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x0
#undef Channel_C_DRAMC_AO_BASE_ADDRESS
#define Channel_C_DRAMC_AO_BASE_ADDRESS 0x0
#undef Channel_D_DRAMC_AO_BASE_ADDRESS
#define Channel_D_DRAMC_AO_BASE_ADDRESS 0x0
#undef Channel_A_DRAMC_NAO_BASE_ADDRESS
#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x10000
#undef Channel_B_DRAMC_NAO_BASE_ADDRESS
#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x0
#undef Channel_C_DRAMC_NAO_BASE_ADDRESS
#define Channel_C_DRAMC_NAO_BASE_ADDRESS 0x0
#undef Channel_D_DRAMC_NAO_BASE_ADDRESS
#define Channel_D_DRAMC_NAO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_AO_BASE_ADDRESS
#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x70000
#undef Channel_B_DDRPHY_AO_BASE_ADDRESS
#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x0
#undef Channel_C_DDRPHY_AO_BASE_ADDRESS
#define Channel_C_DDRPHY_AO_BASE_ADDRESS 0x0
#undef Channel_D_DDRPHY_AO_BASE_ADDRESS
#define Channel_D_DDRPHY_AO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS
#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x80000
#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS
#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x0
#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS
#define Channel_C_DDRPHY_NAO_BASE_ADDRESS 0x0
#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS
#define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x0
#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS
#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0x100000
#undef Channel_B_DDRPHY_DPM_BASE_ADDRESS
#define Channel_B_DDRPHY_DPM_BASE_ADDRESS 0x0
#endif
#define CHK_INCLUDE_LOCAL_HEADER "\n ==> Include local header but not one at DV SERVER\n\n"
#endif // _A60868_REGISTER_H_

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src/vendorcode/mediatek/mt8192/include/dramc_top.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef __DRAMC_TOP_H__
#define __DRAMC_TOP_H__
#include "dramc_common.h"
#if !__ETT__
#if (FOR_DV_SIMULATION_USED==0)
//#define DDR_RESERVE_MODE
#define COMBO_MCP
//#define LAST_DRAMC
//#define VOLTAGE_SEL
//#define ENABLE_DOE
#endif
#endif
//#define DRAM_BASE 0x40000000ULL
//#define DDR_BASE DRAM_BASE
#if __ETT__
#define dramc_crit printf
#define dramc_debug printf
#elif __FLASH_TOOL_DA__
#define dramc_crit LOGD
#define dramc_debug LOGD
#else
#ifndef dramc_info
#define dramc_info print
#endif
#ifndef dramc_crit
#define dramc_crit print
#endif
#ifndef dramc_debug
#define dramc_debug printf
#endif
#endif
#define DRAMC_MAX_CH 2
#define DRAMC_MAX_RK 2
#define DRAMC_MR_CNT 4
#define DRAMC_FREQ_CNT 7
struct mr_info_t {
u16 mr_index;
u16 mr_value;
};
enum DRAM_TYPE {
DTYPE_DDR1 = 1,
DTYPE_LPDDR2,
DTYPE_LPDDR3,
DTYPE_PCDDR3,
DTYPE_LPDDR4,
DTYPE_LPDDR4X,
DTYPE_LPDDR4P
};
extern struct dramc_param *dramc_params;
int mt_get_dram_type(void);
int get_dram_channel_support_nr(void);
int get_dram_channel_nr(void);
int get_dram_rank_nr(void);
int get_dram_mr_cnt(void);
int get_dram_freq_cnt(void);
#if !__ETT__
void get_dram_rank_size(u64 dram_rank_size[]);
void get_dram_freq_step(u32 dram_freq_step[]);
void set_dram_mr(unsigned int index, unsigned short value);
unsigned short get_dram_mr(unsigned int index);
void get_dram_mr_info(struct mr_info_t mr_info[]);
void reserve_dramc_dummy_read(void);
#endif
typedef struct _AC_TIMING_EXTERNAL_T
{
// U 00
U32 AC_TIME_EMI_FREQUENCY :16;
U32 AC_TIME_EMI_TRAS :8;
U32 AC_TIME_EMI_TRP :8;
// U 01
U32 AC_TIME_EMI_TRPAB :8;
U32 AC_TIME_EMI_TRC :8;
U32 AC_TIME_EMI_TRFC :8;
U32 AC_TIME_EMI_TRFCPB :8;
// U 02
U32 AC_TIME_EMI_TXP :8;
U32 AC_TIME_EMI_TRTP :8;
U32 AC_TIME_EMI_TRCD :8;
U32 AC_TIME_EMI_TWR :8;
// U 03
U32 AC_TIME_EMI_TWTR :8;
U32 AC_TIME_EMI_TRRD :8;
U32 AC_TIME_EMI_TFAW :8;
U32 AC_TIME_EMI_TRTW_ODT_OFF :4;
U32 AC_TIME_EMI_TRTW_ODT_ON :4;
// U 04
U32 AC_TIME_EMI_REFCNT :8; //(REFFRERUN = 0)
U32 AC_TIME_EMI_REFCNT_FR_CLK :8; //(REFFRERUN = 1)
U32 AC_TIME_EMI_TXREFCNT :8;
U32 AC_TIME_EMI_TZQCS :8;
// U 05
U32 AC_TIME_EMI_TRTPD :8; // LP4/LP3, // Olymp_us new
U32 AC_TIME_EMI_TWTPD :8; // LP4/LP3, // Olymp_us new
U32 AC_TIME_EMI_TMRR2W_ODT_OFF :8; // LP4 // Olymp_us new
U32 AC_TIME_EMI_TMRR2W_ODT_ON :8; // LP4 // Olymp_us new
// U 06
// Byte0
U32 AC_TIME_EMI_TRAS_05T :2;
U32 AC_TIME_EMI_TRP_05T :2;
U32 AC_TIME_EMI_TRPAB_05T :2;
U32 AC_TIME_EMI_TRC_05T :2;
// Byte1
U32 AC_TIME_EMI_TRFC_05T :2;
U32 AC_TIME_EMI_TRFCPB_05T :2;
U32 AC_TIME_EMI_TXP_05T :2;
U32 AC_TIME_EMI_TRTP_05T :2;
// Byte2
U32 AC_TIME_EMI_TRCD_05T :2;
U32 AC_TIME_EMI_TWR_05T :2;
U32 AC_TIME_EMI_TWTR_05T :2; // Olymp_us modified
U32 AC_TIME_EMI_TRRD_05T :2;
// Byte3
U32 AC_TIME_EMI_TFAW_05T :2;
U32 AC_TIME_EMI_TRTW_ODT_OFF_05T :2;
U32 AC_TIME_EMI_TRTW_ODT_ON_05T :2;
U32 AC_TIME_EMI_TRTPD_05T :2; // LP4/LP3 // Olymp_us new
// U 07
// Byte0
U32 AC_TIME_EMI_TWTPD_05T :2; // LP4/LP3 // Olymp_us new
U32 AC_TIME_EMI_TMRR2W_ODT_OFF_05T :2; // Useless, no 0.5T in Olymp_us and Elbr_us
U32 AC_TIME_EMI_TMRR2W_ODT_ON_05T :2; // Useless, no 0.5T in Olymp_us and Elbr_us
}AC_TIMING_EXTERNAL_T;
typedef struct
{
unsigned int sub_version; // sub_version: 0x1 for new version
unsigned int type; /* 0x0000 : Invalid
0x0001 : Discrete DDR1
0x0002 : Discrete LPDDR2
0x0003 : Discrete LPDDR3
0x0004 : Discrete PCDDR3
0x0005 : Discrete LPDDR4
0x0006 : Discrete LPDR4X
0x0101 : MCP(NAND+DDR1)
0x0102 : MCP(NAND+LPDDR2)
0x0103 : MCP(NAND+LPDDR3)
0x0104 : MCP(NAND+PCDDR3)
0x0201 : MCP(eMMC+DDR1)
0x0202 : MCP(eMMC+LPDDR2)
0x0203 : MCP(eMMC+LPDDR3)
0x0204 : MCP(eMMC+PCDDR3)
0x0205 : MCP(eMMC+LPDDR4)
0x0206 : MCP(eMMC+LPDR4X)
*/
unsigned int id_length; // EMMC and NAND ID checking length
unsigned int fw_id_length; // FW ID checking length
unsigned char ID[16];
unsigned char fw_id[8]; // To save fw id
unsigned int EMI_CONA_VAL; //@0x3000
unsigned int EMI_CONH_VAL;
union {
unsigned int DRAMC_ACTIME_UNION[8];
AC_TIMING_EXTERNAL_T AcTimeEMI;
};
u64 DRAM_RANK_SIZE[4];
unsigned int EMI_CONF_VAL;
unsigned int CHN0_EMI_CONA_VAL;
unsigned int CHN1_EMI_CONA_VAL;
/* Single field to store LP4 dram type (normal, byte, mixed) */
unsigned int dram_cbt_mode_extern;
unsigned int reserved[6];
#if 0
union
{
struct
{
int iLPDDR2_MODE_REG_1;
int iLPDDR2_MODE_REG_2;
int iLPDDR2_MODE_REG_3;
int iLPDDR2_MODE_REG_5;
int iLPDDR2_MODE_REG_10;
int iLPDDR2_MODE_REG_63;
};
struct
{
int iDDR1_MODE_REG;
int iDDR1_EXT_MODE_REG;
};
struct
{
int iPCDDR3_MODE_REG0;
int iPCDDR3_MODE_REG1;
int iPCDDR3_MODE_REG2;
int iPCDDR3_MODE_REG3;
};
struct
{
int iLPDDR3_MODE_REG_1;
int iLPDDR3_MODE_REG_2;
int iLPDDR3_MODE_REG_3;
int iLPDDR3_MODE_REG_5;
int iLPDDR3_MODE_REG_10;
int iLPDDR3_MODE_REG_63;
};
};
#else
unsigned int iLPDDR3_MODE_REG_5;
#endif
unsigned int PIN_MUX_TYPE;
} EMI_SETTINGS;
//typedef EMI_SETTINGS_v15 EMI_SETTINGS;
#if (FOR_DV_SIMULATION_USED==0)
void setup_dramc_voltage_by_pmic(void);
void switch_dramc_voltage_to_auto_mode(void);
#if ! __ETT__
uint32 mt_set_emis(uint8* emi, uint32 len, bool use_default); //array of emi setting.
#endif
#endif
extern int emi_setting_index;
extern EMI_SETTINGS emi_settings[];
extern EMI_SETTINGS default_emi_setting;
extern EMI_SETTINGS emi_setting_default_lpddr3;
extern EMI_SETTINGS emi_setting_default_lpddr4;
#include "x_hal_io.h"
#ifdef LAST_DRAMC
#define LAST_DRAMC_MAGIC_PATTERN 0x19870611
static void update_last_dramc_info(void);
void init_ta2_all_channel(void);
typedef struct {
unsigned int ta2_result_magic;
unsigned int ta2_result_last;
unsigned int ta2_result_past;
unsigned int ta2_result_checksum;
unsigned int reboot_count;
volatile unsigned int last_fatal_err_flag;
volatile unsigned int fatal_err_flag;
volatile unsigned int storage_api_err_flag;
volatile unsigned int last_gating_err[2][2]; // [channel][rank]
volatile unsigned int gating_err[2][2]; // [channel][rank]
unsigned short mr5;
unsigned short mr6;
unsigned short mr7;
unsigned short mr8;
} LAST_DRAMC_INFO_T;
#define DEF_LAST_DRAMC LAST_DRAMC_INFO_T
#define OFFSET_DRAM_FATAL_ERR (31)
#define OFFSET_DRAM_TA2_ERR (23)
#define OFFSET_DRAM_GATING_ERR (7)
#define OFFSET_CPU_RW_ERR (5)
#define OFFSET_DDR_RSV_MODE_FLOW (4)
#define OFFSET_DDR_RSV_MODE_ERR (3)
#define OFFSET_EMI_DCS_ERR (2)
#define OFFSET_DVFSRC_ERR (1)
#define OFFSET_DRS_ERR (0)
#define ERR_DRAM_TA2_RK0 (1 << 0)
#define ERR_DRAM_TA2_RK1 (1 << 1)
#define ERR_DRAM_GATING_RK0_R (1 << 0)
#define ERR_DRAM_GATING_RK0_F (1 << 1)
#define ERR_DRAM_GATING_RK1_R (1 << 2)
#define ERR_DRAM_GATING_RK1_F (1 << 3)
#define ERR_CPU_RW_RK0 (1 << 0)
#define ERR_CPU_RW_RK1 (1 << 1)
/* 0x1f -> bit[4:0] is for DDR reserve mode */
#define DDR_RSV_MODE_ERR_MASK (0x1f)
unsigned int check_last_dram_fatal_exception(void);
unsigned int check_dram_fatal_exception(void);
void set_err_code_for_storage_api(void);
void dram_fatal_set_ta2_err(unsigned int chn, unsigned int err_code);
void dram_fatal_set_gating_err(unsigned int chn, unsigned int err_code);
void dram_fatal_set_cpu_rw_err(unsigned int err_code);
void dram_fatal_set_stberr(unsigned int chn, unsigned int rk, unsigned int err_code);
void dram_fatal_backup_stberr(void);
void dram_fatal_init_stberr(void);
void dram_fatal_set_err(unsigned int err_code, unsigned int mask, unsigned int offset);
#define dram_fatal_set_cpu_rw_err(err_code)\
do {\
dram_fatal_set_err(err_code, 0x3, OFFSET_CPU_RW_ERR);\
} while(0)
#define dram_fatal_set_ddr_rsv_mode_err()\
do {\
dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_ERR);\
} while(0)
#define dram_fatal_set_emi_dcs_err()\
do {\
dram_fatal_set_err(0x1, 0x1, OFFSET_EMI_DCS_ERR);\
} while(0)
#define dram_fatal_set_dvfsrc_err()\
do {\
dram_fatal_set_err(0x1, 0x1, OFFSET_DVFSRC_ERR);\
} while(0)
#define dram_fatal_set_drs_err()\
do {\
dram_fatal_set_err(0x1, 0x1, OFFSET_DRS_ERR);\
} while(0)
#define dram_fatal_set_ddr_rsv_mode_flow()\
do {\
dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_FLOW);\
} while(0)
#endif //LAST_DRAMC
typedef enum {
KSHU0 = 0,
KSHU1,
KSHU2,
KSHU3,
KSHU4,
KSHU5,
KSHU6,
KSHU7,
KSHU8,
KSHU9,
} DRAM_KSHU;
typedef enum {
TYPE_VDRAM = 0,
TYPE_VDDR1,
TYPE_VDDR2,
TYPE_VDDQ,
} TYPE_VOLTAGE;
typedef enum {
LEVEL_VB = 0,
LEVEL_HV,
LEVEL_NV,
LEVEL_LV,
} LEVEL_VOLTAGE;
//================================================
//=============pmic related api for ETT HQA test ==============
//================================================
#if (__ETT__ || CFG_DRAM_LOG_TO_STORAGE)
#define DRAM_HQA
#endif
#define MAX_VCORE 1193750
#define MAX_VDRAM 1300000
#define MAX_VDDQ 1300000
#define MAX_VMDDR 2000000
#define MAX_VIO18 1900000
#define UNIT_VCORE 6250
#define UNIT_VDRAM 5000
#define UNIT_VDDQ 10000
#define UNIT_VMDDR 10000
#define UNIT_VIO18 10000
#define UNIT_VIO18_STEP 100000
#define HQA_VIO18_HV 1950000
#define HQA_VCORE_HV_LP4_KSHU0_PL 762500
#define HQA_VCORE_HV_LP4_KSHU1_PL 725000
#define HQA_VCORE_HV_LP4_KSHU2_PL 700000
#define HQA_VCORE_HV_LP4_KSHU3_PL 700000
#define HQA_VCORE_HV_LP4_KSHU4_PL 687500
#define HQA_VCORE_HV_LP4_KSHU5_PL 687500
#define HQA_VCORE_HV_LP4_KSHU6_PL 687500
#define HQA_VCORE_HV_LP4_KSHU0_ETT 762500
#define HQA_VCORE_HV_LP4_KSHU1_ETT 762500
#define HQA_VCORE_HV_LP4_KSHU2_ETT 762500
#define HQA_VCORE_HV_LP4_KSHU3_ETT 762500
#define HQA_VCORE_HV_LP4_KSHU4_ETT 762500
#define HQA_VCORE_HV_LP4_KSHU5_ETT 762500
#define HQA_VCORE_HV_LP4_KSHU6_ETT 762500
#define HQA_VDRAM_HV_LP4 1170000
#define HQA_VDDQ_HV_LP4 650000
#define HQA_VMDDR_HV_LP4 790000
#define HQA_VIO18_NV 1800000
#define HQA_VCORE_NV_LP4_KSHU0_PL 725000
#define HQA_VCORE_NV_LP4_KSHU1_PL 687500
#define HQA_VCORE_NV_LP4_KSHU2_PL 662500
#define HQA_VCORE_NV_LP4_KSHU3_PL 662500
#define HQA_VCORE_NV_LP4_KSHU4_PL 650000
#define HQA_VCORE_NV_LP4_KSHU5_PL 650000
#define HQA_VCORE_NV_LP4_KSHU6_PL 650000
#define HQA_VCORE_NV_LP4_KSHU0_ETT 725000
#define HQA_VCORE_NV_LP4_KSHU1_ETT 687500
#define HQA_VCORE_NV_LP4_KSHU2_ETT 662500
#define HQA_VCORE_NV_LP4_KSHU3_ETT 662500
#define HQA_VCORE_NV_LP4_KSHU4_ETT 650000
#define HQA_VCORE_NV_LP4_KSHU5_ETT 650000
#define HQA_VCORE_NV_LP4_KSHU6_ETT 650000
#define HQA_VDRAM_NV_LP4 1125000
#define HQA_VDDQ_NV_LP4 600000
#define HQA_VMDDR_NV_LP4 750000
#define HQA_VIO18_LV 1730000
#define HQA_VCORE_LV_LP4_KSHU0_PL 687500
#define HQA_VCORE_LV_LP4_KSHU1_PL 650000
#define HQA_VCORE_LV_LP4_KSHU2_PL 625000
#define HQA_VCORE_LV_LP4_KSHU3_PL 625000
#define HQA_VCORE_LV_LP4_KSHU4_PL 612500
#define HQA_VCORE_LV_LP4_KSHU5_PL 612500
#define HQA_VCORE_LV_LP4_KSHU6_PL 612500
#define HQA_VCORE_LV_LP4_KSHU0_ETT 687500
#define HQA_VCORE_LV_LP4_KSHU1_ETT 612500
#define HQA_VCORE_LV_LP4_KSHU2_ETT 568750
#define HQA_VCORE_LV_LP4_KSHU3_ETT 568750
#define HQA_VCORE_LV_LP4_KSHU4_ETT 543750
#define HQA_VCORE_LV_LP4_KSHU5_ETT 543750
#define HQA_VCORE_LV_LP4_KSHU6_ETT 543750
#define HQA_VDRAM_LV_LP4 1060000
#define HQA_VDDQ_LV_LP4 570000
#define HQA_VMDDR_LV_LP4 710000
#define _SEL_PREFIX_SHU_PL(type,vol,dtype,shu) HQA_##type##_##vol##_##dtype##_##shu##_PL
#define _SEL_PREFIX_SHU_ETT(type,vol,dtype,shu) HQA_##type##_##vol##_##dtype##_##shu##_ETT
#define _SEL_PREFIX(type,vol,dtype) HQA_##type##_##vol##_##dtype
#define _SEL_VIO18(vol) HQA_VIO18_##vol
#define STD_VIO18 _SEL_VIO18(NV)
#define STD_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,NV,dtype,shu)
#define STD_VDRAM(dtype) _SEL_PREFIX(VDRAM,NV,dtype)
#define STD_VDDQ _SEL_PREFIX(VDDQ,NV,LP4)
#define STD_VMDDR _SEL_PREFIX(VMDDR,NV,LP4)
#ifdef DRAM_HQA
//#define HVCORE_HVDRAM
#define NVCORE_NVDRAM
//#define LVCORE_LVDRAM
//#define HVCORE_LVDRAM
//#define LVCORE_HVDRAM
#if defined(HVCORE_HVDRAM)
#define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,HV,dtype,shu)
#define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,HV,dtype)
#define HQA_VDDQ _SEL_PREFIX(VDDQ,HV,LP4)
#define HQA_VMDDR _SEL_PREFIX(VMDDR,HV,LP4)
#define HQA_VIO18 _SEL_VIO18(HV)
#elif defined(NVCORE_NVDRAM)
#define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,NV,dtype,shu)
#define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,NV,dtype)
#define HQA_VDDQ _SEL_PREFIX(VDDQ,NV,LP4)
#define HQA_VMDDR _SEL_PREFIX(VMDDR,NV,LP4)
#define HQA_VIO18 _SEL_VIO18(NV)
#elif defined(LVCORE_LVDRAM)
#define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,LV,dtype,shu)
#define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,LV,dtype)
#define HQA_VDDQ _SEL_PREFIX(VDDQ,LV,LP4)
#define HQA_VMDDR _SEL_PREFIX(VMDDR,LV,LP4)
#define HQA_VIO18 _SEL_VIO18(LV)
#elif defined(HVCORE_LVDRAM)
#define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,HV,dtype,shu)
#define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,LV,dtype)
#define HQA_VDDQ _SEL_PREFIX(VDDQ,LV,LP4)
#define HQA_VMDDR _SEL_PREFIX(VMDDR,LV,LP4)
#define HQA_VIO18 _SEL_VIO18(LV)
#elif defined(LVCORE_HVDRAM)
#define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,LV,dtype,shu)
#define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,HV,dtype)
#define HQA_VDDQ _SEL_PREFIX(VDDQ,HV,LP4)
#define HQA_VMDDR _SEL_PREFIX(VMDDR,HV,LP4)
#define HQA_VIO18 _SEL_VIO18(HV)
#else
#error "Please set HQA voltage type"
#endif
#define SEL_PREFIX_VCORE(dtype,shu) HQA_VCORE(dtype,shu)
#define SEL_PREFIX_VDRAM(dtype) HQA_VDRAM(dtype)
#define SEL_PREFIX_VDDQ HQA_VDDQ
#define SEL_PREFIX_VMDDR HQA_VMDDR
#define SEL_VIO18 HQA_VIO18
#else
#if !__ETT__
#define VCORE_BIN
#endif
#define SEL_PREFIX_VCORE(dtype,shu) STD_VCORE(dtype,shu)
#define SEL_PREFIX_VDRAM(dtype) STD_VDRAM(dtype)
#define SEL_PREFIX_VDDQ STD_VDDQ
#define SEL_PREFIX_VMDDR STD_VMDDR
#define SEL_VIO18 STD_VIO18
#endif // #define DRAM_HQA
#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
#define PART_DRAM_DATA_SIZE 0x100000
#define DRAM_CALIBRATION_DATA_MAGIC 0x9502
typedef struct _DRAM_CALIBRATION_HEADER_T
{
u32 pl_version;
u16 magic_number;
u32 calib_err_code;
} DRAM_CALIBRATION_HEADER_T;
typedef struct _DRAM_CALIBRATION_MRR_DATA_T
{
u16 checksum;
u16 emi_checksum;
DRAM_INFO_BY_MRR_T DramInfo;
} DRAM_CALIBRATION_MRR_DATA_T;
typedef struct _DRAM_CALIBRATION_SHU_DATA_T
{
u16 checksum;
u32 calib_err_code;
SAVE_TIME_FOR_CALIBRATION_T calibration_data;
} DRAM_CALIBRATION_SHU_DATA_T;
typedef struct _DRAM_CALIBRATION_DATA_T
{
DRAM_CALIBRATION_HEADER_T header;
DRAM_CALIBRATION_MRR_DATA_T mrr_info;
DRAM_CALIBRATION_SHU_DATA_T data[DRAM_DFS_SHUFFLE_MAX];
} DRAM_CALIBRATION_DATA_T;
/*
* g_dram_storage_api_err_code:
* bit[0:3] -> read api
* bit[4:7] -> write api
* bit[8:11] -> clean api
* bit[12:12] -> data formatted due to fatal exception
*/
#define ERR_NULL_POINTER (0x1)
#define ERR_MAGIC_NUMBER (0x2)
#define ERR_CHECKSUM (0x3)
#define ERR_PL_UPDATED (0x4)
#define ERR_BLKDEV_NOT_FOUND (0x5)
#define ERR_BLKDEV_READ_FAIL (0x6)
#define ERR_BLKDEV_WRITE_FAIL (0x7)
#define ERR_BLKDEV_NO_PART (0x8)
#define ERR_DATA_FORMATTED_OFFSET (12)
typedef enum {
DRAM_STORAGE_API_READ = 0,
DRAM_STORAGE_API_WRITE,
DRAM_STORAGE_API_CLEAN,
} DRAM_STORAGE_API_TPYE;
extern u32 g_dram_storage_api_err_code;
#define SET_DRAM_STORAGE_API_ERR(err_type, api_type) \
do {\
g_dram_storage_api_err_code |= (err_type << (api_type * 4));\
} while(0)
#define SET_DATA_FORMATTED_STORAGE_API_ERR() \
do {\
g_dram_storage_api_err_code |= (1 << ERR_DATA_FORMATTED_OFFSET);\
} while(0)
int read_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData);
int write_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData);
int clean_dram_calibration_data(void);
void dram_fatal_exception_detection_start(void);
void dram_fatal_exception_detection_end(void);
#define CBT_VREF_OFFSET 2
#define WRITE_LEVELING_OFFSET 5
#define GATING_START_OFFSET 0
#define GATING_PASS_WIN_OFFSET 3
#define RX_WIN_PERBIT_OFFSET 5
#define RX_WIN_PERBIT_VREF_OFFSET 4
#define TX_WIN_PERBIT_OFFSET 5
#define TX_WIN_PERBIT_VREF_OFFSET 4
#define RX_DATLAT_OFFSET 1
#define RX_WIN_HIGH_SPEED_TH 10
#define RX_WIN_LOW_SPEED_TH 100
#define TX_WIN_TH 12
#endif
#if defined(SLT)
#define SLT_ERR_NO_DATA (-1)
#define SLT_ERR_NO_DEV (-2)
#define SLT_ERR_NO_ADDR (-3)
#define SLT_ERR_WRITE_FAIL (-4)
#define SLT_ERR_READ_FAIL (-5)
typedef struct _DRAM_SLT_HEADER_T
{
u32 pl_version;
int stage_status;
} DRAM_SLT_HEADER_T;
typedef struct _DRAM_SLT_DATA_T
{
DRAM_SLT_HEADER_T header;
u32 test_result[10];
} DRAM_SLT_DATA_T;
int read_slt_data(DRAM_SLT_DATA_T *data);
int write_slt_data(DRAM_SLT_DATA_T *data);
int clean_slt_data(void);
#endif
int doe_get_config(const char* feature);
unsigned long long get_dram_size(void);
typedef struct {
unsigned long long full_sys_addr;
unsigned int addr;
unsigned int row;
unsigned int col;
unsigned char ch;
unsigned char rk;
unsigned char bk;
unsigned char dummy;
} dram_addr_t;
unsigned int get_dramc_addr(dram_addr_t *dram_addr, unsigned int offset);
unsigned int get_dummy_read_addr(dram_addr_t *dram_addr);
unsigned int is_discrete_lpddr4(void);
#endif /* __DRAMC_TOP_H__ */

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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef _DRAMC_TYPEDEFS_H_
#define _DRAMC_TYPEDEFS_H_
#include <stdint.h>
#define IMPORT EXTERN
#ifndef __cplusplus
#define EXTERN extern
#else
#define EXTERN extern "C"
#endif
#define LOCAL static
#define GLOBAL
#define EXPORT GLOBAL
#define EQ ==
#define NEQ !=
#define AND &&
#define OR ||
#define XOR(A,B) ((!(A) AND (B)) OR ((A) AND !(B)))
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE 1
#endif
#if 0
#define ASSERT(expr) \
do{ if(!(expr)){while(1);} }while(0)
#endif
#ifndef BOOL
typedef unsigned char BOOL;
#endif
typedef unsigned long ulong;
typedef unsigned char uchar;
typedef unsigned int uint;
typedef signed char int8;
typedef signed short int16;
typedef signed long int32;
typedef signed int intx;
typedef unsigned char uint8;
typedef unsigned short uint16;
typedef unsigned long uint32;
typedef unsigned int uintx;
typedef signed char S8;
typedef signed short S16;
typedef signed int S32;
typedef signed long long S64;
typedef unsigned char U8;
typedef unsigned short U16;
typedef unsigned int U32;
typedef unsigned long long U64;
typedef unsigned char US8;
typedef unsigned short US16;
typedef unsigned int US32;
typedef unsigned long long US64;
typedef unsigned char u8;
typedef unsigned short u16;
typedef unsigned int u32;
typedef unsigned long long u64;
typedef unsigned char UINT8;
typedef unsigned short UINT16;
typedef unsigned int UINT32;
typedef unsigned short USHORT;
typedef signed char INT8;
typedef signed short INT16;
typedef signed int INT32;
typedef volatile signed char *P_S8;
typedef volatile signed short *P_S16;
typedef volatile signed int *P_S32;
typedef long LONG;
typedef unsigned char UBYTE;
typedef short SHORT;
typedef unsigned int *UINT32P;
typedef volatile unsigned short *UINT16P;
typedef volatile unsigned char *UINT8P;
typedef unsigned char *U8P;
typedef volatile unsigned char *P_U8;
typedef volatile unsigned short *P_U16;
typedef volatile unsigned int *P_U32;
typedef unsigned long long *P_U64;
typedef signed long long *P_S64;
typedef unsigned int uint;
typedef void VOID;
typedef unsigned char BYTE;
typedef float FLOAT;
#if FOR_DV_SIMULATION_USED
#include <stdio.h>
#include <string.h>
#endif
#endif

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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef __EMI_H__
#define __EMI_H__
#include <soc/addressmap.h>
#include <dramc_top.h>
#define EMI_APB_BASE EMI_BASE
#if __ETT__
#define emi_log printf
#elif __FLASH_TOOL_DA__
#define emi_log LOGD
#else
#define emi_log(_x_...) printk(BIOS_INFO, _x_)
#endif
struct isu_info_t {
unsigned int buf_size;
unsigned long long buf_addr;
unsigned long long ver_addr;
unsigned long long con_addr;
};
#define EMI_ISU_BUF_SIZE 0x800000
#define LAST_EMI_MAGIC_PATTERN 0x19870611
typedef struct {
unsigned int isu_magic;
unsigned int isu_ctrl;
unsigned int isu_dram_type;
unsigned int isu_diff_us;
unsigned int isu_buf_l;
unsigned int isu_buf_h;
unsigned int isu_version;
unsigned int snst_last;
unsigned int snst_past;
unsigned int os_flag_sspm;
unsigned int os_flag_ap;
} LAST_EMI_INFO_T;
#define DEF_LAST_EMI LAST_EMI_INFO_T
void emi_init(void);
void emi_init2(void);
void clr_emi_mpu_prot(void);
void dis_emi_apb_prot(void);
int get_row_width_by_emi(unsigned int rank);
int get_channel_nr_by_emi(void);
int get_rank_nr_by_emi(void);
void get_rank_size_by_emi(unsigned long long dram_rank_size[DRAMC_MAX_RK]);
void set_cen_emi_cona(unsigned int cona_val);
void set_cen_emi_conf(unsigned int conf_val);
void set_cen_emi_conh(unsigned int conh_val);
void set_chn_emi_cona(unsigned int cona_val);
void set_chn_emi_conc(unsigned int conc_val);
unsigned int get_cen_emi_cona(void);
unsigned int get_chn_emi_cona(void);
void phy_addr_to_dram_addr(dram_addr_t *dram_addr, unsigned long long phy_addr);
unsigned int set_emi_before_rank1_mem_test(void);
void restore_emi_after_rank1_mem_test(void);
void get_emi_isu_info(struct isu_info_t *isu_info_ptr);
void reserve_emi_isu_buf(void);
void reserve_emi_mbist_buf(void);
void record_emi_snst(void);
unsigned long long platform_memory_size(void);
#endif /* __EMI_H__ */

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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef __EMI_HW_H__
#define __EMI_HW_H__
/* from EMI golden setting */
#define MARGAUX_EMI_MP_SETTING
#define MARGAUX_REAL_CHIP_EMI_GOLDEN_SETTING
//#define INFRA_DRAMC_REG_CONFIG (INFRACFG_AO_BASE + 0xB4)
//#define INFRACFG_AO_MEM_BASE (0x10002000)
//#define SUB_INFRACFG_AO_MEM_BASE (0x1030E000)
//#define MCUSYS_PAR_WRAP_BASE (0x0C530000)
//#define EMI_BASE (0x10219000)
//#define EMI_MPU_BASE (0x10226000)
#define CHN0_EMI_BASE (IO_PHYS + 0x235000)
#define CHN1_EMI_BASE (IO_PHYS + 0x245000)
#define EMI_CONA (EMI_BASE+0x000)
#define EMI_CONB (EMI_BASE+0x008)
#define EMI_CONC (EMI_BASE+0x010)
#define EMI_COND (EMI_BASE+0x018)
#define EMI_CONE (EMI_BASE+0x020)
#define EMI_CONF (EMI_BASE+0x028)
#define EMI_CONG (EMI_BASE+0x030)
#define EMI_CONH (EMI_BASE+0x038)
#define EMI_CONH_2ND (EMI_BASE+0x03C)
#define EMI_CONI (EMI_BASE+0x040)
#define EMI_CONJ (EMI_BASE+0x048)
#define EMI_CONM (EMI_BASE+0x060)
#define EMI_CONN (EMI_BASE+0x068)
#define EMI_CONO (EMI_BASE+0x070)
#define EMI_MDCT (EMI_BASE+0x078)
#define EMI_MDCT_2ND (EMI_BASE+0x07C)
#define EMI_IOCL (EMI_BASE+0x0D0)
#define EMI_IOCL_2ND (EMI_BASE+0x0D4)
#define EMI_IOCM (EMI_BASE+0x0D8)
#define EMI_IOCM_2ND (EMI_BASE+0x0DC)
#define EMI_TESTB (EMI_BASE+0x0E8)
#define EMI_TESTC (EMI_BASE+0x0F0)
#define EMI_TESTD (EMI_BASE+0x0F8)
#define EMI_ARBA (EMI_BASE+0x100)
#define EMI_ARBB (EMI_BASE+0x108)
#define EMI_ARBC (EMI_BASE+0x110)
#define EMI_ARBD (EMI_BASE+0x118)
#define EMI_ARBE (EMI_BASE+0x120)
#define EMI_ARBF (EMI_BASE+0x128)
#define EMI_ARBG (EMI_BASE+0x130)
#define EMI_ARBH (EMI_BASE+0x138)
#define EMI_ARBI (EMI_BASE+0x140)
#define EMI_ARBI_2ND (EMI_BASE+0x144)
#define EMI_ARBJ_2ND (EMI_BASE+0x14C)
#define EMI_ARBK (EMI_BASE+0x150)
#define EMI_ARBK_2ND (EMI_BASE+0x154)
#define EMI_SLCT (EMI_BASE+0x158)
#define EMI_MPUD0_ST (EMI_BASE+0x160)
#define EMI_MPUD1_ST (EMI_BASE+0x164)
#define EMI_MPUD2_ST (EMI_BASE+0x168)
#define EMI_MPUD3_ST (EMI_BASE+0x16C)
#define EMI_MPUD4_ST (EMI_BASE+0x170)
#define EMI_MPUD5_ST (EMI_BASE+0x174)
#define EMI_MPUD6_ST (EMI_BASE+0x178)
#define EMI_MPUD7_ST (EMI_BASE+0x17C)
#define EMI_MPUD8_ST (EMI_BASE+0x180)
#define EMI_MPUD9_ST (EMI_BASE+0x184)
#define EMI_MPUD10_ST (EMI_BASE+0x188)
#define EMI_MPUD11_ST (EMI_BASE+0x18C)
#define EMI_MPUD12_ST (EMI_BASE+0x190)
#define EMI_MPUD13_ST (EMI_BASE+0x194)
#define EMI_MPUD14_ST (EMI_BASE+0x198)
#define EMI_MPUD15_ST (EMI_BASE+0x19C)
#define EMI_MPUD16_ST (EMI_BASE+0x1A0)
#define EMI_MPUD17_ST (EMI_BASE+0x1A4)
#define EMI_MPUD18_ST (EMI_BASE+0x1A8)
#define EMI_MPUD19_ST (EMI_BASE+0x1AC)
#define EMI_MPUD20_ST (EMI_BASE+0x1B0)
#define EMI_MPUD21_ST (EMI_BASE+0x1B4)
#define EMI_MPUD22_ST (EMI_BASE+0x1B8)
#define EMI_MPUD23_ST (EMI_BASE+0x1BC)
#define EMI_MPUD24_ST (EMI_BASE+0x1C0)
#define EMI_MPUD25_ST (EMI_BASE+0x1C4)
#define EMI_MPUD26_ST (EMI_BASE+0x1C8)
#define EMI_MPUD27_ST (EMI_BASE+0x1CC)
#define EMI_MPUD28_ST (EMI_BASE+0x1D0)
#define EMI_MPUD29_ST (EMI_BASE+0x1D4)
#define EMI_MPUD30_ST (EMI_BASE+0x1D8)
#define EMI_MPUD31_ST (EMI_BASE+0x1DC)
#define EMI_MPUS (EMI_BASE+0x1F0)
#define EMI_MPUT (EMI_BASE+0x1F8)
#define EMI_MPUT_2ND (EMI_BASE+0x1FC)
#define EMI_D0_ST2 (EMI_BASE+0x200)
#define EMI_D1_ST2 (EMI_BASE+0x204)
#define EMI_D2_ST2 (EMI_BASE+0x208)
#define EMI_D3_ST2 (EMI_BASE+0x20C)
#define EMI_D4_ST2 (EMI_BASE+0x210)
#define EMI_D5_ST2 (EMI_BASE+0x214)
#define EMI_D6_ST2 (EMI_BASE+0x218)
#define EMI_D7_ST2 (EMI_BASE+0x21C)
#define EMI_D8_ST2 (EMI_BASE+0x220)
#define EMI_D9_ST2 (EMI_BASE+0x224)
#define EMI_D10_ST2 (EMI_BASE+0x228)
#define EMI_D11_ST2 (EMI_BASE+0x22C)
#define EMI_D12_ST2 (EMI_BASE+0x230)
#define EMI_D13_ST2 (EMI_BASE+0x234)
#define EMI_D14_ST2 (EMI_BASE+0x238)
#define EMI_D15_ST2 (EMI_BASE+0x23C)
#define EMI_D16_ST2 (EMI_BASE+0x240)
#define EMI_D17_ST2 (EMI_BASE+0x244)
#define EMI_D18_ST2 (EMI_BASE+0x248)
#define EMI_D19_ST2 (EMI_BASE+0x24C)
#define EMI_D20_ST2 (EMI_BASE+0x250)
#define EMI_D21_ST2 (EMI_BASE+0x254)
#define EMI_D22_ST2 (EMI_BASE+0x258)
#define EMI_D23_ST2 (EMI_BASE+0x25C)
#define EMI_D24_ST2 (EMI_BASE+0x260)
#define EMI_D25_ST2 (EMI_BASE+0x264)
#define EMI_D26_ST2 (EMI_BASE+0x268)
#define EMI_D27_ST2 (EMI_BASE+0x26C)
#define EMI_D28_ST2 (EMI_BASE+0x270)
#define EMI_D29_ST2 (EMI_BASE+0x274)
#define EMI_D30_ST2 (EMI_BASE+0x278)
#define EMI_D31_ST2 (EMI_BASE+0x27C)
#define EMI_BMEN (EMI_BASE+0x400)
#define EMI_BSTP (EMI_BASE+0x404)
#define EMI_BCNT (EMI_BASE+0x408)
#define EMI_TACT (EMI_BASE+0x410)
#define EMI_TSCT (EMI_BASE+0x418)
#define EMI_WACT (EMI_BASE+0x420)
#define EMI_WSCT (EMI_BASE+0x428)
#define EMI_BACT (EMI_BASE+0x430)
#define EMI_BSCT (EMI_BASE+0x438)
#define EMI_MSEL (EMI_BASE+0x440)
#define EMI_TSCT2 (EMI_BASE+0x448)
#define EMI_TSCT3 (EMI_BASE+0x450)
#define EMI_WSCT2 (EMI_BASE+0x458)
#define EMI_WSCT3 (EMI_BASE+0x460)
#define EMI_WSCT4 (EMI_BASE+0x464)
#define EMI_MSEL2 (EMI_BASE+0x468)
#define EMI_MSEL3 (EMI_BASE+0x470)
#define EMI_MSEL4 (EMI_BASE+0x478)
#define EMI_MSEL5 (EMI_BASE+0x480)
#define EMI_MSEL6 (EMI_BASE+0x488)
#define EMI_MSEL7 (EMI_BASE+0x490)
#define EMI_MSEL8 (EMI_BASE+0x498)
#define EMI_MSEL9 (EMI_BASE+0x4A0)
#define EMI_MSEL10 (EMI_BASE+0x4A8)
#define EMI_BMID0 (EMI_BASE+0x4B0)
#define EMI_BMID1 (EMI_BASE+0x4B4)
#define EMI_BMID2 (EMI_BASE+0x4B8)
#define EMI_BMID3 (EMI_BASE+0x4BC)
#define EMI_BMID4 (EMI_BASE+0x4C0)
#define EMI_BMID5 (EMI_BASE+0x4C4)
#define EMI_BMID6 (EMI_BASE+0x4C8)
#define EMI_BMID7 (EMI_BASE+0x4CC)
#define EMI_BMID8 (EMI_BASE+0x4D0)
#define EMI_BMID9 (EMI_BASE+0x4D4)
#define EMI_BMID10 (EMI_BASE+0x4D8)
#define EMI_BMEN1 (EMI_BASE+0x4E0)
#define EMI_BMEN2 (EMI_BASE+0x4E8)
#define EMI_BMRW0 (EMI_BASE+0x4F8)
#define EMI_BMRW1 (EMI_BASE+0x4FC)
#define EMI_TTYPE1 (EMI_BASE+0x500)
#define EMI_TTYPE2 (EMI_BASE+0x508)
#define EMI_TTYPE3 (EMI_BASE+0x510)
#define EMI_TTYPE4 (EMI_BASE+0x518)
#define EMI_TTYPE5 (EMI_BASE+0x520)
#define EMI_TTYPE6 (EMI_BASE+0x528)
#define EMI_TTYPE7 (EMI_BASE+0x530)
#define EMI_TTYPE8 (EMI_BASE+0x538)
#define EMI_TTYPE9 (EMI_BASE+0x540)
#define EMI_TTYPE10 (EMI_BASE+0x548)
#define EMI_TTYPE11 (EMI_BASE+0x550)
#define EMI_TTYPE12 (EMI_BASE+0x558)
#define EMI_TTYPE13 (EMI_BASE+0x560)
#define EMI_TTYPE14 (EMI_BASE+0x568)
#define EMI_TTYPE15 (EMI_BASE+0x570)
#define EMI_TTYPE16 (EMI_BASE+0x578)
#define EMI_TTYPE17 (EMI_BASE+0x580)
#define EMI_TTYPE18 (EMI_BASE+0x588)
#define EMI_TTYPE19 (EMI_BASE+0x590)
#define EMI_TTYPE20 (EMI_BASE+0x598)
#define EMI_TTYPE21 (EMI_BASE+0x5A0)
#define EMI_BWCT0 (EMI_BASE+0x5B0)
#define EMI_BWCT1 (EMI_BASE+0x5B4)
#define EMI_BWCT2 (EMI_BASE+0x5B8)
#define EMI_BWCT3 (EMI_BASE+0x5BC)
#define EMI_BWCT4 (EMI_BASE+0x5C0)
#define EMI_BWST0 (EMI_BASE+0x5C4)
#define EMI_BWST1 (EMI_BASE+0x5C8)
#define EMI_EX_CON (EMI_BASE+0x5D0)
#define EMI_EX_ST0 (EMI_BASE+0x5D4)
#define EMI_EX_ST1 (EMI_BASE+0x5D8)
#define EMI_EX_ST2 (EMI_BASE+0x5DC)
#define EMI_WP_ADR (EMI_BASE+0x5E0)
#define EMI_WP_ADR_2ND (EMI_BASE+0x5E4)
#define EMI_WP_CTRL (EMI_BASE+0x5E8)
#define EMI_CHKER (EMI_BASE+0x5F0)
#define EMI_CHKER_TYPE (EMI_BASE+0x5F4)
#define EMI_CHKER_ADR (EMI_BASE+0x5F8)
#define EMI_CHKER_ADR_2ND (EMI_BASE+0x5FC)
#define EMI_BWCT0_2ND (EMI_BASE+0x6A0)
#define EMI_LTCT0_2ND (EMI_BASE+0x750)
#define EMI_LTCT1_2ND (EMI_BASE+0x754)
#define EMI_LTCT2_2ND (EMI_BASE+0x758)
#define EMI_LTCT3_2ND (EMI_BASE+0x75C)
#define EMI_BWCT0_3RD (EMI_BASE+0x770)
#define EMI_BWCT0_4TH (EMI_BASE+0x780)
#define EMI_BWCT0_5TH (EMI_BASE+0x7B0)
#define EMI_BWCT0_6TH (EMI_BASE+0x7C8)
#define EMI_SNST (EMI_BASE+0x7F8)
#define EMI_SLVA (EMI_BASE+0x800)
#define EMI_THRO_CTRL1 (EMI_BASE+0x858)
#define EMI_AXI_BIST_ADR0 (EMI_BASE+0x98c)
#define EMI_AXI_BIST_ADR1 (EMI_BASE+0x990)
#define EMI_AXI_BIST_ADR2 (EMI_BASE+0x994)
#define EMI_MPU_CTRL (EMI_MPU_BASE+0x000)
#define EMI_MPU_DBG (EMI_MPU_BASE+0x004)
#define EMI_MPU_SA0 (EMI_MPU_BASE+0x100)
#define EMI_MPU_EA0 (EMI_MPU_BASE+0x200)
#define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region*4))
#define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region*4))
#define EMI_MPU_APC0 (EMI_MPU_BASE+0x300)
#define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region*4) + ((dgroup)*0x100))
#define EMI_MPU_CTRL_D0 (EMI_MPU_BASE+0x800)
#define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain*4))
#define EMI_RG_MASK_D0 (EMI_MPU_BASE+0x900)
#define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain*4))
#define CHN_EMI_CONA(base) (base + 0x000)
#define CHN_EMI_CONC(base) (base + 0x010)
#endif // __EMI_HW_H__

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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef __EMI_MPU_MT_H__
#define __EMI_MPU_MT_H__
#define ENABLE_MPU 1
#define EMI_MPU_ALIGN_BITS 16
#define EMI_MPU_DOMAIN_NUM 16
#define EMI_MPU_REGION_NUM 32
#define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS)
#define SSPM_MPU_REGION_ID 4
#include <emi_mpu_v1.h>
#endif /* __EMI_MPU_MT_H__ */

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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef __EMI_MPU_H__
#define __EMI_MPU_H__
#include <emi_mpu_mt.h>
#define NO_PROTECTION 0
#define SEC_RW 1
#define SEC_RW_NSEC_R 2
#define SEC_RW_NSEC_W 3
#define SEC_R_NSEC_R 4
#define FORBIDDEN 5
#define SEC_R_NSEC_RW 6
#define LOCK 1
#define UNLOCK 0
#define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8)
#if (EMI_MPU_DGROUP_NUM == 1)
#define SET_ACCESS_PERMISSION(apc_ary, lock, d7, d6, d5, d4, d3, d2, d1, d0) \
do { \
apc_ary[0] = \
(((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | (((unsigned int) d5) << 15) | \
(((unsigned int) d4) << 12) | (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \
(((unsigned int) d1) << 3) | ((unsigned int) d0) | ((unsigned int) lock << 31); \
} while (0)
#elif (EMI_MPU_DGROUP_NUM == 2)
#define SET_ACCESS_PERMISSION(apc_ary, lock, d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d4, d3, d2, d1, d0) \
do { \
apc_ary[1] = \
(((unsigned int) d15) << 21) | (((unsigned int) d14) << 18) | (((unsigned int) d13) << 15) | \
(((unsigned int) d12) << 12) | (((unsigned int) d11) << 9) | (((unsigned int) d10) << 6) | \
(((unsigned int) d9) << 3) | ((unsigned int) d8); \
apc_ary[0] = \
(((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | (((unsigned int) d5) << 15) | \
(((unsigned int) d4) << 12) | (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \
(((unsigned int) d1) << 3) | ((unsigned int) d0) | ((unsigned int) lock << 31); \
} while (0)
#endif
struct emi_region_info_t {
unsigned long long start;
unsigned long long end;
unsigned int region;
unsigned int apc[EMI_MPU_DGROUP_NUM];
};
extern int emi_mpu_set_protection(struct emi_region_info_t *region_info);
#endif /* __EMI_MPU_H__ */

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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef MT6516_MEMORY_H
#define MT6516_MEMORY_H
#include <stdint.h>
/**************************************************************************
* DEBUG CONTROL
**************************************************************************/
#define MEM_TEST (1)
// do not change the test size !!!!
#define MEM_TEST_SIZE (0x2000)
/**************************************************************************
* DRAM SIZE
**************************************************************************/
#define E1_DRAM_SIZE (0x10000000)
#define E2_DRAM_SIZE (0x08000000)
/**************************************************************************
* EXPOSED API
**************************************************************************/
extern u32 mt6516_get_hardware_ver (void);
extern void mt6516_mem_init (void);
#if MEM_TEST
extern int complex_mem_test (unsigned int start, unsigned int len);
#endif
#endif

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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef PRINT_H
#define PRINT_H
#include <console/console.h>
//int print(const char *fmt, ...);
#define print(_x_...) printk(BIOS_INFO, _x_)
#define printf print
#endif

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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef REG_H
#define REG_H
#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
#define read32(addr) (*REG32(addr))
#define write32(addr, val) (*REG32(addr) = (val))
#endif

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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef __SV_C_DATA_TRAFFIC_H
#define __SV_C_DATA_TRAFFIC_H
//#define STRINGIFY(x) #x
#define TOSTRING(x) STRINGIFY(x)
#define print_svarg(arg) \
({ \
mcSHOW_DBG_MSG((TOSTRING(arg) "=0x%x\n", psra->arg)); \
})
/*
* channel type from sv's view
*/
enum {
SV_CHN_A = 0,
SV_CHN_B
};
/*
* dram type from sv's view
*/
enum {
SV_LPDDR = 0,
SV_LPDDR2,
SV_PCDDR3,
SV_LPDDR3,
SV_LPDDR4,
SV_LPDDR5
};
/*
* data rate from sv's view
*/
enum {
SV_DDR4266 = 0,
SV_DDR3200,
SV_DDR1600,
SV_DDR3733,
SV_DDR2400,
SV_DDR1866,
SV_DDR1200,
SV_DDR1333,
SV_DDR800,
SV_DDR1066,
SV_DDR2667,
SV_DDR4800,
SV_DDR5500,
SV_DDR6000,
SV_DDR6400,
SV_DDR2750,
SV_DDR2133
};
/*
* cal_sv_rand_args is data traffic from sv to c.
* sv randomizes these arguments for c to control
* calibration.
*/
typedef struct cal_sv_rand_args {
/* >>>>>>>>>> common part begin>>>>>>>>>> */
/*
* 0x4C503435
* "LP45"
*/
int magic;
/*
* 0: channel-a
* 1: channel-b
*/
int calibration_channel;
/*
* 0: rank0
* 1: rank1
*/
int calibration_rank;
/*
* 0: LPDDR
* 1: LPDDR2
* 2: PCDDR3
* 3: LPDDR3
* 4: LPDDR4
* 5: LPDDR5
*/
int dram_type;
/*
* 0: DDR4266
* 1: DDR3200
* 2: DDR1600
* 3: DDR3733
* 4: DDR2400
* 5: DDR1866
* 6: DDR1200
* 7: DDR1333
* 8: DDR800
* 9: DDR1066
* 10: DDR2667
* 11: DDR4800
* 12: DDR5500
* 13: DDR6000
* 14: DDR6400
* 15: DDR2750
* 16: DDR2133
*/
int datarate;
/*
* Data Mask Disable
* 0: enable
* 1: disable
*/
int dmd;
int mr2_value; /* for lp4-wirteleveling*/
int mr3_value;
int mr13_value;
int mr12_value;
int mr16_value;
int mr18_value; /* lp5 writeleveling */
int mr20_value; /* lp5 rddqc */
/* ============================= */
/* >>>>>>>>>> cbt part begin>>>>>>>>>> */
/*
* 0: doesn't run cbt calibration
* 1: run cbt calibration
*/
int cbt;
/*
* 0: rising phase
* 1: falling phase
*/
int cbt_phase;
/*
* 0: training mode1
* 1: training mode2
*/
int cbt_training_mode;
/*
* 0: normal mode
* 1: byte mode
*/
int rk0_cbt_mode;
/*
* 0: normal mode
* 1: byte mode
*/
int rk1_cbt_mode;
/*
* 0: cbt does NOT use autok
* 1: cbt use autok
*/
int cbt_autok;
/*
* autok respi
* 0/1/2/3
*/
int cbt_atk_respi;
/*
* 0: cbt does NOT use new cbt mode
* 1: cbt use new cbt mode
*/
int new_cbt_mode;
/*
* cbt pat0~7v
*/
int pat_v[8];
/*
* cbt pat0~7a
*/
int pat_a[8];
/*
* cbt pat_dmv
*/
int pat_dmv;
/*
* cbt pat_dma
*/
int pat_dma;
/*
* cbt pat_cs
*/
int pat_cs;
/*
* new cbt cagolden sel
*/
int cagolden_sel;
/*
* new cbt invert num
*/
int invert_num;
/* ============================= */
/* >>>>>>>>>> wl part begin>>>>>>>>>> */
/*
* 0: doesn't run wl calibration
* 1: run wl calibration
*/
int wl;
/*
* 0: wl does NOT use autok
* 1: wl use autok
*/
int wl_autok;
/*
* autok respi
* 0/1/2/3
*/
int wl_atk_respi;
/* ============================= */
/* >>>>>>>>>> Gating part begin >>>>>> */
/*
* 0: does not run gating calibration
* 1: run gating calibration
*/
int gating;
/*
* 0: SW mode calibration
* 1: HW AUTO calibration
*/
int gating_autok;
int dqsien_autok_pi_offset;
int dqsien_autok_early_break_en;
int dqsien_autok_dbg_mode_en;
/* ============================= */
/* >>>>>>>>>> RDDQC part begin >>>>>> */
/*
* 0: does not run rddq calibration
* 1: run rddq calibration
*/
int rddqc;
int low_byte_invert_golden;
int upper_byte_invert_golden;
int mr_dq_a_golden;
int mr_dq_b_golden;
int lp5_mr20_6_golden;
int lp5_mr20_7_golden;
/* ============================= */
/* >>>>>>>>>> TX perbit part begin >>>>>> */
/*
* 0: does not run txperbit calibration
* 1: run txperbit calibration
*/
int tx_perbit;
/*
* 0: does not run txperbit auto calibration
* 1: run txperbit auto calibration
*/
int tx_auto_cal;
int tx_atk_pass_pi_thrd;
int tx_atk_early_break;
/* ============================= */
/* >>>>>>>>>> TX perbit part begin >>>>>> */
/*
* 0: does not run rxperbit calibration
* 1: run rxperbit calibration
*/
int rx_perbit;
/*
* 0: does not run rxperbit auto calibration
* 1: run rxperbit auto calibration
*/
int rx_auto_cal;
int rx_atk_cal_step;
int rx_atk_cal_out_dbg_en;
int rx_atk_cal_out_dbg_sel;
/* ============================= */
} cal_sv_rand_args_t;
void set_psra(cal_sv_rand_args_t *psra);
cal_sv_rand_args_t *get_psra(void);
void print_sv_args(cal_sv_rand_args_t *psra);
u8 valid_magic(cal_sv_rand_args_t *psra);
void set_type_freq_by_svargs(DRAMC_CTX_T *p,
cal_sv_rand_args_t *psra);
#endif /* __SV_C_DATA_TRAFFIC_H */

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/* SPDX-License-Identifier: BSD-3-Clause */
#ifndef X_HAL_IO_H
#define X_HAL_IO_H
#include "dramc_pi_api.h"
//===========================================================================
#define REG_ACCESS_NAO_DGB 0
#define REG_ACCESS_PORTING_DGB 0
#define REG_SHUFFLE_REG_CHECK 0
// field access macro-----------------------------------------------------------
/* field macros */
#define Fld(wid, shft) (((U32)wid << 16) | (shft << 8))
#define Fld_wid(fld) ((UINT8)((fld) >> 16))
#define Fld_shft(fld) ((UINT8)((fld) >> 8))
#define Fld_ac(fld) (UINT8)(fld)
/* access method*/
#define AC_FULLB0 1
#define AC_FULLB1 2
#define AC_FULLB2 3
#define AC_FULLB3 4
#define AC_FULLW10 5
#define AC_FULLW21 6
#define AC_FULLW32 7
#define AC_FULLDW 8
#define AC_MSKB0 11
#define AC_MSKB1 12
#define AC_MSKB2 13
#define AC_MSKB3 14
#define AC_MSKW10 15
#define AC_MSKW21 16
#define AC_MSKW32 17
#define AC_MSKDW 18
#define Fld2Msk32(fld) /*lint -save -e504 */ (((U32)0xffffffff>>(32-Fld_wid(fld)))<<Fld_shft(fld)) /*lint -restore */
#define P_Fld(val, fld) ( upk > 0 ? Fld2Msk32(fld): (((UINT32)(val) & ((1 << Fld_wid(fld)) - 1)) << Fld_shft(fld)))
extern U32 u4Dram_Register_Read(DRAMC_CTX_T *p, U32 u4reg_addr);
extern void ucDram_Register_Write(DRAMC_CTX_T *p, U32 u4reg_addr, U32 u4reg_value);
extern void vIO32Write4BMsk2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32);
extern void vIO32Write4BMsk_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32);
extern void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32);
// =========================
// public Macro for general use.
//==========================
#define u4IO32Read4B(reg32) u4Dram_Register_Read(p, reg32)
#define vIO32Write4B(reg32, val32) ucDram_Register_Write(p, reg32, val32)
#define vIO32Write4B_All(reg32, val32) vIO32Write4B_All2(p, reg32, val32)
#define vIO32Write4BMsk(reg32, val32, msk32) vIO32Write4BMsk2(p, reg32, val32, msk32)
#define vIO32Write4BMsk_All(reg32, val32, msk32) vIO32Write4BMsk_All2(p, reg32, val32, msk32)
#define u4IO32ReadFldAlign(reg32, fld) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \
((u4IO32Read4B(reg32) & Fld2Msk32(fld)) >> Fld_shft(fld))
#define vIO32WriteFldAlign(reg32, val, fld) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \
(vIO32Write4BMsk((reg32), ((U32)(val) << Fld_shft(fld)), Fld2Msk32(fld)))
#define vIO32WriteFldMulti(reg32, list) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \
{ \
UINT16 upk = 1; \
INT32 msk = (INT32)(list); \
{ upk = 0; \
((U32)msk == 0xffffffff)? (vIO32Write4B(reg32, (list))): (((U32)msk)? vIO32Write4BMsk(reg32, (list), ((U32)msk)):(U32)0); \
} \
}/*lint -restore */
//=========================
// Public Macro for write all-dramC or all-PHY registers
//=========================
#define vIO32WriteFldAlign_All(reg32, val, fld) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \
(vIO32Write4BMsk_All((reg32), ((U32)(val) << Fld_shft(fld)), Fld2Msk32(fld)))
#define vIO32WriteFldMulti_All(reg32, list) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \
{ \
UINT16 upk = 1; \
INT32 msk = (INT32)(list); \
{ upk = 0; \
((U32)msk == 0xffffffff)? (vIO32Write4B_All(reg32, (list))): (((U32)msk)? vIO32Write4BMsk_All(reg32, (list), ((U32)msk)): (void)0); \
} \
}/*lint -restore */
#ifdef __MD32__
#include "x_hal_io_dpm.h"
#endif
#endif // X_HAL_IO_H