From 0278090e68f0c19e92d0aa320032152cdf829b04 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Wed, 25 May 2022 12:18:35 -0600 Subject: [PATCH] soc/intel/tgl: Add PEG devices to IRQ constraints Fixes IRQ errors on oryp8 that cause conflicts with the PCH HDA device. Change-Id: If0020d9bb6585f7b0fb2dabd3d8b2a3efdd86de2 Signed-off-by: Tim Crawford --- src/soc/intel/tigerlake/fsp_params.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 1cf3d2fee8..e3c7879902 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -93,6 +93,14 @@ static void parse_devicetree(FSP_S_CONFIG *params) * regardless of whether or not they are used by the mainboard. */ static const struct slot_irq_constraints irq_constraints[] = { + { + .slot = SA_DEV_SLOT_PEG, + .fns = { + FIXED_INT_PIRQ(SA_DEVFN_PEG1, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(SA_DEVFN_PEG2, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(SA_DEVFN_PEG3, PCI_INT_C, PIRQ_C), + }, + }, { .slot = SA_DEV_SLOT_IGD, .fns = {