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ACPI: Add usb_charge_mode_from_gnvs()

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Early Chromebook generations stored the information about
USB port power control for S3/S5 sleepstates in GNVS, although
the configuration is static.

Reduce code duplication and react to ACPI S4 as if it was ACPI
S5 request.

Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Kyösti Mälkki
2022-12-02 15:30:10 +02:00
parent 4a9de553c5
commit 027f86e6af
34 changed files with 94 additions and 159 deletions
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7
src/acpi/Kconfig
View File

@@ -29,6 +29,13 @@ config ACPI_SOC_NVS
Set to indicate <soc/nvs.h> exists for the platform with a definition
for global_nvs.
config ACPI_GNVS_USB_CHARGECTL
bool
depends on ACPI_SOC_NVS
help
Set to indicate <soc/nvs.h> implements fields s3u0, s3u1, s5u0, s5u1
to control USB port power rail for S3/S4/S5 sleep states.
config ACPI_CUSTOM_MADT
bool
default n if ACPI_NO_CUSTOM_MADT

27
src/acpi/acpi_pm.c
View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <acpi/acpi_gnvs.h>
#include <acpi/acpi_pm.h>
#include <assert.h>
#include <cbmem.h>
@@ -59,3 +60,29 @@ int acpi_fetch_pm_state(const struct chipset_power_state **ps,
}
return 0;
}
/* Not every <soc/nvs.h> exists and has required fields. */
#if CONFIG(ACPI_GNVS_USB_CHARGECTL) && ENV_SMM
#include <cpu/x86/smm.h>
#include <soc/nvs.h>
void usb_charge_mode_from_gnvs(uint8_t slp_typ, bool *usb0_disable, bool *usb1_disable)
{
if (!gnvs)
return;
switch (slp_typ) {
case ACPI_S3:
*usb0_disable = (gnvs->s3u0 == 0);
*usb1_disable = (gnvs->s3u1 == 0);
break;
case ACPI_S4:
case ACPI_S5:
*usb0_disable = (gnvs->s5u0 == 0);
*usb1_disable = (gnvs->s5u1 == 0);
break;
}
}
#endif /* CONFIG(ACPI_GNVS_USB_CHARGECTL) */