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cpu/intel/car: Fix typo

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Change-Id: If71ab647f012a735c6aa6939463414407757ab9a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes HAOUAS
2018-09-30 07:44:39 +02:00
committed by Patrick Georgi
parent 0562c1e758
commit 02820ca186
3 changed files with 3 additions and 3 deletions
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2
src/cpu/intel/car/core2/cache_as_ram.S
View File

@@ -55,7 +55,7 @@ clear_fixed_mtrr:
wrmsr wrmsr
jnz clear_fixed_mtrr jnz clear_fixed_mtrr
/* Figure put how many MTRRs we have, and clear them out */ /* Figure out how many MTRRs we have, and clear them out */
mov $MTRR_CAP_MSR, %ecx mov $MTRR_CAP_MSR, %ecx
rdmsr rdmsr
movzb %al, %ebx /* Number of variable MTRRs */ movzb %al, %ebx /* Number of variable MTRRs */

2
src/cpu/intel/car/p3/cache_as_ram.S
View File

@@ -43,7 +43,7 @@ clear_fixed_mtrr:
wrmsr wrmsr
jnz clear_fixed_mtrr jnz clear_fixed_mtrr
/* Figure put how many MTRRs we have, and clear them out */ /* Figure out how many MTRRs we have, and clear them out */
mov $MTRR_CAP_MSR, %ecx mov $MTRR_CAP_MSR, %ecx
rdmsr rdmsr
movzb %al, %ebx /* Number of variable MTRRs */ movzb %al, %ebx /* Number of variable MTRRs */

2
src/cpu/intel/car/p4-netburst/cache_as_ram.S
View File

@@ -53,7 +53,7 @@ clear_fixed_mtrr:
wrmsr wrmsr
jnz clear_fixed_mtrr jnz clear_fixed_mtrr
/* Figure put how many MTRRs we have, and clear them out */ /* Figure out how many MTRRs we have, and clear them out */
mov $MTRR_CAP_MSR, %ecx mov $MTRR_CAP_MSR, %ecx
rdmsr rdmsr
movzb %al, %ebx /* Number of variable MTRRs */ movzb %al, %ebx /* Number of variable MTRRs */