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mb/system76: Enable S0ix for darp8/darp9

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The newer batch of these boards do not de-assert VW PLTRST# on S3
resume, causes the units to not power on in the EC code. Switch them to
S0ix by default, but leave S3 available.

Change-Id: I95337c1391102db9e020e82bdd938659c1a4f905
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford 2024-01-08 16:41:32 -07:00
parent 783b4bfc52
commit 028b384807
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GPG Key ID: 68E558D2BBD856E3
2 changed files with 4 additions and 0 deletions
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2
src/mainboard/system76/adl/variants/darp8/overridetree.cb
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@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only # SPDX-License-Identifier: GPL-2.0-only
chip soc/intel/alderlake chip soc/intel/alderlake
register "s0ix_enable" = "1"
register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
.tdp_pl1_override = 20, .tdp_pl1_override = 20,
.tdp_pl2_override = 56, .tdp_pl2_override = 56,

2
src/mainboard/system76/rpl/variants/darp9/overridetree.cb
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@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only # SPDX-License-Identifier: GPL-2.0-only
chip soc/intel/alderlake chip soc/intel/alderlake
register "s0ix_enable" = "1"
register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{ register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{
.tdp_pl1_override = 20, .tdp_pl1_override = 20,
.tdp_pl2_override = 56, .tdp_pl2_override = 56,