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amd/cezanne: Add slow_ppt_time & thermctl_limit to UPD

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These values will be added in the upcoming STAPM configuration update.

BUG=b:185209734
TEST=Build & Boot guybrush

Cq-Depend: chrome-internal:3780259
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I2a6835c16badfe505e3c33b356ca671766cd6972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: chris wang <Chris.Wang@amd.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Martin Roth
2021-04-23 12:22:59 -06:00
committed by Martin Roth
parent 109c4d05d6
commit 029d997b6e
3 changed files with 7 additions and 1 deletions
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4
src/vendorcode/amd/fsp/cezanne/FspmUpd.h
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@ -65,7 +65,9 @@ typedef struct __packed {
/** Offset 0x0405**/ uint8_t cppc_preferred_cores;
/** Offset 0x0406**/ uint8_t stapm_boost;
/** Offset 0x0407**/ uint32_t stapm_time_constant;
/** Offset 0x040B**/ uint8_t smu_soc_tuning_reserved[17];
/** Offset 0x040B**/ uint32_t slow_ppt_time_constant;
/** Offset 0x040F**/ uint32_t thermctl_limit;
/** Offset 0x0413**/ uint8_t smu_soc_tuning_reserved[9];
/** Offset 0x041C**/ uint8_t iommu_support;
/** Offset 0x041D**/ uint8_t pspp_policy;
/** Offset 0x041E**/ uint8_t enable_nb_azalia;