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vc/amd/pi/0067F00: add option to add AGESA binary PI as stage

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Stage addition to CBFS allows relocation to happen on the fly. Take
advantage of that by adding AGESA binary PI as a stage file so that
each instance will be relocated properly within CBFS. Without this
patch Chrome OS having multiple CBFS instances just redirects the
AGESA calls back into RO which is inappropriate.

BUG=b:65442265,b:68141063
TEST=Enabled AGESA_BINARY_PI_AS_STAGE and used ELF file. Booted and
     noted each instance in Chrome OS build was relocated.

Change-Id: Ic0141bc6436a30f855148ff205f28ac9bce30043
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Aaron Durbin
2017-12-12 14:56:41 -07:00
parent ec5a947b44
commit 02b43aa2e0
3 changed files with 70 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/vendorcode/amd/pi/00670F00/Makefile.inc
View File

@ -125,7 +125,15 @@ ramstage-libs += $(agesa_output_path)/libagesa.a
cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_CBFS_NAME)
$(CONFIG_AGESA_CBFS_NAME)-file := $(CONFIG_AGESA_BINARY_PI_FILE)
ifeq ($(CONFIG_AGESA_BINARY_PI_AS_STAGE),y)
$(CONFIG_AGESA_CBFS_NAME)-type := stage
$(CONFIG_AGESA_CBFS_NAME)-options := --xip
# 4KiB alignment to handle any interior alignment. Current AGESA only has
# 64 byte alignment.
$(CONFIG_AGESA_CBFS_NAME)-align := 4096
else
$(CONFIG_AGESA_CBFS_NAME)-type := raw
$(CONFIG_AGESA_CBFS_NAME)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION)
endif
endif

10
src/vendorcode/amd/pi/Kconfig
View File

@ -49,6 +49,15 @@ config AGESA_BINARY_PI_FILE
help
Specify the binary file to use for AMD platform initialization.
config AGESA_BINARY_PI_AS_STAGE
bool "AGESA Binary PI is added as stage to CBFS."
depends on SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_STONEYRIDGE_FP4
help
AGESA will be added as a stage utilizing --xip cbfstool options
as needed relocating the image to the proper location in memory-mapped
cpu address space. It's required that the file be in ELF format
containing the relocations necessary for relocating at runtime.
config AGESA_CBFS_NAME
string
default "AGESA"
@ -56,6 +65,7 @@ config AGESA_CBFS_NAME
config AGESA_BINARY_PI_LOCATION
hex "AGESA PI binary address in ROM"
default 0xFFE00000
depends on !AGESA_BINARY_PI_AS_STAGE
help
Specify the ROM address at which to store the binary Platform
Initialization code.