mb/google/asurada: Add new MT8192 mainboard "Asurada"

The placeholder functions and build rules for generating a minimal
firmware to run on MT8192 SOC based mainboard "Asurada".

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43963
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/asurada/Kconfig

@@ -0,0 +1,52 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# Umbrella option to be selected by variant boards.
+config BOARD_GOOGLE_ASURADA_COMMON
+	def_bool n
+
+if BOARD_GOOGLE_ASURADA_COMMON
+
+config VBOOT
+	select EC_GOOGLE_CHROMEEC_SWITCHES
+	select VBOOT_VBNV_FLASH
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOOTBLOCK_CONSOLE
+	select SOC_MEDIATEK_MT8192
+	select BOARD_ROMSIZE_KB_8192
+	select MAINBOARD_HAS_CHROMEOS
+	select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS
+	select COMMON_CBFS_SPI_WRAPPER
+	select SPI_FLASH
+	select SPI_FLASH_INCLUDE_ALL_DRIVERS
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_BOARDID
+	select EC_GOOGLE_CHROMEEC_SPI
+	select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT
+	select MAINBOARD_HAS_TPM2 if VBOOT
+	select MAINBOARD_HAS_NATIVE_VGA_INIT
+	select MAINBOARD_FORCE_NATIVE_VGA_INIT
+	select HAVE_LINEAR_FRAMEBUFFER
+
+config MAINBOARD_DIR
+	string
+	default "google/asurada"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Asurada" if BOARD_GOOGLE_ASURADA
+
+config DRIVER_TPM_SPI_BUS
+	hex
+	default 0x0
+
+config BOOT_DEVICE_SPI_FLASH_BUS
+	int
+	default 1
+
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+	hex
+	default 0x2
+
+endif

src/mainboard/google/asurada/Kconfig.name

@@ -0,0 +1,5 @@
+comment "Asurada"
+
+config BOARD_GOOGLE_ASURADA
+	bool "->  Asurada"
+	select BOARD_GOOGLE_ASURADA_COMMON

src/mainboard/google/asurada/Makefile.inc

@@ -0,0 +1,14 @@
+bootblock-y += memlayout.ld
+bootblock-y += bootblock.c
+
+verstage-y += memlayout.ld
+verstage-y += reset.c
+
+romstage-y += memlayout.ld
+romstage-y += boardid.c
+
+ramstage-y += memlayout.ld
+ramstage-y += boardid.c
+ramstage-y += chromeos.c
+ramstage-y += mainboard.c
+ramstage-y += reset.c

src/mainboard/google/asurada/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Asurada MediaTek MT8192 reference board
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/google/asurada/boardid.c

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boardid.h>
+
+/* board_id is provided by ec/google/chromeec/ec_boardid.c */
+
+uint32_t sku_id(void)
+{
+	return 0;
+}
+
+uint32_t ram_code(void)
+{
+	return 0;
+}

src/mainboard/google/asurada/bootblock.c

@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+
+void bootblock_mainboard_init(void)
+{
+}

src/mainboard/google/asurada/chromeos.c

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootmode.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <security/tpm/tis.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+}
+
+int get_write_protect_state(void)
+{
+	return 0;
+}
+
+int tis_plat_irq_status(void)
+{
+	return 0;
+}

src/mainboard/google/asurada/chromeos.fmd

@@ -0,0 +1,45 @@
+# Firmware Layout Description for Chrome OS.
+#
+# The size and address of every section must be aligned to at least 4K, except:
+# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.
+#
+# 'FMAP' may be found by binary search so its starting address should be better
+# aligned to larger values.
+#
+# For sections to be preserved on update, add (PRESERVE) to individual sections
+# instead of a group section; otherwise the preserved data may be wrong if you
+# resize or reorder sections inside a group.
+
+FLASH@0x0 8M {
+	WP_RO@0x0 4M {
+		RO_SECTION {
+			BOOTBLOCK 128K
+			FMAP 4K
+			COREBOOT(CBFS)
+			GBB 0x2f00
+			RO_FRID 0x100
+		}
+		RO_VPD(PRESERVE) 32K  # At least 16K.
+	}
+	RW_SECTION_A 1500K {
+		VBLOCK_A 8K
+		FW_MAIN_A(CBFS)
+		RW_FWID_A 0x100
+	}
+	RW_MISC 36K {
+		RW_VPD(PRESERVE) 16K  # At least 8K.
+		RW_NVRAM(PRESERVE) 8K
+		RW_DDR_TRAINING(PRESERVE) 8K
+		RW_ELOG(PRESERVE) 4K  # ELOG driver hard-coded size in 4K.
+	}
+	RW_SECTION_B 1500K {
+		VBLOCK_B 8K
+		FW_MAIN_B(CBFS)
+		RW_FWID_B 0x100
+	}
+	RW_SHARED 36K {  # Will be force updated on recovery.
+		SHARED_DATA 4K  # 4K or less for netboot params.
+		RW_UNUSED
+	}
+	RW_LEGACY(CBFS) 1M  # Minimal 1M.
+}

src/mainboard/google/asurada/devicetree.cb

@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/mediatek/mt8192
+	device cpu_cluster 0 on
+		device cpu 0 on end
+	end
+end

src/mainboard/google/asurada/mainboard.c

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+
+static void mainboard_init(struct device *dev)
+{
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+	.name = CONFIG_MAINBOARD_PART_NUMBER,
+	.enable_dev = mainboard_enable,
+};

src/mainboard/google/asurada/memlayout.ld

@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/memlayout.ld>

src/mainboard/google/asurada/reset.c

@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <reset.h>
+
+void do_board_reset(void)
+{
+}