soc/intel/apollolake: Add function to translate device into ACPI name
Add support for the soc_acpi_name() handler in the device operations structure to translate a device path into ACPI name. In order to make this more complete add some missing devices in include/soc/pci_devs.h. Change-Id: I517bc86d8d9fe70bfa0fc4eb3828681887239587 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15479 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
		| @@ -39,6 +39,72 @@ | |||||||
| static void *vbt; | static void *vbt; | ||||||
| static struct region_device vbt_rdev; | static struct region_device vbt_rdev; | ||||||
|  |  | ||||||
|  | static const char *soc_acpi_name(struct device *dev) | ||||||
|  | { | ||||||
|  | 	if (dev->path.type == DEVICE_PATH_DOMAIN) | ||||||
|  | 		return "PCI0"; | ||||||
|  |  | ||||||
|  | 	if (dev->path.type != DEVICE_PATH_PCI) | ||||||
|  | 		return NULL; | ||||||
|  |  | ||||||
|  | 	switch (dev->path.pci.devfn) { | ||||||
|  | 	/* DSDT: acpi/northbridge.asl */ | ||||||
|  | 	case NB_DEVFN: | ||||||
|  | 		return "MCHC"; | ||||||
|  | 	/* DSDT: acpi/lpc.asl */ | ||||||
|  | 	case LPC_DEVFN: | ||||||
|  | 		return "LPCB"; | ||||||
|  | 	/* DSDT: acpi/xhci.asl */ | ||||||
|  | 	case XHCI_DEVFN: | ||||||
|  | 		return "XHCI"; | ||||||
|  | 	/* DSDT: acpi/pch_hda.asl */ | ||||||
|  | 	case HDA_DEVFN: | ||||||
|  | 		return "HDAS"; | ||||||
|  | 	/* DSDT: acpi/lpss.asl */ | ||||||
|  | 	case LPSS_DEVFN_UART0: | ||||||
|  | 		return "URT1"; | ||||||
|  | 	case LPSS_DEVFN_UART1: | ||||||
|  | 		return "URT2"; | ||||||
|  | 	case LPSS_DEVFN_UART2: | ||||||
|  | 		return "URT3"; | ||||||
|  | 	case LPSS_DEVFN_UART3: | ||||||
|  | 		return "URT4"; | ||||||
|  | 	case LPSS_DEVFN_SPI0: | ||||||
|  | 		return "SPI1"; | ||||||
|  | 	case LPSS_DEVFN_SPI1: | ||||||
|  | 		return "SPI2"; | ||||||
|  | 	case LPSS_DEVFN_SPI2: | ||||||
|  | 		return "SPI3"; | ||||||
|  | 	case LPSS_DEVFN_PWM: | ||||||
|  | 		return "PWM"; | ||||||
|  | 	case LPSS_DEVFN_I2C0: | ||||||
|  | 		return "I2C0"; | ||||||
|  | 	case LPSS_DEVFN_I2C1: | ||||||
|  | 		return "I2C1"; | ||||||
|  | 	case LPSS_DEVFN_I2C2: | ||||||
|  | 		return "I2C2"; | ||||||
|  | 	case LPSS_DEVFN_I2C3: | ||||||
|  | 		return "I2C3"; | ||||||
|  | 	case LPSS_DEVFN_I2C4: | ||||||
|  | 		return "I2C4"; | ||||||
|  | 	case LPSS_DEVFN_I2C5: | ||||||
|  | 		return "I2C5"; | ||||||
|  | 	case LPSS_DEVFN_I2C6: | ||||||
|  | 		return "I2C6"; | ||||||
|  | 	case LPSS_DEVFN_I2C7: | ||||||
|  | 		return "I2C7"; | ||||||
|  | 	/* Storage */ | ||||||
|  | 	case SDCARD_DEVFN: | ||||||
|  | 		return "SDCD"; | ||||||
|  | 	case EMMC_DEVFN: | ||||||
|  | 		return "EMMC"; | ||||||
|  | 	case SDIO_DEVFN: | ||||||
|  | 		return "SDIO"; | ||||||
|  | 	} | ||||||
|  |  | ||||||
|  | 	return NULL; | ||||||
|  | } | ||||||
|  |  | ||||||
| static void pci_domain_set_resources(device_t dev) | static void pci_domain_set_resources(device_t dev) | ||||||
| { | { | ||||||
|        assign_resources(dev->link_list); |        assign_resources(dev->link_list); | ||||||
| @@ -51,6 +117,7 @@ static struct device_operations pci_domain_ops = { | |||||||
| 	.init = NULL, | 	.init = NULL, | ||||||
| 	.scan_bus = pci_domain_scan_bus, | 	.scan_bus = pci_domain_scan_bus, | ||||||
| 	.ops_pci_bus = pci_bus_default_ops, | 	.ops_pci_bus = pci_bus_default_ops, | ||||||
|  | 	.acpi_name = &soc_acpi_name, | ||||||
| }; | }; | ||||||
|  |  | ||||||
| static struct device_operations cpu_bus_ops = { | static struct device_operations cpu_bus_ops = { | ||||||
|   | |||||||
| @@ -35,8 +35,16 @@ | |||||||
| #define NB_DEV_ROOT			_PCI_DEV(0x0, 0) | #define NB_DEV_ROOT			_PCI_DEV(0x0, 0) | ||||||
|  |  | ||||||
| #define P2SB_DEV			_PCI_DEV(0xd, 0) | #define P2SB_DEV			_PCI_DEV(0xd, 0) | ||||||
|  | #define P2SB_DEVFN			_PCI_DEVFN(0xd, 0) | ||||||
|  |  | ||||||
| #define PMC_DEV				_PCI_DEV(0xd, 1) | #define PMC_DEV				_PCI_DEV(0xd, 1) | ||||||
|  | #define PMC_DEVFN			_PCI_DEVFN(0xd, 1) | ||||||
|  |  | ||||||
| #define SPI_DEV				_PCI_DEV(0xd, 2) | #define SPI_DEV				_PCI_DEV(0xd, 2) | ||||||
|  | #define SPI_DEVFN			_PCI_DEVFN(0xd, 2) | ||||||
|  |  | ||||||
|  | #define HDA_DEV				_PCI_DEV(0xe, 0) | ||||||
|  | #define HDA_DEVFN			_PCI_DEVFN(0xe, 0) | ||||||
|  |  | ||||||
| #define ISH_DEV				_PCI_DEV(0x11, 0) | #define ISH_DEV				_PCI_DEV(0x11, 0) | ||||||
| #define ISH_DEVFN			_PCI_DEVFN(0x11, 0) | #define ISH_DEVFN			_PCI_DEVFN(0x11, 0) | ||||||
| @@ -86,6 +94,10 @@ | |||||||
| #define  LPSS_DEVFN_SPI1		_LPSS_PCI_DEVFN(SPI, 1) | #define  LPSS_DEVFN_SPI1		_LPSS_PCI_DEVFN(SPI, 1) | ||||||
| #define  LPSS_DEVFN_SPI2		_LPSS_PCI_DEVFN(SPI, 2) | #define  LPSS_DEVFN_SPI2		_LPSS_PCI_DEVFN(SPI, 2) | ||||||
|  |  | ||||||
|  | /* LPSS PWM */ | ||||||
|  | #define LPSS_DEV_SLOT_PWM		0x1a | ||||||
|  | #define  LPSS_DEVFN_PWM			_LPSS_PCI_DEVFN(PWM, 0) | ||||||
|  |  | ||||||
| #define SDCARD_DEV			_PCI_DEV(0x1b, 0) | #define SDCARD_DEV			_PCI_DEV(0x1b, 0) | ||||||
| #define SDCARD_DEVFN			_PCI_DEVFN(0x1b, 0) | #define SDCARD_DEVFN			_PCI_DEVFN(0x1b, 0) | ||||||
|  |  | ||||||
| @@ -100,4 +112,5 @@ | |||||||
|  |  | ||||||
| #define SMBUS_DEV			_PCI_DEV(0x1f, 1) | #define SMBUS_DEV			_PCI_DEV(0x1f, 1) | ||||||
| #define SMBUS_DEVFN			_PCI_DEVFN(0x1f, 1) | #define SMBUS_DEVFN			_PCI_DEVFN(0x1f, 1) | ||||||
|  |  | ||||||
| #endif | #endif | ||||||
|   | |||||||
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