soc/intel/cannonlake: Correct PMC/GPIO routing information

PMC and GPIO DWx definition is not identical, hence update that to
correct information. For cannonlake lp PCH, GPIO group C, group E and
group GPD is different for PMC GPIO_CFG and GPIO MISCCFG. Also add
function call to set up GPE routing in bootblock stage.

TEST=Boot up into OS, and manually check PMC GPE status

Change-Id: I1edb83edabc72e8a762b129cf51dcd936cd37ddf
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

src/soc/intel/cannonlake/Kconfig

@@ -165,7 +165,7 @@ config VBOOT
 
 config C_ENV_BOOTBLOCK_SIZE
 	hex
-	default 0x4000
+	default 0x8000
 
 config STACK_SIZE
 	hex

src/soc/intel/cannonlake/bootblock/pch.c

@@ -18,6 +18,7 @@
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/rtc.h>
+#include <intelblocks/pmclib.h>
 #include <intelblocks/smbus.h>
 #include <soc/bootblock.h>
 #include <soc/iomap.h>
@@ -192,5 +193,8 @@ void pch_early_init(void)
 	/* Program SMBUS_BASE_ADDRESS and Enable it */
 	smbus_common_init();
 
+	/* Set up GPE configuration */
+	pmc_gpe_init();
+
 	enable_rtc_upper_bank();
 }

src/soc/intel/cannonlake/chip.h

@@ -24,6 +24,7 @@
 #include <soc/pch.h>
 #include <soc/gpio_defs.h>
 #include <soc/pci_devs.h>
+#include <soc/pmc.h>
 #include <soc/serialio.h>
 #include <soc/usb.h>
 #include <soc/vr_config.h>

src/soc/intel/cannonlake/gpio.c

@@ -17,6 +17,7 @@
 #include <intelblocks/gpio.h>
 #include <intelblocks/pcr.h>
 #include <soc/pcr_ids.h>
+#include <soc/pmc.h>
 
 static const struct reset_mapping rst_map[] = {
 	{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
@@ -100,15 +101,15 @@ const struct pad_community *soc_gpio_get_community(size_t *num_communities)
 const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
 {
 	static const struct pmc_to_gpio_route routes[] = {
-		{ GPP_A, GPP_A },
+		{ PMC_GPP_A, GPP_A },
-		{ GPP_B, GPP_B },
+		{ PMC_GPP_B, GPP_B },
-		{ GPP_C, GPP_C },
+		{ PMC_GPP_C, GPP_C },
-		{ GPP_D, GPP_D },
+		{ PMC_GPP_D, GPP_D },
-		{ GPP_E, GPP_E },
+		{ PMC_GPP_E, GPP_E },
-		{ GPP_F, GPP_F },
+		{ PMC_GPP_F, GPP_F },
-		{ GPP_G, GPP_G },
+		{ PMC_GPP_G, GPP_G },
-		{ GPP_H, GPP_H },
+		{ PMC_GPP_H, GPP_H },
-		{ GPD, GPD },
+		{ PMC_GPD, GPD },
 	};
 	*num = ARRAY_SIZE(routes);
 	return routes;

src/soc/intel/cannonlake/include/soc/pmc.h

@@ -116,6 +116,16 @@
 #define  GPE0_DWX_MASK			0xf
 #define  GPE0_DW_SHIFT(x)		(4*(x))
 
+#define  PMC_GPP_A			0x0
+#define  PMC_GPP_B			0x1
+#define  PMC_GPP_C			0xD
+#define  PMC_GPP_D			0x4
+#define  PMC_GPP_E			0xE
+#define  PMC_GPP_F			0x5
+#define  PMC_GPP_G			0x2
+#define  PMC_GPP_H			0x6
+#define  PMC_GPD			0xA
+
 #define GBLRST_CAUSE0			0x1924
 #define   GBLRST_CAUSE0_THERMTRIP	(1 << 5)
 #define GBLRST_CAUSE1			0x1928