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ARM: API to Map Physical Address to Wipe Memory above 4GB

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TEST=Booted nyan in normal and recovery mode. Created a map, filled it with some
chars, then verified they can be read from the pointer returned.
BUG=chrome-os-partner:25587
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>

Original-Change-Id: Id1f1be4f6d2d5734d87bf3452d4806d0fe3fda88
Original-Reviewed-on: https://chromium-review.googlesource.com/188894
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit 7fda3885f51c8d383585a80e99ab3df9c789d872)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I6255d11396c87f40b0ae12ceab0fd152f2478529
Reviewed-on: http://review.coreboot.org/7658
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Daisuke Nojiri
2014-03-05 15:46:28 -08:00
committed by Marc Jones
parent 97345dbc6c
commit 0341169761
5 changed files with 139 additions and 1 deletions
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9
payloads/libpayload/include/arm/arch/cache.h
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@@ -117,6 +117,15 @@ static inline void write_ttbr0(uint32_t val)
asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory");
}
/* read translation table base register 0 (TTBR0) */
static inline uint64_t read_ttbr0(void)
{
uint32_t low, high;
asm volatile ("mrrc p15, 0, %[low], %[high], c2" :
[low] "=r" (low), [high] "=r" (high));
return ((uint64_t)high << 32) | low;
}
/* read translation table base control register (TTBCR) */
static inline uint32_t read_ttbcr(void)
{