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soc/intel: Make use of PMC low power program from common block

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List of changes:
1. Select PMC_LOW_POWER_MODE_PROGRAM from applicable SoC directory
2. Remove redundant PMC programming from SoC and refer to common
code block
3. Remove unused 'reg8' and 'reg32' variable as applicable from SoC
function.

Change-Id: I18894c49cfc6e88675b5fb71bca0412e5639fb4b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45796
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
2020-09-28 18:43:47 +05:30
parent 3e959d8e2a
commit 0359d9dde3
18 changed files with 41 additions and 79 deletions
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13
src/soc/intel/cannonlake/finalize.c
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@@ -9,6 +9,7 @@
#include <device/pci.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/tco.h>
#include <intelblocks/thermal.h>
#include <spi-generic.h>
@@ -44,7 +45,6 @@ static void pch_finalize(void)
uint32_t reg32;
uint8_t *pmcbase;
config_t *config;
uint8_t reg8;
tco_lockdown();
@@ -70,17 +70,12 @@ static void pch_finalize(void)
*/
config = config_of_soc();
pmcbase = pmc_mmio_regs();
if (config->PmTimerDisabled) {
reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
reg8 |= (1 << 1);
write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
}
if (config->PmTimerDisabled)
pmc_disable_acpi_timer();
if (config->s0ix_enable) {
/* Disable XTAL shutdown qualification for low power idle. */
reg32 = read32(pmcbase + CPPMVRIC);
reg32 |= XTALSDQDIS;
write32(pmcbase + CPPMVRIC, reg32);
pmc_ignore_xtal_shutdown();
if (config->cppmvric2_adsposcdis) {
/* Enable Audio DSP OSC qualification for S0ix */