mb/google/brya/var/dochi: Update overridetree for FingerPrint
Update overridetree to correct FP_MCU fw_config settings. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: If76dd8fa3567ed01b11a6d2ba796e8c39807816c Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78454 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@@ -1,9 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootstate.h>
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <fw_config.h>
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#include <fw_config.h>
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#include <gpio.h>
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static const struct pad_config fp_disable_pads[] = {
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static const struct pad_config fp_disable_pads[] = {
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PAD_NC(GPP_D0, NONE), /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */
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PAD_NC(GPP_D0, NONE), /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */
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@@ -11,11 +11,10 @@ static const struct pad_config fp_disable_pads[] = {
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PAD_NC(GPP_D2, NONE), /* D2 : ISH_GP2 ==> EN_FP_PWR */
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PAD_NC(GPP_D2, NONE), /* D2 : ISH_GP2 ==> EN_FP_PWR */
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};
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};
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static void fw_config_handle(void *unused)
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void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
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{
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{
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if (fw_config_probe(FW_CONFIG(FPMCU_MASK, FPMCU_DISABLED))) {
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if (fw_config_probe(FW_CONFIG(FP_MCU, FP_ABSENT))) {
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printk(BIOS_INFO, "Disabling FP pads\n");
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printk(BIOS_INFO, "Configure GPIOs for no FP module.\n");
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gpio_configure_pads(fp_disable_pads, ARRAY_SIZE(fp_disable_pads));
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gpio_padbased_override(padbased_table, fp_disable_pads, ARRAY_SIZE(fp_disable_pads));
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}
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}
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}
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
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@@ -1,7 +1,7 @@
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fw_config
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fw_config
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field FPMCU_MASK 10
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field FP_MCU 9 10
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option FPMCU_DISABLED 0
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option FP_ABSENT 0
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option FPMCU_ENABLED 1
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option FP_MCU_NUVOTON 1
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end
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end
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field STORAGE 30 31
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field STORAGE 30 31
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option STORAGE_UNKNOWN 0
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option STORAGE_UNKNOWN 0
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@@ -279,7 +279,7 @@ chip soc/intel/alderlake
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
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register "enable_delay_ms" = "3"
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register "enable_delay_ms" = "3"
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device spi 0 on
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device spi 0 on
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probe FPMCU_MASK FPMCU_ENABLED
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probe FP_MCU FP_MCU_NUVOTON
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end
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end
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end # FPMCU
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end # FPMCU
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end
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end
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@@ -6,6 +6,6 @@
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void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
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void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
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{
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{
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if (fw_config_probe(FW_CONFIG(FPMCU_MASK, FPMCU_DISABLED)))
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if (fw_config_probe(FW_CONFIG(FP_MCU, FP_ABSENT)))
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config->serial_io_gspi_mode[PchSerialIoIndexGSPI1] = PchSerialIoDisabled;
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config->serial_io_gspi_mode[PchSerialIoIndexGSPI1] = PchSerialIoDisabled;
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}
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}
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