From 0365fc81860a2fa1b60bc64cece0af1a61f12105 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 7 Dec 2021 00:38:29 +0100 Subject: [PATCH] sb/amd/pi/hudson/early_init: fix setting SPI_USE_SPI100 in SPI100_ENABLE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities. Haven't checked the reference code, but the register descriptions suggested that the register in Mullins behaves similar to the one in Stoneyridge. Right now this code is unused, but it's probably still a good idea to fix it. TEST=Booting Debian 11 with kernel 5.10 on apu2 still works when adding a call to hudson_set_spi100 with this patch applied. Signed-off-by: Felix Held Change-Id: Ifbd960a9509542b28f03326a3066995540260bef Tested-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/59934 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson Reviewed-by: Michał Żygowski --- src/southbridge/amd/pi/hudson/early_setup.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 20597d43da..26179859cc 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -215,7 +215,8 @@ void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) (fast << SPI_FAST_SPEED_NEW_SH) | (alt << SPI_ALT_SPEED_NEW_SH) | (tpm << SPI_TPM_SPEED_NEW_SH)); - write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); + write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100 | + read16((void *)(base + SPI100_ENABLE))); } void hudson_disable_4dw_burst(void)