mb/google/brya: Add new baseboard trulo

This patch adds a new baseboard trulo. This commit is a stub which
only adds the minimum code needed for a successful build.

BUG=b:333314089
TEST=abuild -a -x -p none -t google/brya

Change-Id: Iad6230064c6b8359698d37c3e0440614cc7b073d
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>

src/mainboard/google/brya/Kconfig

@@ -99,6 +99,22 @@ config BOARD_GOOGLE_BASEBOARD_NISSA
 	select TPM_GOOGLE_TI50
 	select SOC_INTEL_COMMON_MMC_OVERRIDE
 
+config BOARD_GOOGLE_BASEBOARD_TRULO
+	def_bool n
+	select BOARD_GOOGLE_BRYA_COMMON
+	select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768
+	select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
+	select DRIVERS_AUDIO_SOF
+	select DRIVERS_INTEL_ISH
+	select MAINBOARD_DISABLE_STAGE_CACHE
+	select MEMORY_SOLDERDOWN
+	select SOC_INTEL_COMMON_MMC_OVERRIDE
+	select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
+	select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
+	select SOC_INTEL_TWINLAKE
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_GOOGLE_TI50
+
 config BOARD_GOOGLE_AGAH
 	select BOARD_GOOGLE_BASEBOARD_BRYA
 	select DRIVERS_GENESYSLOGIC_GL9750
@@ -556,6 +572,7 @@ config BASEBOARD_DIR
 	default "brask" if BOARD_GOOGLE_BASEBOARD_BRASK
 	default "hades" if BOARD_GOOGLE_BASEBOARD_HADES
 	default "nissa" if BOARD_GOOGLE_BASEBOARD_NISSA
+	default "trulo" if BOARD_GOOGLE_BASEBOARD_TRULO
 
 config CHROMEOS
 	select EC_GOOGLE_CHROMEEC_SWITCHES
@@ -636,8 +653,8 @@ config DRIVER_TPM_I2C_ADDR
 
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-serger.fmd" if CHROMEOS && BOARD_GOOGLE_BRASK
-	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB-debugfsp.fmd" if CHROMEOS && BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_16384 && BUILDING_WITH_DEBUG_FSP
-	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if CHROMEOS && BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_16384
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB-debugfsp.fmd" if CHROMEOS && (BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) && BOARD_ROMSIZE_KB_16384 && BUILDING_WITH_DEBUG_FSP
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if CHROMEOS && (BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) && BOARD_ROMSIZE_KB_16384
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
 
 config TPM_TIS_ACPI_INTERRUPT
@@ -657,6 +674,7 @@ config MAINBOARD_FAMILY
 	default "Google_Brask" if BOARD_GOOGLE_BASEBOARD_BRASK
 	default "Google_Hades" if BOARD_GOOGLE_BASEBOARD_HADES
 	default "Google_Nissa" if BOARD_GOOGLE_BASEBOARD_NISSA
+	default "Google_Trulo" if BOARD_GOOGLE_BASEBOARD_TRULO
 
 config MAINBOARD_PART_NUMBER
 	default "Agah" if BOARD_GOOGLE_AGAH

src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk

@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+romstage-y += memory.c
+romstage-y += gpio.c
+
+ramstage-y += gpio.c

src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb

@@ -0,0 +1,4 @@
+chip soc/intel/alderlake
+	device domain 0 on
+	end
+end

src/mainboard/google/brya/variants/baseboard/trulo/gpio.c

@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+#include <types.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+	/* TODO */
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* TODO */
+};
+
+const struct pad_config *__weak variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *__weak variant_gpio_override_table(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}
+
+const struct pad_config *__weak variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	/* TODO */
+};
+DECLARE_CROS_GPIOS(cros_gpios);
+
+const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}

src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <baseboard/gpio.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+
+/* TODO: Set the correct values */
+#define MAINBOARD_EC_SCI_EVENTS		0
+#define MAINBOARD_EC_SMI_EVENTS		0
+#define MAINBOARD_EC_S5_WAKE_EVENTS	0
+#define MAINBOARD_EC_S3_WAKE_EVENTS	0
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS	0
+#define MAINBOARD_EC_LOG_EVENTS		0
+
+#endif /* __BASEBOARD_EC_H__ */

src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/gpio.h

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* TODO: Set the correct values */
+#define EC_SCI_GPI		0
+#define GPIO_PCH_WP		0
+#define GPIO_EC_IN_RW		0
+#define GPIO_SLP_S0_GATE	0
+
+#endif /* __BASEBOARD_GPIO_H__ */

src/mainboard/google/brya/variants/baseboard/trulo/memory.c

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+
+const struct mb_cfg *__weak variant_memory_params(void)
+{
+	/* TODO */
+	return NULL;
+}
+
+bool __weak variant_is_half_populated(void)
+{
+	/* TODO */
+	return false;
+}
+
+void __weak variant_get_spd_info(struct mem_spd *spd_info)
+{
+	/* TODO */
+}