aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK

This board is the only user of these ancient chipsets,
so we'll do all in one go.

Also wipe out some extra headers.

Change-Id: I22c172d577e6072562d8fcfa58145ec62473823e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/cpu/intel/socket_mPGA604/Kconfig

@@ -10,6 +10,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
 	select SSE
 	select UDELAY_TSC
 	select SIPI_VECTOR_IN_ROM
+	select C_ENVIRONMENT_BOOTBLOCK
 
 # mPGA604 are usually Intel Netburst CPUs which should have SSE2
 # but the ramtest.c code on the Dell S1850 seems to choke on
@@ -26,4 +27,8 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x4000
 
+config DCACHE_BSP_STACK_SIZE
+	hex
+	default 0x2000
+
 endif # CPU_INTEL_SOCKET_MPGA604

src/cpu/intel/socket_mPGA604/Makefile.inc

@@ -7,6 +7,8 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 
-cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
+bootblock-y += ../car/p4-netburst/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
+
 postcar-y += ../car/p4-netburst/exit_car.S
 romstage-y += ../car/romstage.c