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src/soc: Capitalize CPU, ACPI, RAM and ROM

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Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15963
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS
2016-07-29 18:31:16 +02:00
committed by Martin Roth
parent f9e7d1b0ca
commit 038e7247dc
41 changed files with 54 additions and 54 deletions
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4
src/soc/intel/baytrail/include/soc/iosf.h
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@@ -185,11 +185,11 @@ void iosf_ssus_write(int reg, uint32_t val);
#define BNOCACHE 0x23
/* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */
#define BUNIT_BMBOUND 0x25
/* BMBOUND_HI describes the available ram above 4GiB. It has a
/* BMBOUND_HI describes the available RAM above 4GiB. It has a
* 256MiB granularity. Physical address bits 35:28 are compared with 31:24
* bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB
* granularity care needs to be taken with the e820 map to account for a hole
* in the ram. */
* in the RAM. */
#define BUNIT_BMBOUND_HI 0x26
#define BUNIT_MMCONF_REG 0x27
/* The SMMRR registers define the SMM region in MiB granularity. */

4
src/soc/intel/baytrail/romstage/romstage.c
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@@ -305,7 +305,7 @@ static void *setup_stack_and_mttrs(void)
num_mtrrs++;
top_of_ram = (uint32_t)cbmem_top();
/* Cache 8MiB below the top of ram. The top of ram under 4GiB is the
/* Cache 8MiB below the top of ram. The top of RAM under 4GiB is the
* start of the TSEG region. It is required to be 8MiB aligned. Set
* this area as cacheable so it can be used later for ramstage before
* setting up the entire RAM as cacheable. */
@@ -315,7 +315,7 @@ static void *setup_stack_and_mttrs(void)
slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
num_mtrrs++;
/* Cache 8MiB at the top of ram. Top of ram is where the TSEG
/* Cache 8MiB at the top of ram. Top of RAM is where the TSEG
* region resides. However, it is not restricted to SMM mode until
* SMM has been relocated. By setting the region to cacheable it
* provides faster access when relocating the SMM handler as well