From 03b392355c84a5c868a96470e1b96e3d422fb85a Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 23 May 2022 15:32:00 +0800 Subject: [PATCH] mb/google/rex: Add flashmap descriptor Add 32MB flashmap descriptor as below: Descriptor Region -> 0 - 0x3fff (~16KB) CSE Partition -> 0x4000 - 0x8fffff (~9MB) BIOS Region -> 0x900000 - 0x1ffffff (23MB) BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai Signed-off-by: Subrata Banik Change-Id: Ia5ced770bb02c11a9ab39837e66562d2ee22b6e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64590 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/rex/chromeos.fmd | 54 +++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 src/mainboard/google/rex/chromeos.fmd diff --git a/src/mainboard/google/rex/chromeos.fmd b/src/mainboard/google/rex/chromeos.fmd new file mode 100644 index 0000000000..334cddaf7b --- /dev/null +++ b/src/mainboard/google/rex/chromeos.fmd @@ -0,0 +1,54 @@ +FLASH 32M { + SI_ALL 9M { + SI_DESC 16K + SI_ME + } + SI_BIOS 23M { + RW_SECTION_A 6M { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + ME_RW_A(CBFS) 3008K + } + RW_LEGACY(CBFS) 2M + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory. + # It is placed in the common `chromeos.fmd` file because it is only 4K and there + # is free space in the RW_MISC region that cannot be easily reclaimed because + # the RW_SECTION_B must start on the 16M boundary. + RW_SPD_CACHE(PRESERVE) 4K + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 6M { + VBLOCK_B 64K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + ME_RW_B(CBFS) 3008K + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 8M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +}