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mb/system76/gaze14: Reduce from 4 to 2 variants

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GPIOs for 15/17 models appear to be the same. It may be possible to use
a single variant like how it was done for gaze15.

Change-Id: Iae8ef8a733ed8c46151705d7ae240fbfa013662f
This commit is contained in:
Tim Crawford
2021-04-09 13:20:59 -06:00
committed by Jeremy Soller
parent e67769d719
commit 03f477d395
21 changed files with 590 additions and 705 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
src/mainboard/system76/gaze14/Kconfig
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@@ -1,4 +1,4 @@
if BOARD_SYSTEM76_GAZE14_1650_15 || BOARD_SYSTEM76_GAZE14_1650_17 || BOARD_SYSTEM76_GAZE14_1660TI_15 || BOARD_SYSTEM76_GAZE14_1660TI_17
if BOARD_SYSTEM76_GAZE14_1650 || BOARD_SYSTEM76_GAZE14_1660TI
config BOARD_SPECIFIC_OPTIONS
def_bool y
@@ -24,19 +24,20 @@ config BOARD_SPECIFIC_OPTIONS
select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP
select TPM_RDRESP_NEED_DELAY
select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
select USE_OPTION_TABLE
config MAINBOARD_DIR
string
default "system76/gaze14"
config MAINBOARD_PART_NUMBER
string
default "gaze14"
config VARIANT_DIR
string
default "gaze14_1650_15" if BOARD_SYSTEM76_GAZE14_1650_15
default "gaze14_1650_17" if BOARD_SYSTEM76_GAZE14_1650_17
default "gaze14_1660ti_15" if BOARD_SYSTEM76_GAZE14_1660TI_15
default "gaze14_1660ti_17" if BOARD_SYSTEM76_GAZE14_1660TI_17
default "gaze14_1650" if BOARD_SYSTEM76_GAZE14_1650
default "gaze14_1660ti" if BOARD_SYSTEM76_GAZE14_1660TI
config MAINBOARD_SMBIOS_PRODUCT_NAME
string
@@ -74,14 +75,6 @@ config DIMM_SPD_SIZE
int
default 512
# config VGA_BIOS_FILE
# string
# default "pci8086,3ea0.rom"
# config VGA_BIOS_ID
# string
# default "8086,3ea0"
config POST_DEVICE
bool
default n

14
src/mainboard/system76/gaze14/Kconfig.name
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@@ -1,11 +1,5 @@
config BOARD_SYSTEM76_GAZE14_1650_15
bool "gaze14 1650 15"
config BOARD_SYSTEM76_GAZE14_1650
bool "gaze14 1650"
config BOARD_SYSTEM76_GAZE14_1650_17
bool "gaze14 1650 17"
config BOARD_SYSTEM76_GAZE14_1660TI_15
bool "gaze14 1660Ti 15"
config BOARD_SYSTEM76_GAZE14_1660TI_17
bool "gaze14 1660Ti 17"
config BOARD_SYSTEM76_GAZE14_1660TI
bool "gaze14 1660Ti"

4
src/mainboard/system76/gaze14/bootblock.c
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@@ -3,9 +3,11 @@
#include <bootblock_common.h>
#include <gpio.h>
#include "gpio.h"
#include <drivers/system76/dgpu/bootblock.c>
void bootblock_mainboard_init(void) {
void bootblock_mainboard_init(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
dgpu_power_enable(1);
}

5
src/mainboard/system76/gaze14/devicetree.cb
View File

@@ -16,9 +16,6 @@ chip soc/intel/cannonlake
.tdp_pl2_override = 90,
}"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
# Enable Enhanced Intel SpeedStep
register "eist_enable" = "1"
@@ -70,7 +67,7 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[8]" = "8"
end
device pci 02.0 on # Integrated Graphics Device
register "gfx" = "GMBA_DEFAULT_PANEL(0)"
register "gfx" = "GMA_DEFAULT_PANEL(0)"
end
device pci 04.0 on # SA Thermal device
register "Device4Enable" = "1"

4
src/mainboard/system76/gaze14/dsdt.asl
View File

@@ -7,10 +7,10 @@ DefinitionBlock(
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725 // OEM revision
0x20110725 /* OEM revision */
)
{
#include <soc/intel/cannonlake/acpi/platform.asl>
#include <soc/intel/common/block/acpi/acpi/platform.asl>
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>

4
src/mainboard/system76/gaze14/gpio.h
View File

@@ -1 +1,5 @@
#define DGPU_RST_N GPP_F22
#define DGPU_PWR_EN GPP_F23
#define DGPU_GC6 GPP_K21
#include <variant/gpio.h>

BIN
src/mainboard/system76/gaze14/variants/gaze14_1650/data.vbt Normal file
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Binary file not shown.

5
src/mainboard/system76/gaze14/variants/gaze14_1650_15/hda_verb.c → src/mainboard/system76/gaze14/variants/gaze14_1650/hda_verb.c
View File

@@ -1,8 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef HDA_VERB_H
#define HDA_VERB_H
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
@@ -34,5 +31,3 @@ const u32 cim_verb_data[] = {
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;
#endif

272
src/mainboard/system76/gaze14/variants/gaze14_1650/include/variant/gpio.h Normal file
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@@ -0,0 +1,272 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
#include <soc/gpe.h>
#include <soc/gpio.h>
#ifndef __ACPI__
static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
};
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_NC(GPD0, NONE), // PM_BATLOW#
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP#
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
PAD_NC(GPD6, NONE), // SLP_A#
PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD_7 (crystal input)
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
PAD_NC(GPD9, NONE), // PCH_SLP_WLAN#
PAD_NC(GPD10, NONE),
PAD_NC(GPD11, NONE), // LAN_DISABLE_N
/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
PAD_NC(GPP_A7, NONE),
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC
PAD_NC(GPP_A10, NONE),
PAD_CFG_GPI(GPP_A11, NONE, DEEP), // LAN_WAKEUP#
PAD_NC(GPP_A12, NONE), // ISH_GP_6_R
PAD_NC(GPP_A13, NONE), // SUSWARN#
PAD_NC(GPP_A14, NONE), // S4_STATE#
PAD_NC(GPP_A15, NONE), // SUS_PWR_ACK
PAD_NC(GPP_A16, NONE),
PAD_NC(GPP_A17, NONE),
PAD_CFG_GPO(GPP_A18, 1, DEEP), // SB_BLON
PAD_NC(GPP_A19, NONE),
PAD_NC(GPP_A20, NONE),
PAD_NC(GPP_A21, NONE), // 3G_CONFIG2
PAD_CFG_GPO(GPP_A22, 0, DEEP), // SATA_PWR_EN
PAD_NC(GPP_A23, NONE), // DGPU_PWM_SELECT#
/* ------- GPIO Group GPP_B ------- */
PAD_CFG_GPI(GPP_B0, NONE, DEEP), // TPM_PIRQ#
PAD_NC(GPP_B1, NONE),
PAD_NC(GPP_B2, NONE), // VRALERTB#
PAD_NC(GPP_B3, NONE),
PAD_NC(GPP_B4, NONE), // EXTTS_SNI_DRV1
PAD_NC(GPP_B5, NONE),
PAD_NC(GPP_B6, NONE),
PAD_NC(GPP_B7, NONE),
PAD_NC(GPP_B8, NONE),
PAD_NC(GPP_B9, NONE),
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // LAN_CLKREQ#
PAD_CFG_GPI(GPP_B11, UP_20K, DEEP), // TODO: GPP_B11: DDR Voltage select - 0 = 1.2V, 1 = 1.35V
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
PAD_NC(GPP_B15, NONE),
PAD_NC(GPP_B16, NONE),
PAD_NC(GPP_B17, NONE),
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), // NO REBOOT strap
PAD_NC(GPP_B19, NONE),
PAD_NC(GPP_B20, NONE),
PAD_NC(GPP_B21, NONE),
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), // LPC/SPI BOOT strap
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), // DCI BSSB mode strap
/* ------- GPIO Group GPP_C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPI(GPP_C2, NONE, DEEP), // SKIN_THRM_SNSR_ALERT_N
PAD_NC(GPP_C3, NONE), // SML0_CLK
PAD_NC(GPP_C4, NONE), // SML0_DATA
PAD_NC(GPP_C5, NONE),
PAD_NC(GPP_C6, NONE), // SMC_CPU_THERM
PAD_NC(GPP_C7, NONE), // SMD_CPU_THERM
PAD_NC(GPP_C8, NONE),
PAD_CFG_GPO(GPP_C9, 1, DEEP), // TODO: CNVI_DET#
PAD_NC(GPP_C10, NONE),
PAD_NC(GPP_C11, NONE),
PAD_NC(GPP_C12, NONE),
PAD_NC(GPP_C13, NONE),
PAD_NC(GPP_C14, NONE),
PAD_NC(GPP_C15, NONE),
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SDA_TP
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SCL_TP
PAD_NC(GPP_C18, NONE),
PAD_NC(GPP_C19, NONE),
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_NC(GPP_C22, NONE),
PAD_NC(GPP_C23, NONE),
/* ------- GPIO Group GPP_D ------- */
PAD_NC(GPP_D0, NONE),
PAD_NC(GPP_D1, NONE),
PAD_NC(GPP_D2, NONE),
PAD_NC(GPP_D3, NONE),
PAD_NC(GPP_D4, NONE),
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RF_RST#
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ
PAD_NC(GPP_D7, NONE),
PAD_NC(GPP_D8, NONE),
PAD_NC(GPP_D9, NONE),
PAD_NC(GPP_D10, NONE),
PAD_NC(GPP_D11, NONE),
PAD_NC(GPP_D12, NONE),
PAD_NC(GPP_D13, NONE),
PAD_NC(GPP_D14, NONE),
PAD_NC(GPP_D15, NONE),
PAD_NC(GPP_D16, NONE),
PAD_NC(GPP_D17, NONE),
PAD_NC(GPP_D18, NONE),
PAD_NC(GPP_D19, NONE),
PAD_NC(GPP_D20, NONE),
PAD_NC(GPP_D21, NONE),
PAD_NC(GPP_D22, NONE),
PAD_NC(GPP_D23, NONE),
/* ------- GPIO Group GPP_E ------- */
PAD_NC(GPP_E0, NONE), // SATAGP0
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // SATAGP1
PAD_NC(GPP_E2, NONE), // SATAGP2
PAD_NC(GPP_E3, NONE), // EXTTS_SNI_DRV0
PAD_CFG_GPI(GPP_E4, NONE, DEEP), // DEVSLP0
PAD_CFG_GPI(GPP_E5, NONE, DEEP), // DEVSLP1
PAD_NC(GPP_E6, NONE), // PCH_MUTE#
_PAD_CFG_STRUCT(GPP_E7, 0x40800100, 0x3000), // TODO: TP_ATTN#
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
PAD_NC(GPP_E9, NONE),
PAD_NC(GPP_E10, NONE),
PAD_NC(GPP_E11, NONE),
PAD_NC(GPP_E12, NONE),
/* ------- GPIO Group GPP_F ------- */
PAD_NC(GPP_F0, NONE), // SATAGP3
PAD_NC(GPP_F1, NONE),
PAD_NC(GPP_F2, NONE),
PAD_NC(GPP_F3, NONE),
PAD_NC(GPP_F4, NONE),
PAD_CFG_GPI(GPP_F5, NONE, DEEP), // KBLED_DET
PAD_CFG_GPI(GPP_F6, NONE, DEEP), // LIGHT_KB_DET#
PAD_NC(GPP_F7, NONE),
PAD_NC(GPP_F8, NONE),
PAD_NC(GPP_F9, NONE),
PAD_NC(GPP_F10, NONE), // BIOS_REC - BIOS RECOVERY ENABLE strap
PAD_NC(GPP_F11, NONE), // PCH_RSVD - unused strap
PAD_NC(GPP_F12, NONE), // MFG_MODE - Manufacturing mode strap
PAD_NC(GPP_F13, NONE), // GP39_GFX_CRB_DETECT - 0 = normal gfx, 1 = customer gfx
PAD_CFG_GPI(GPP_F14, NONE, DEEP), // H_SKTOCC_N
PAD_NC(GPP_F15, NONE),
PAD_NC(GPP_F16, NONE),
PAD_NC(GPP_F17, NONE),
PAD_NC(GPP_F18, NONE),
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH
PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN
/* ------- GPIO Group GPP_G ------- */
PAD_CFG_GPI(GPP_G0, NONE, DEEP), // BOARD_ID1
PAD_CFG_GPI(GPP_G1, NONE, DEEP), // BOARD_ID2
PAD_CFG_GPI(GPP_G2, NONE, DEEP), // TPM_DET
PAD_CFG_GPI(GPP_G3, UP_20K, DEEP), // TODO: GPIO4_1V8_MAIN_EN_R
PAD_NC(GPP_G4, NONE),
PAD_NC(GPP_G5, NONE),
PAD_NC(GPP_G6, NONE),
PAD_NC(GPP_G7, NONE),
/* ------- GPIO Group GPP_H ------- */
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
PAD_NC(GPP_H1, NONE),
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
PAD_NC(GPP_H3, NONE),
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD_CLKREQ#
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // SSD2_CLKREQ#
PAD_NC(GPP_H6, NONE),
PAD_NC(GPP_H7, NONE),
PAD_NC(GPP_H8, NONE),
PAD_NC(GPP_H9, NONE),
PAD_NC(GPP_H10, NONE),
PAD_NC(GPP_H11, NONE),
PAD_CFG_GPI(GPP_H12, NONE, DEEP), // ESPI FLASH SHARING MODE strap
PAD_NC(GPP_H13, NONE),
PAD_NC(GPP_H14, NONE),
PAD_NC(GPP_H15, NONE),
PAD_NC(GPP_H16, NONE),
PAD_NC(GPP_H17, NONE),
PAD_NC(GPP_H18, NONE),
PAD_NC(GPP_H19, NONE),
PAD_NC(GPP_H20, NONE),
PAD_NC(GPP_H21, NONE),
PAD_NC(GPP_H22, NONE),
PAD_NC(GPP_H23, NONE), // DGPU_SELECT#
/* ------- GPIO Group GPP_I ------- */
PAD_NC(GPP_I0, NONE),
PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), // HDMI_HPD
PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000), // MDP_E_HPD
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HPD
PAD_NC(GPP_I5, NONE),
PAD_NC(GPP_I6, NONE),
PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), // HDMI_CTRLCLK
PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), // HDMI_CTRLDATA
PAD_NC(GPP_I9, NONE),
PAD_NC(GPP_I10, NONE),
PAD_CFG_GPI(GPP_I11, NONE, DEEP), // H_SKTOCC_N
PAD_NC(GPP_I12, NONE),
PAD_NC(GPP_I13, NONE),
PAD_NC(GPP_I14, NONE),
/* ------- GPIO Group GPP_J ------- */
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_NC(GPP_J1, NONE),
PAD_NC(GPP_J2, NONE),
PAD_NC(GPP_J3, NONE),
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
PAD_NC(GPP_J10, NONE),
PAD_NC(GPP_J11, NONE),
/* ------- GPIO Group GPP_K ------- */
PAD_NC(GPP_K0, NONE),
PAD_NC(GPP_K1, NONE),
PAD_NC(GPP_K2, NONE),
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), // SCI#
PAD_NC(GPP_K4, NONE),
PAD_NC(GPP_K5, NONE),
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x3000), // SWI#
PAD_NC(GPP_K7, NONE),
PAD_CFG_GPO(GPP_K8, 1, DEEP), // SATA_M2_PWR_EN1
PAD_CFG_GPO(GPP_K9, 1, DEEP), // SATA_M2_PWR_EN2
PAD_NC(GPP_K10, NONE),
PAD_NC(GPP_K11, NONE),
PAD_NC(GPP_K12, NONE),
PAD_NC(GPP_K13, NONE),
PAD_NC(GPP_K14, NONE), // GPP_K_14_GSXDIN
PAD_NC(GPP_K15, NONE),
PAD_NC(GPP_K16, NONE),
PAD_NC(GPP_K17, NONE),
PAD_NC(GPP_K18, NONE),
_PAD_CFG_STRUCT(GPP_K19, 0x42000100, 0x3000), // SMI#
PAD_CFG_GPI(GPP_K20, NONE, DEEP), // GPU_EVENT#
PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN_PCH
PAD_CFG_GPI(GPP_K22, NONE, DEEP), // DGPU_PWRGD_R
PAD_NC(GPP_K23, NONE), // DGPU_PRSNT#
};
#endif
#endif

0
src/mainboard/system76/gaze14/variants/gaze14_1650_15/overridetree.cb → src/mainboard/system76/gaze14/variants/gaze14_1650/overridetree.cb
View File

276
src/mainboard/system76/gaze14/variants/gaze14_1650_15/include/variant/gpio.h
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@@ -1,276 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
#include <soc/gpe.h>
#include <soc/gpio.h>
#ifndef __ACPI__
/* Early pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_NC(GPP_C22, NONE), // NC
PAD_NC(GPP_C23, NONE), // NC
};
/* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
PAD_CFG_GPI(GPD2, NATIVE, PWROK), // NC
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
_PAD_CFG_STRUCT(GPD6, 0x44000601, 0x0000), // NC
_PAD_CFG_STRUCT(GPD7, 0x04000300, 0x0000), // NC
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK_R
PAD_CFG_GPI(GPD9, NONE, PWROK), // NC
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // NC
PAD_CFG_TERM_GPO(GPD11, 0, NONE, PWROK), // NC
/* ------- GPIO Group A ------- */
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // NC
PAD_CFG_GPI(GPP_A11, NONE, DEEP), // TODO: LAN_WAKEUP#
PAD_CFG_GPI(GPP_A12, NONE, DEEP), // NC
PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1), // SUSWARN#
PAD_CFG_TERM_GPO(GPP_A14, 0, DN_20K, DEEP), // NC
PAD_CFG_GPI(GPP_A15, NONE, DEEP), // SUS_PWR_ACK
PAD_NC(GPP_A16, NONE), // NC
PAD_NC(GPP_A17, NONE), // NC
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), // SB_BLON
PAD_NC(GPP_A19, NONE), // NC
PAD_NC(GPP_A20, NONE), // NC
PAD_NC(GPP_A21, NONE), // NC
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP), // SATA_PWR_EN
PAD_NC(GPP_A23, NONE), // NC
/* ------- GPIO Group B ------- */
PAD_CFG_GPI(GPP_B0, NONE, DEEP), // TODO: TPM_PIRQ#
PAD_CFG_TERM_GPO(GPP_B1, 0, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_B2, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_B3, NONE, DEEP), // NC
PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP), // TODO: EXTTS_SNI_DRV1
PAD_CFG_GPI(GPP_B5, NONE, PLTRST), // NC
PAD_CFG_GPI(GPP_B6, NONE, PLTRST), // NC
PAD_CFG_GPI(GPP_B7, NONE, PLTRST), // NC
PAD_CFG_GPI(GPP_B8, NONE, PLTRST), // NC
PAD_CFG_GPI(GPP_B9, NONE, PLTRST), // NC
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // LAN_CLKREQ#
PAD_CFG_GPI(GPP_B11, UP_20K, DEEP), // TODO: GPP_B11: DDR Voltage select - 0 = 1.2V, 1 = 1.35V
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
PAD_NC(GPP_B15, NONE), // NC
PAD_CFG_GPI(GPP_B16, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_B17, NONE, DEEP), // NC
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), // LPSS_GSPI0_MOSI - strap for no reboot mode
PAD_NC(GPP_B19, NONE), // NC
PAD_NC(GPP_B20, NONE), // NC
PAD_NC(GPP_B21, NONE), // NC
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), // LPSS_GSPI1_MOSI - strap for booting from SPI or LPC
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), // PCH_HOT_GNSS_DISABLE - strap for DCI BSSB mode
/* ------- GPIO Group C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPI(GPP_C2, NONE, DEEP), // NC
PAD_NC(GPP_C3, NONE), // NC
PAD_NC(GPP_C4, NONE), // NC
PAD_CFG_GPI(GPP_C5, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_C6, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_C7, NONE, DEEP), // NC
PAD_NC(GPP_C8, NONE), // NC
PAD_CFG_TERM_GPO(GPP_C9, 1, NONE, DEEP), // TODO: CNVI_DET#
PAD_NC(GPP_C10, NONE), // NC
PAD_NC(GPP_C11, NONE), // NC
PAD_NC(GPP_C12, NONE), // NC
PAD_NC(GPP_C13, NONE), // NC
PAD_NC(GPP_C14, NONE), // NC
PAD_NC(GPP_C15, NONE), // NC
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SCL_TP
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SDA_TP
PAD_NC(GPP_C18, NONE), // NC
PAD_NC(GPP_C19, NONE), // NC
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), // NC
/* ------- GPIO Group D ------- */
PAD_NC(GPP_D0, NONE), // NC
PAD_NC(GPP_D1, NONE), // NC
PAD_NC(GPP_D2, NONE), // NC
PAD_NC(GPP_D3, NONE), // NC
PAD_NC(GPP_D4, NONE), // NC
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RF_RST#
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ
PAD_NC(GPP_D7, NONE), // NC
PAD_NC(GPP_D8, NONE), // NC
PAD_NC(GPP_D9, NONE), // NC
PAD_NC(GPP_D10, NONE), // NC
PAD_NC(GPP_D11, NONE), // NC
PAD_NC(GPP_D12, NONE), // NC
PAD_NC(GPP_D13, NONE), // NC
PAD_NC(GPP_D14, NONE), // NC
PAD_NC(GPP_D15, NONE), // NC
PAD_NC(GPP_D16, NONE), // NC
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // NC
PAD_NC(GPP_D21, NONE), // NC
PAD_NC(GPP_D22, NONE), // NC
PAD_NC(GPP_D23, NONE), // NC
/* ------- GPIO Group E ------- */
PAD_CFG_GPI(GPP_E0, NONE, DEEP), // NC
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // SATAGP1
PAD_CFG_GPI(GPP_E2, NONE, DEEP), // NC
_PAD_CFG_STRUCT(GPP_E3, 0x44000101, 0x0000), // TODO: EXTTS_SNI_DRV0
PAD_CFG_GPI(GPP_E4, UP_20K, DEEP), // DEVSLP0
PAD_CFG_GPI(GPP_E5, UP_20K, DEEP), // DEVSLP1
PAD_NC(GPP_E6, NONE), // NC
_PAD_CFG_STRUCT(GPP_E7, 0x40800100, 0x3000), // TODO: TP_ATTN#
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
PAD_NC(GPP_E9, NONE), // NC
PAD_NC(GPP_E10, NONE), // NC
PAD_NC(GPP_E11, NONE), // NC
PAD_NC(GPP_E12, NONE), // NC
/* ------- GPIO Group F ------- */
PAD_NC(GPP_F0, NONE), // NC
PAD_NC(GPP_F1, NONE), // NC
PAD_NC(GPP_F2, NONE), // NC
PAD_NC(GPP_F3, NONE), // NC
PAD_NC(GPP_F4, NONE), // NC
PAD_CFG_GPI(GPP_F5, NONE, DEEP), // KBLED_DET
PAD_CFG_GPI(GPP_F6, NONE, DEEP), // LIGHT_KB_DET#
PAD_NC(GPP_F7, NONE), // NC
PAD_NC(GPP_F8, NONE), // NC
PAD_NC(GPP_F9, NONE), // NC
PAD_NC(GPP_F10, NONE), // BIOS_REC - strap for bios recovery enable
PAD_NC(GPP_F11, NONE), // PCH_RSVD - unused strap
PAD_NC(GPP_F12, NONE), // MFG_MODE - strap for manufacturing mode
PAD_NC(GPP_F13, NONE), // TODO: GP39_GFX_CRB_DETECT - 0 = normal gfx, 1 = customer gfx
PAD_CFG_GPI(GPP_F14, UP_20K, DEEP), // H_SKTOCC_N
PAD_NC(GPP_F15, NONE), // NC
PAD_NC(GPP_F16, NONE), // NC
PAD_NC(GPP_F17, NONE), // NC
PAD_NC(GPP_F18, NONE), // NC
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, PLTRST), // TODO: DGPU_RST#_PCH
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // TODO: DGPU_PWR_EN
/* ------- GPIO Group G ------- */
PAD_CFG_GPI(GPP_G0, NONE, DEEP), // BOARD_ID1
PAD_CFG_GPI(GPP_G1, NONE, DEEP), // BOARD_ID2
PAD_CFG_GPI(GPP_G2, NONE, DEEP), // TPM_DET
PAD_CFG_GPI(GPP_G3, UP_20K, DEEP), // TODO: GPIO4_1V8_MAIN_EN_R
PAD_NC(GPP_G4, NONE), // NC
PAD_NC(GPP_G5, NONE), // NC
PAD_NC(GPP_G6, NONE), // NC
PAD_NC(GPP_G7, NONE), // NC
/* ------- GPIO Group H ------- */
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
_PAD_CFG_STRUCT(GPP_H1, 0x84000300, 0x0000), // NC
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
_PAD_CFG_STRUCT(GPP_H3, 0x84000300, 0x0000), // NC
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD_CLKREQ#
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // SSD2_CLKREQ#
_PAD_CFG_STRUCT(GPP_H6, 0x84000300, 0x0000), // NC
_PAD_CFG_STRUCT(GPP_H7, 0x84000300, 0x0000), // NC
_PAD_CFG_STRUCT(GPP_H8, 0x84000300, 0x0000), // NC
_PAD_CFG_STRUCT(GPP_H9, 0x84000300, 0x0000), // NC
PAD_CFG_GPI(GPP_H10, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H11, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H12, NONE, DEEP), // GPP_H_12 - strap for ESPI flash sharing mode
PAD_CFG_GPI(GPP_H13, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H14, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H15, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H16, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H17, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H18, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H19, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H20, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H21, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H22, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H23, NONE, DEEP), // NC
/* ------- GPIO Group I ------- */
PAD_CFG_GPI(GPP_I0, NONE, DEEP), // NC
PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), // HDMI_HPD
PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // NC
_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000), // MDP_E_HPD
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HPD
PAD_CFG_GPI(GPP_I5, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I6, NONE, DEEP), // NC
PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), // HDMI_CTRLCLK
PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), // HDMI_CTRLDATA
PAD_CFG_GPI(GPP_I9, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I10, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I11, NONE, DEEP), // TODO: H_SKTOCC_N
PAD_CFG_GPI(GPP_I12, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I13, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I14, NONE, DEEP), // NC
/* ------- GPIO Group J ------- */
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), // NC
PAD_NC(GPP_J2, NONE), // NC
PAD_NC(GPP_J3, NONE), // NC
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
PAD_NC(GPP_J10, NONE), // NC
PAD_NC(GPP_J11, NONE), // NC
/* ------- GPIO Group K ------- */
PAD_NC(GPP_K0, NONE), // NC
PAD_NC(GPP_K1, NONE), // NC
PAD_NC(GPP_K2, NONE), // NC
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), // SCI#
PAD_NC(GPP_K4, NONE), // NC
PAD_NC(GPP_K5, NONE), // NC
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x3000), // SWI#
PAD_NC(GPP_K7, NONE), // NC
PAD_CFG_GPI(GPP_K8, NONE, DEEP), // SATA_M2_PWR_EN1
PAD_CFG_GPI(GPP_K9, NONE, DEEP), // SATA_M2_PWR_EN2
PAD_CFG_GPI(GPP_K10, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_K11, NONE, DEEP), // NC
PAD_NC(GPP_K12, NONE), // NC
PAD_NC(GPP_K13, NONE), // NC
PAD_NC(GPP_K14, NONE), // NC
PAD_NC(GPP_K15, NONE), // NC
PAD_NC(GPP_K16, NONE), // NC
PAD_NC(GPP_K17, NONE), // NC
PAD_NC(GPP_K18, NONE), // NC
_PAD_CFG_STRUCT(GPP_K19, 0x42000100, 0x3000), // SMI#
_PAD_CFG_STRUCT(GPP_K20, 0x44000101, 0x0000), // TODO: GPU_EVENT#
PAD_CFG_GPI(GPP_K21, NONE, DEEP), // TODO: GC6_FB_EN_PCH
_PAD_CFG_STRUCT(GPP_K22, 0x80000100, 0x0000), // TODO: DGPU_PWRGD_R
PAD_CFG_NF(GPP_K23, NONE, DEEP, NF1), // NC
};
#endif
#endif

38
src/mainboard/system76/gaze14/variants/gaze14_1650_17/hda_verb.c
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@@ -1,38 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef HDA_VERB_H
#define HDA_VERB_H
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek, ALC269VC */
0x10ec0269, /* Vendor ID */
0x15588561, /* Subsystem ID */
11, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x15588561),
AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
AZALIA_PIN_CFG(0, 0x15, 0x02211020),
AZALIA_PIN_CFG(0, 0x17, 0x40000000),
AZALIA_PIN_CFG(0, 0x18, 0x02a11030),
AZALIA_PIN_CFG(0, 0x19, 0x02a1103f),
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1d, 0x40f00001),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
/* Intel, KabylakeHDMI */
0x8086280b, /* Vendor ID */
0x80860101, /* Subsystem ID */
4, /* Number of entries */
AZALIA_SUBVENDOR(2, 0x80860101),
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
AZALIA_PIN_CFG(2, 0x07, 0x18560010),
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;
#endif

276
src/mainboard/system76/gaze14/variants/gaze14_1650_17/include/variant/gpio.h
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@@ -1,276 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
#include <soc/gpe.h>
#include <soc/gpio.h>
#ifndef __ACPI__
/* Early pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_NC(GPP_C22, NONE), // NC
PAD_NC(GPP_C23, NONE), // NC
};
/* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
PAD_CFG_GPI(GPD2, NATIVE, PWROK), // NC
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
_PAD_CFG_STRUCT(GPD6, 0x44000601, 0x0000), // NC
_PAD_CFG_STRUCT(GPD7, 0x04000300, 0x0000), // NC
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK_R
PAD_CFG_GPI(GPD9, NONE, PWROK), // NC
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // NC
PAD_CFG_TERM_GPO(GPD11, 0, NONE, PWROK), // NC
/* ------- GPIO Group A ------- */
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // NC
PAD_CFG_GPI(GPP_A11, NONE, DEEP), // TODO: LAN_WAKEUP#
PAD_CFG_GPI(GPP_A12, NONE, DEEP), // NC
PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1), // SUSWARN#
PAD_CFG_TERM_GPO(GPP_A14, 0, DN_20K, DEEP), // NC
PAD_CFG_GPI(GPP_A15, NONE, DEEP), // SUS_PWR_ACK
PAD_NC(GPP_A16, NONE), // NC
PAD_NC(GPP_A17, NONE), // NC
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), // SB_BLON
PAD_NC(GPP_A19, NONE), // NC
PAD_NC(GPP_A20, NONE), // NC
PAD_NC(GPP_A21, NONE), // NC
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP), // SATA_PWR_EN
PAD_NC(GPP_A23, NONE), // NC
/* ------- GPIO Group B ------- */
PAD_CFG_GPI(GPP_B0, NONE, DEEP), // TODO: TPM_PIRQ#
PAD_CFG_TERM_GPO(GPP_B1, 0, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_B2, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_B3, NONE, DEEP), // NC
PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP), // TODO: EXTTS_SNI_DRV1
PAD_CFG_GPI(GPP_B5, NONE, PLTRST), // NC
PAD_CFG_GPI(GPP_B6, NONE, PLTRST), // NC
PAD_CFG_GPI(GPP_B7, NONE, PLTRST), // NC
PAD_CFG_GPI(GPP_B8, NONE, PLTRST), // NC
PAD_CFG_GPI(GPP_B9, NONE, PLTRST), // NC
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // LAN_CLKREQ#
PAD_CFG_GPI(GPP_B11, UP_20K, DEEP), // TODO: GPP_B11: DDR Voltage select - 0 = 1.2V, 1 = 1.35V
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
PAD_NC(GPP_B15, NONE), // NC
PAD_CFG_GPI(GPP_B16, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_B17, NONE, DEEP), // NC
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), // LPSS_GSPI0_MOSI - strap for no reboot mode
PAD_NC(GPP_B19, NONE), // NC
PAD_NC(GPP_B20, NONE), // NC
PAD_NC(GPP_B21, NONE), // NC
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), // LPSS_GSPI1_MOSI - strap for booting from SPI or LPC
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), // PCH_HOT_GNSS_DISABLE - strap for DCI BSSB mode
/* ------- GPIO Group C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPI(GPP_C2, NONE, DEEP), // NC
PAD_NC(GPP_C3, NONE), // NC
PAD_NC(GPP_C4, NONE), // NC
PAD_CFG_GPI(GPP_C5, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_C6, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_C7, NONE, DEEP), // NC
PAD_NC(GPP_C8, NONE), // NC
PAD_CFG_TERM_GPO(GPP_C9, 1, NONE, DEEP), // TODO: CNVI_DET#
PAD_NC(GPP_C10, NONE), // NC
PAD_NC(GPP_C11, NONE), // NC
PAD_NC(GPP_C12, NONE), // NC
PAD_NC(GPP_C13, NONE), // NC
PAD_NC(GPP_C14, NONE), // NC
PAD_NC(GPP_C15, NONE), // NC
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SCL_TP
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SDA_TP
PAD_NC(GPP_C18, NONE), // NC
PAD_NC(GPP_C19, NONE), // NC
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), // NC
/* ------- GPIO Group D ------- */
PAD_NC(GPP_D0, NONE), // NC
PAD_NC(GPP_D1, NONE), // NC
PAD_NC(GPP_D2, NONE), // NC
PAD_NC(GPP_D3, NONE), // NC
PAD_NC(GPP_D4, NONE), // NC
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RF_RST#
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ
PAD_NC(GPP_D7, NONE), // NC
PAD_NC(GPP_D8, NONE), // NC
PAD_NC(GPP_D9, NONE), // NC
PAD_NC(GPP_D10, NONE), // NC
PAD_NC(GPP_D11, NONE), // NC
PAD_NC(GPP_D12, NONE), // NC
PAD_NC(GPP_D13, NONE), // NC
PAD_NC(GPP_D14, NONE), // NC
PAD_NC(GPP_D15, NONE), // NC
PAD_NC(GPP_D16, NONE), // NC
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // NC
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // NC
PAD_NC(GPP_D21, NONE), // NC
PAD_NC(GPP_D22, NONE), // NC
PAD_NC(GPP_D23, NONE), // NC
/* ------- GPIO Group E ------- */
PAD_CFG_GPI(GPP_E0, NONE, DEEP), // NC
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // SATAGP1
PAD_CFG_GPI(GPP_E2, NONE, DEEP), // NC
_PAD_CFG_STRUCT(GPP_E3, 0x44000101, 0x0000), // TODO: EXTTS_SNI_DRV0
PAD_CFG_GPI(GPP_E4, UP_20K, DEEP), // DEVSLP0
PAD_CFG_GPI(GPP_E5, UP_20K, DEEP), // DEVSLP1
PAD_NC(GPP_E6, NONE), // NC
_PAD_CFG_STRUCT(GPP_E7, 0x40800100, 0x3000), // TODO: TP_ATTN#
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
PAD_NC(GPP_E9, NONE), // NC
PAD_NC(GPP_E10, NONE), // NC
PAD_NC(GPP_E11, NONE), // NC
PAD_NC(GPP_E12, NONE), // NC
/* ------- GPIO Group F ------- */
PAD_NC(GPP_F0, NONE), // NC
PAD_NC(GPP_F1, NONE), // NC
PAD_NC(GPP_F2, NONE), // NC
PAD_NC(GPP_F3, NONE), // NC
PAD_NC(GPP_F4, NONE), // NC
PAD_CFG_GPI(GPP_F5, NONE, DEEP), // KBLED_DET
PAD_CFG_GPI(GPP_F6, NONE, DEEP), // LIGHT_KB_DET#
PAD_NC(GPP_F7, NONE), // NC
PAD_NC(GPP_F8, NONE), // NC
PAD_NC(GPP_F9, NONE), // NC
PAD_NC(GPP_F10, NONE), // BIOS_REC - strap for bios recovery enable
PAD_NC(GPP_F11, NONE), // PCH_RSVD - unused strap
PAD_NC(GPP_F12, NONE), // MFG_MODE - strap for manufacturing mode
PAD_NC(GPP_F13, NONE), // TODO: GP39_GFX_CRB_DETECT - 0 = normal gfx, 1 = customer gfx
PAD_CFG_GPI(GPP_F14, UP_20K, DEEP), // H_SKTOCC_N
PAD_NC(GPP_F15, NONE), // NC
PAD_NC(GPP_F16, NONE), // NC
PAD_NC(GPP_F17, NONE), // NC
PAD_NC(GPP_F18, NONE), // NC
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, PLTRST), // TODO: DGPU_RST#_PCH
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // TODO: DGPU_PWR_EN
/* ------- GPIO Group G ------- */
PAD_CFG_GPI(GPP_G0, NONE, DEEP), // BOARD_ID1
PAD_CFG_GPI(GPP_G1, NONE, DEEP), // BOARD_ID2
PAD_CFG_GPI(GPP_G2, NONE, DEEP), // TPM_DET
PAD_CFG_GPI(GPP_G3, UP_20K, DEEP), // TODO: GPIO4_1V8_MAIN_EN_R
PAD_NC(GPP_G4, NONE), // NC
PAD_NC(GPP_G5, NONE), // NC
PAD_NC(GPP_G6, NONE), // NC
PAD_NC(GPP_G7, NONE), // NC
/* ------- GPIO Group H ------- */
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
_PAD_CFG_STRUCT(GPP_H1, 0x84000300, 0x0000), // NC
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
_PAD_CFG_STRUCT(GPP_H3, 0x84000300, 0x0000), // NC
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD_CLKREQ#
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // SSD2_CLKREQ#
_PAD_CFG_STRUCT(GPP_H6, 0x84000300, 0x0000), // NC
_PAD_CFG_STRUCT(GPP_H7, 0x84000300, 0x0000), // NC
_PAD_CFG_STRUCT(GPP_H8, 0x84000300, 0x0000), // NC
_PAD_CFG_STRUCT(GPP_H9, 0x84000300, 0x0000), // NC
PAD_CFG_GPI(GPP_H10, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H11, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H12, NONE, DEEP), // GPP_H_12 - strap for ESPI flash sharing mode
PAD_CFG_GPI(GPP_H13, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H14, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H15, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H16, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H17, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H18, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H19, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H20, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H21, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H22, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_H23, NONE, DEEP), // NC
/* ------- GPIO Group I ------- */
PAD_CFG_GPI(GPP_I0, NONE, DEEP), // NC
PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), // HDMI_HPD
PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // NC
_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000), // MDP_E_HPD
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HPD
PAD_CFG_GPI(GPP_I5, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I6, NONE, DEEP), // NC
PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), // HDMI_CTRLCLK
PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), // HDMI_CTRLDATA
PAD_CFG_GPI(GPP_I9, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I10, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I11, NONE, DEEP), // TODO: H_SKTOCC_N
PAD_CFG_GPI(GPP_I12, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I13, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_I14, NONE, DEEP), // NC
/* ------- GPIO Group J ------- */
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), // NC
PAD_NC(GPP_J2, NONE), // NC
PAD_NC(GPP_J3, NONE), // NC
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
PAD_NC(GPP_J10, NONE), // NC
PAD_NC(GPP_J11, NONE), // NC
/* ------- GPIO Group K ------- */
PAD_NC(GPP_K0, NONE), // NC
PAD_NC(GPP_K1, NONE), // NC
PAD_NC(GPP_K2, NONE), // NC
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), // SCI#
PAD_NC(GPP_K4, NONE), // NC
PAD_NC(GPP_K5, NONE), // NC
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x3000), // SWI#
PAD_NC(GPP_K7, NONE), // NC
PAD_CFG_GPI(GPP_K8, NONE, DEEP), // SATA_M2_PWR_EN1
PAD_CFG_GPI(GPP_K9, NONE, DEEP), // SATA_M2_PWR_EN2
PAD_CFG_GPI(GPP_K10, NONE, DEEP), // NC
PAD_CFG_GPI(GPP_K11, NONE, DEEP), // NC
PAD_NC(GPP_K12, NONE), // NC
PAD_NC(GPP_K13, NONE), // NC
PAD_NC(GPP_K14, NONE), // NC
PAD_NC(GPP_K15, NONE), // NC
PAD_NC(GPP_K16, NONE), // NC
PAD_NC(GPP_K17, NONE), // NC
PAD_NC(GPP_K18, NONE), // NC
_PAD_CFG_STRUCT(GPP_K19, 0x42000100, 0x3000), // SMI#
_PAD_CFG_STRUCT(GPP_K20, 0x44000101, 0x0000), // TODO: GPU_EVENT#
PAD_CFG_GPI(GPP_K21, NONE, DEEP), // TODO: GC6_FB_EN_PCH
_PAD_CFG_STRUCT(GPP_K22, 0x80000100, 0x0000), // TODO: DGPU_PWRGD_R
PAD_CFG_NF(GPP_K23, NONE, DEEP, NF1), // NC
};
#endif
#endif

5
src/mainboard/system76/gaze14/variants/gaze14_1650_17/overridetree.cb
View File

@@ -1,5 +0,0 @@
chip soc/intel/cannonlake
device domain 0 on
subsystemid 0x1558 0x8561 inherit
end
end

BIN
src/mainboard/system76/gaze14/variants/gaze14_1660ti/data.vbt Normal file
View File

Binary file not shown.

5
src/mainboard/system76/gaze14/variants/gaze14_1660ti_15/hda_verb.c → src/mainboard/system76/gaze14/variants/gaze14_1660ti/hda_verb.c
View File

@@ -1,8 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef HDA_VERB_H
#define HDA_VERB_H
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
@@ -35,5 +32,3 @@ const u32 cim_verb_data[] = {
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;
#endif

272
src/mainboard/system76/gaze14/variants/gaze14_1660ti/include/variant/gpio.h Normal file
View File

@@ -0,0 +1,272 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
#include <soc/gpe.h>
#include <soc/gpio.h>
#ifndef __ACPI__
static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
};
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_NC(GPD0, NONE), // PM_BATLOW#
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP#
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
PAD_NC(GPD6, NONE), // SLP_A#
PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD_7 (crystal input)
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
PAD_NC(GPD9, NONE), // PCH_SLP_WLAN#
PAD_NC(GPD10, NONE),
PAD_NC(GPD11, NONE), // LAN_DISABLE_N
/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
PAD_CFG_GPI_APIC_HIGH(GPP_A7, NONE, PLTRST), // INTP_OUT
PAD_NC(GPP_A8, NONE), // PM_CLKRUN#
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC
PAD_NC(GPP_A10, NONE),
PAD_CFG_GPI(GPP_A11, NONE, DEEP), // LAN_WAKEUP#
PAD_NC(GPP_A12, NONE), // ISH_GP_6_R
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
PAD_NC(GPP_A14, NONE), // S4_STATE#
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), // SUS_PWR_ACK#
PAD_NC(GPP_A16, NONE),
PAD_NC(GPP_A17, NONE),
PAD_CFG_GPO(GPP_A18, 1, DEEP), // SB_BLON
PAD_NC(GPP_A19, NONE),
PAD_NC(GPP_A20, NONE),
PAD_NC(GPP_A21, NONE), // 3G_CONFIG2
PAD_CFG_GPO(GPP_A22, 0, DEEP), // SATA_PWR_EN
PAD_NC(GPP_A23, NONE), // DGPU_PWM_SELECT#
/* ------- GPIO Group GPP_B ------- */
PAD_CFG_GPI(GPP_B0, NONE, DEEP), // TPM_PIRQ#
PAD_NC(GPP_B1, NONE),
PAD_NC(GPP_B2, NONE), // VRALERTB#
PAD_NC(GPP_B3, NONE),
PAD_NC(GPP_B4, NONE), // EXTTS_SNI_DRV1
PAD_NC(GPP_B5, NONE),
PAD_NC(GPP_B6, NONE),
PAD_NC(GPP_B7, NONE),
PAD_NC(GPP_B8, NONE),
PAD_NC(GPP_B9, NONE),
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // LAN_CLKREQ#
PAD_NC(GPP_B11, NONE),
_PAD_CFG_STRUCT(GPP_B12, 0x44000601, 0x0000), // SLP_S0#
_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x1000), // PLT_RST#
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
PAD_NC(GPP_B15, NONE),
PAD_NC(GPP_B16, NONE),
PAD_NC(GPP_B17, NONE),
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), // NO REBOOT strap
PAD_NC(GPP_B19, NONE),
PAD_NC(GPP_B20, NONE),
PAD_NC(GPP_B21, NONE),
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), // LPC/SPI BOOT strap
PAD_CFG_GPI(GPP_B23, NONE, DEEP), // DCI BSSB mode strap
/* ------- GPIO Group GPP_C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPI(GPP_C2, NONE, DEEP), // SKIN_THRM_SNSR_ALERT_N
PAD_NC(GPP_C3, NONE), // SML0_CLK
PAD_NC(GPP_C4, NONE), // SML0_DATA
PAD_NC(GPP_C5, NONE),
PAD_NC(GPP_C6, NONE), // SMC_CPU_THERM
PAD_NC(GPP_C7, NONE), // SMD_CPU_THERM
PAD_NC(GPP_C8, NONE),
PAD_NC(GPP_C9, NONE),
PAD_NC(GPP_C10, NONE),
PAD_NC(GPP_C11, NONE),
PAD_NC(GPP_C12, NONE),
PAD_NC(GPP_C13, NONE),
PAD_NC(GPP_C14, NONE),
PAD_NC(GPP_C15, NONE),
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SDA_TP
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SCL_TP
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // SMD_7411
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // SMC_7411
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_NC(GPP_C22, NONE),
PAD_NC(GPP_C23, NONE),
/* ------- GPIO Group GPP_D ------- */
PAD_NC(GPP_D0, NONE),
PAD_NC(GPP_D1, NONE),
PAD_NC(GPP_D2, NONE),
PAD_NC(GPP_D3, NONE),
PAD_NC(GPP_D4, NONE),
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RF_RST#
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ
PAD_NC(GPP_D7, NONE),
PAD_NC(GPP_D8, NONE),
PAD_NC(GPP_D9, NONE),
PAD_NC(GPP_D10, NONE),
PAD_NC(GPP_D11, NONE),
PAD_NC(GPP_D12, NONE),
PAD_NC(GPP_D13, NONE),
PAD_NC(GPP_D14, NONE),
PAD_NC(GPP_D15, NONE),
PAD_NC(GPP_D16, NONE),
PAD_NC(GPP_D17, NONE),
PAD_NC(GPP_D18, NONE),
PAD_NC(GPP_D19, NONE),
PAD_NC(GPP_D20, NONE),
PAD_NC(GPP_D21, NONE),
PAD_NC(GPP_D22, NONE),
PAD_NC(GPP_D23, NONE),
/* ------- GPIO Group GPP_E ------- */
PAD_NC(GPP_E0, NONE), // SATAGP0
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1
PAD_NC(GPP_E2, NONE), // SATAGP2
PAD_NC(GPP_E3, NONE), // EXTTS_SNI_DRV0
PAD_CFG_GPI(GPP_E4, NONE, DEEP), // DEVSLP0
PAD_CFG_GPI(GPP_E5, NONE, DEEP), // DEVSLP1
PAD_NC(GPP_E6, NONE), // PCH_MUTE#
_PAD_CFG_STRUCT(GPP_E7, 0x80800100, 0x0000), // TP_ATTN#
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
PAD_NC(GPP_E9, NONE),
PAD_NC(GPP_E10, NONE),
PAD_NC(GPP_E11, NONE),
PAD_NC(GPP_E12, NONE),
/* ------- GPIO Group GPP_F ------- */
PAD_NC(GPP_F0, NONE), // SATAGP3
PAD_NC(GPP_F1, NONE),
PAD_NC(GPP_F2, NONE),
PAD_NC(GPP_F3, NONE),
PAD_NC(GPP_F4, NONE),
PAD_CFG_GPI(GPP_F5, NONE, DEEP), // KBLED_DET
PAD_CFG_GPI(GPP_F6, NONE, DEEP), // LIGHT_KB_DET#
PAD_NC(GPP_F7, NONE),
PAD_NC(GPP_F8, NONE),
PAD_NC(GPP_F9, NONE),
PAD_NC(GPP_F10, NONE), // BIOS_REC - BIOS RECOVERY ENABLE strap
PAD_NC(GPP_F11, NONE), // PCH_RSVD - unused strap
PAD_NC(GPP_F12, NONE), // MFG_MODE - Manufacturing mode strap
PAD_NC(GPP_F13, NONE), // GP39_GFX_CRB_DETECT - 0 = normal gfx, 1 = customer gfx
PAD_CFG_GPI(GPP_F14, NONE, DEEP), // H_SKTOCC_N
PAD_NC(GPP_F15, NONE),
PAD_NC(GPP_F16, NONE),
PAD_NC(GPP_F17, NONE),
PAD_NC(GPP_F18, NONE),
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH
PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN
/* ------- GPIO Group GPP_G ------- */
PAD_CFG_GPI(GPP_G0, NONE, DEEP), // BOARD_ID1
PAD_CFG_GPI(GPP_G1, NONE, DEEP), // BOARD_ID2
PAD_CFG_GPI(GPP_G2, NONE, DEEP), // TPM_DET
PAD_CFG_GPI(GPP_G3, UP_20K, DEEP), // TODO: GPIO4_1V8_MAIN_EN_R
PAD_NC(GPP_G4, NONE),
PAD_NC(GPP_G5, NONE),
PAD_NC(GPP_G6, NONE),
PAD_NC(GPP_G7, NONE),
/* ------- GPIO Group GPP_H ------- */
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
PAD_NC(GPP_H1, NONE),
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ
PAD_NC(GPP_H3, NONE),
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD_CLKREQ#
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // SSD2_CLKREQ#
PAD_NC(GPP_H6, NONE),
PAD_NC(GPP_H7, NONE),
PAD_NC(GPP_H8, NONE),
PAD_NC(GPP_H9, NONE),
PAD_NC(GPP_H10, NONE),
PAD_NC(GPP_H11, NONE),
PAD_CFG_GPI(GPP_H12, NONE, DEEP), // ESPI FLASH SHARING MODE strap
PAD_NC(GPP_H13, NONE),
PAD_NC(GPP_H14, NONE),
PAD_NC(GPP_H15, NONE),
PAD_NC(GPP_H16, NONE),
PAD_NC(GPP_H17, NONE),
PAD_NC(GPP_H18, NONE),
PAD_NC(GPP_H19, NONE),
PAD_NC(GPP_H20, NONE),
PAD_NC(GPP_H21, NONE),
PAD_NC(GPP_H22, NONE),
PAD_NC(GPP_H23, NONE), // DGPU_SELECT#
/* ------- GPIO Group GPP_I ------- */
PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), // I_MDP_HPD
_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000), // HDMI_HPD
PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000), // MDP_E_HPD
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HPD
PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), // I_MDP_CLK
PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), // I_MDP_DATA
PAD_NC(GPP_I7, NONE),
PAD_NC(GPP_I8, NONE),
PAD_NC(GPP_I9, NONE),
PAD_NC(GPP_I10, NONE),
PAD_CFG_GPI(GPP_I11, NONE, DEEP), // H_SKTOCC_N
PAD_NC(GPP_I12, NONE),
PAD_NC(GPP_I13, NONE),
PAD_NC(GPP_I14, NONE),
/* ------- GPIO Group GPP_J ------- */
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_NC(GPP_J1, NONE),
PAD_NC(GPP_J2, NONE),
PAD_NC(GPP_J3, NONE),
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
PAD_NC(GPP_J10, NONE),
PAD_NC(GPP_J11, NONE),
/* ------- GPIO Group GPP_K ------- */
PAD_NC(GPP_K0, NONE),
PAD_NC(GPP_K1, NONE),
PAD_NC(GPP_K2, NONE),
_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000), // SCI#
PAD_NC(GPP_K4, NONE),
PAD_NC(GPP_K5, NONE),
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#
PAD_NC(GPP_K7, NONE),
PAD_CFG_GPO(GPP_K8, 1, DEEP), // SATA_M2_PWR_EN1
PAD_CFG_GPO(GPP_K9, 1, DEEP), // SATA_M2_PWR_EN2
PAD_NC(GPP_K10, NONE),
PAD_NC(GPP_K11, NONE),
PAD_NC(GPP_K12, NONE),
PAD_NC(GPP_K13, NONE),
PAD_NC(GPP_K14, NONE), // GPP_K14_TEST_R
PAD_NC(GPP_K15, NONE),
PAD_NC(GPP_K16, NONE),
PAD_NC(GPP_K17, NONE),
PAD_NC(GPP_K18, NONE),
_PAD_CFG_STRUCT(GPP_K19, 0x42800101, 0x0000), // SMI#
PAD_CFG_GPI(GPP_K20, NONE, DEEP), // GPU_EVENT#
PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN_PCH
PAD_CFG_GPI(GPP_K22, NONE, DEEP), // DGPU_PWRGD_R
PAD_NC(GPP_K23, NONE), // DGPU_PRSNT#
};
#endif
#endif

0
src/mainboard/system76/gaze14/variants/gaze14_1660ti_15/overridetree.cb → src/mainboard/system76/gaze14/variants/gaze14_1660ti/overridetree.cb
View File

39
src/mainboard/system76/gaze14/variants/gaze14_1660ti_17/hda_verb.c
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@@ -1,39 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef HDA_VERB_H
#define HDA_VERB_H
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek, ALC293 */
0x10ec0293, /* Vendor ID */
0x15588551, /* Subsystem ID */
12, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x15588550),
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
AZALIA_PIN_CFG(0, 0x15, 0x02211020),
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
AZALIA_PIN_CFG(0, 0x18, 0x02a11040),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1d, 0x40738205),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
/* Intel, KabylakeHDMI */
0x8086280b, /* Vendor ID */
0x80860101, /* Subsystem ID */
4, /* Number of entries */
AZALIA_SUBVENDOR(2, 0x80860101),
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
AZALIA_PIN_CFG(2, 0x07, 0x18560010),
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;
#endif

5
src/mainboard/system76/gaze14/variants/gaze14_1660ti_17/overridetree.cb
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@@ -1,5 +0,0 @@
chip soc/intel/cannonlake
device domain 0 on
subsystemid 0x1558 0x8551 inherit
end
end