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soc/intel/broadwell: Get rid of device_t

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Use of device_t has been abandoned in ramstage.

Change-Id: I043f4169ad080f9a449c8780500332c9512b62ff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26583
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS
2018-05-27 16:30:36 +02:00
committed by Martin Roth
parent 4f41336fd8
commit 040aff2745
12 changed files with 68 additions and 65 deletions
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4
src/soc/intel/broadwell/acpi.c
View File

@ -387,7 +387,7 @@ static void generate_T_state_entries(int core, int cores_per_package)
static void generate_C_state_entries(void)
{
device_t dev = SA_DEV_ROOT;
struct device *dev = SA_DEV_ROOT;
config_t *config = dev->chip_info;
acpi_cstate_t map[3];
int *set;
@ -534,7 +534,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
acpigen_pop_len();
}
void generate_cpu_entries(device_t device)
void generate_cpu_entries(struct device *device)
{
int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6;
int totalcores = dev_count_cpu();

6
src/soc/intel/broadwell/chip.c
View File

@ -21,7 +21,7 @@
#include <soc/ramstage.h>
#include <soc/intel/broadwell/chip.h>
static void pci_domain_set_resources(device_t dev)
static void pci_domain_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
}
@ -42,7 +42,7 @@ static struct device_operations cpu_bus_ops = {
.init = &broadwell_init_cpus,
};
static void broadwell_enable(device_t dev)
static void broadwell_enable(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
@ -64,7 +64,7 @@ struct chip_operations soc_intel_broadwell_ops = {
.init = &broadwell_init_pre_device,
};
static void pci_set_subsystem(device_t dev, unsigned int vendor,
static void pci_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device)

8
src/soc/intel/broadwell/cpu.c
View File

@ -197,7 +197,7 @@ static int pcode_mailbox_write(u32 command, u32 data)
static void initialize_vr_config(void)
{
device_t dev = SA_DEV_ROOT;
struct device *dev = SA_DEV_ROOT;
config_t *conf = dev->chip_info;
msr_t msr;
@ -452,7 +452,7 @@ static void configure_c_states(void)
static void configure_thermal_target(void)
{
device_t dev = SA_DEV_ROOT;
struct device *dev = SA_DEV_ROOT;
config_t *conf = dev->chip_info;
msr_t msr;
@ -572,7 +572,7 @@ static void configure_mca(void)
}
/* All CPUs including BSP will run the following function. */
static void cpu_core_init(device_t cpu)
static void cpu_core_init(struct device *cpu)
{
/* Clear out pending MCEs */
configure_mca();
@ -672,7 +672,7 @@ static const struct mp_ops mp_ops = {
.post_mp_init = post_mp_init,
};
void broadwell_init_cpus(device_t dev)
void broadwell_init_cpus(struct device *dev)
{
struct bus *cpu_bus = dev->link_list;

2
src/soc/intel/broadwell/ehci.c
View File

@ -24,7 +24,7 @@
#include <soc/ehci.h>
#include <soc/pch.h>
static void usb_ehci_set_subsystem(device_t dev, unsigned int vendor,
static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
u8 access_cntl;

4
src/soc/intel/broadwell/include/soc/ramstage.h
View File

@ -20,8 +20,8 @@
#include <soc/intel/broadwell/chip.h>
void broadwell_init_pre_device(void *chip_info);
void broadwell_init_cpus(device_t dev);
void broadwell_pch_enable_dev(device_t dev);
void broadwell_init_cpus(struct device *dev);
void broadwell_pch_enable_dev(struct device *dev);
#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB)
void broadwell_run_reference_code(void);

24
src/soc/intel/broadwell/lpc.c
View File

@ -102,9 +102,9 @@ static void enable_hpet(struct device *dev)
* 0x80 - The PIRQ is not routed.
*/
static void pch_pirq_init(device_t dev)
static void pch_pirq_init(struct device *dev)
{
device_t irq_dev;
struct device *irq_dev;
config_t *config = dev->chip_info;
pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
@ -147,7 +147,7 @@ static void pch_pirq_init(device_t dev)
}
}
static void pch_power_options(device_t dev)
static void pch_power_options(struct device *dev)
{
u16 reg16;
const char *state;
@ -362,7 +362,7 @@ static void pch_pm_init(struct device *dev)
}
static void pch_cg_init(device_t dev)
static void pch_cg_init(struct device *dev)
{
u32 reg32;
u16 reg16;
@ -460,7 +460,7 @@ static void lpc_init(struct device *dev)
pch_set_acpi_mode();
}
static void pch_lpc_add_mmio_resources(device_t dev)
static void pch_lpc_add_mmio_resources(struct device *dev)
{
u32 reg;
struct resource *res;
@ -522,7 +522,8 @@ static inline int pch_io_range_in_default(u16 base, u16 size)
* Note: this function assumes there is no overlap with the default LPC device's
* claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
*/
static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index)
static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size,
int index)
{
struct resource *res;
@ -535,7 +536,8 @@ static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index)
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index)
static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value,
int index)
{
/*
* Check if the register is enabled. If so and the base exceeds the
@ -548,7 +550,7 @@ static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index)
}
}
static void pch_lpc_add_io_resources(device_t dev)
static void pch_lpc_add_io_resources(struct device *dev)
{
struct resource *res;
config_t *config = dev->chip_info;
@ -573,7 +575,7 @@ static void pch_lpc_add_io_resources(device_t dev)
pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC);
}
static void pch_lpc_read_resources(device_t dev)
static void pch_lpc_read_resources(struct device *dev)
{
global_nvs_t *gnvs;
@ -592,7 +594,7 @@ static void pch_lpc_read_resources(device_t dev)
memset(gnvs, 0, sizeof(global_nvs_t));
}
static void southcluster_inject_dsdt(device_t device)
static void southcluster_inject_dsdt(struct device *device)
{
global_nvs_t *gnvs;
@ -616,7 +618,7 @@ static void southcluster_inject_dsdt(device_t device)
}
}
static unsigned long broadwell_write_acpi_tables(device_t device,
static unsigned long broadwell_write_acpi_tables(struct device *device,
unsigned long current,
struct acpi_rsdp *rsdp)
{

20
src/soc/intel/broadwell/me.c
View File

@ -110,7 +110,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
mei_dump(ptr, dword, offset, "WRITE");
}
static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
{
u32 dword = pci_read_config32(dev, offset);
memcpy(ptr, &dword, sizeof(dword));
@ -433,7 +433,7 @@ static inline int mei_sendrecv_icc(struct icc_header *icc,
* mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read
* state machine on the BIOS end doesn't match the ME's state machine.
*/
static void intel_me_mbp_give_up(device_t dev)
static void intel_me_mbp_give_up(struct device *dev)
{
struct mei_csr csr;
@ -449,7 +449,7 @@ static void intel_me_mbp_give_up(device_t dev)
* mbp clear routine. This will wait for the ME to indicate that
* the MBP has been read and cleared.
*/
static void intel_me_mbp_clear(device_t dev)
static void intel_me_mbp_clear(struct device *dev)
{
int count;
struct me_hfs2 hfs2;
@ -611,7 +611,7 @@ static int mkhi_hmrfpo_lock_noack(void)
return 0;
}
static void intel_me_finalize(device_t dev)
static void intel_me_finalize(struct device *dev)
{
u32 reg32;
@ -653,7 +653,7 @@ static int me_icc_set_clock_enables(u32 mask)
}
/* Determine the path that we should take based on ME status */
static me_bios_path intel_me_path(device_t dev)
static me_bios_path intel_me_path(struct device *dev)
{
me_bios_path path = ME_DISABLE_BIOS_PATH;
struct me_hfs hfs;
@ -723,7 +723,7 @@ static me_bios_path intel_me_path(device_t dev)
}
/* Prepare ME for MEI messages */
static int intel_mei_setup(device_t dev)
static int intel_mei_setup(struct device *dev)
{
struct resource *res;
struct mei_csr host;
@ -753,7 +753,7 @@ static int intel_mei_setup(device_t dev)
}
/* Read the Extend register hash of ME firmware */
static int intel_me_extend_valid(device_t dev)
static int intel_me_extend_valid(struct device *dev)
{
struct me_heres status;
u32 extend[8] = {0};
@ -839,7 +839,7 @@ struct mbp_payload {
* Return 0 to indicate success (send LOCK+EOP)
* Return 1 to indicate success (send LOCK+EOP with NOACK)
*/
static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)
static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
{
mbp_header mbp_hdr;
u32 me2host_pending;
@ -968,7 +968,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)
}
/* Check whether ME is present and do basic init */
static void intel_me_init(device_t dev)
static void intel_me_init(struct device *dev)
{
config_t *config = dev->chip_info;
me_bios_path path = intel_me_path(dev);
@ -1045,7 +1045,7 @@ static void intel_me_init(device_t dev)
}
}
static void intel_me_enable(device_t dev)
static void intel_me_enable(struct device *dev)
{
/* Avoid talking to the device in S3 path */
if (acpi_is_wakeup_s3()) {

28
src/soc/intel/broadwell/pcie.c
View File

@ -48,23 +48,23 @@ struct root_port_config {
int coalesce;
int gbe_port;
int num_ports;
device_t ports[NUM_ROOT_PORTS];
struct device *ports[NUM_ROOT_PORTS];
};
static struct root_port_config rpc;
static inline int root_port_is_first(device_t dev)
static inline int root_port_is_first(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn) == 0;
}
static inline int root_port_is_last(device_t dev)
static inline int root_port_is_last(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1);
}
/* Root ports are numbered 1..N in the documentation. */
static inline int root_port_number(device_t dev)
static inline int root_port_number(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn) + 1;
}
@ -94,7 +94,7 @@ static void root_port_config_update_gbe_port(void)
}
}
static void pcie_iosf_port_grant_count(device_t dev)
static void pcie_iosf_port_grant_count(struct device *dev)
{
u8 update_val;
u32 rpcd = (pci_read_config32(dev, 0xfc) >> 14) & 0x3;
@ -115,7 +115,7 @@ static void pcie_iosf_port_grant_count(device_t dev)
RCBA32(0x103C) = (RCBA32(0x103C) & (~0xff)) | update_val;
}
static void root_port_init_config(device_t dev)
static void root_port_init_config(struct device *dev)
{
int rp;
u32 data = 0;
@ -186,7 +186,7 @@ static void root_port_init_config(device_t dev)
/* Update devicetree with new Root Port function number assignment */
static void pch_pcie_device_set_func(int index, int pci_func)
{
device_t dev;
struct device *dev;
unsigned int new_devfn;
dev = rpc.ports[index];
@ -216,7 +216,7 @@ static void pcie_enable_clock_gating(void)
int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
for (i = 0; i < rpc.num_ports; i++) {
device_t dev;
struct device *dev;
int rp;
dev = rpc.ports[i];
@ -294,7 +294,7 @@ static void root_port_commit_config(void)
pcie_enable_clock_gating();
for (i = 0; i < rpc.num_ports; i++) {
device_t dev;
struct device *dev;
u32 reg32;
int n = 0;
@ -359,7 +359,7 @@ static void root_port_commit_config(void)
RCBA32(RPFN) = rpc.new_rpfn;
}
static void root_port_mark_disable(device_t dev)
static void root_port_mark_disable(struct device *dev)
{
/* Mark device as disabled. */
dev->enabled = 0;
@ -367,7 +367,7 @@ static void root_port_mark_disable(device_t dev)
rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));
}
static void root_port_check_disable(device_t dev)
static void root_port_check_disable(struct device *dev)
{
int rp;
@ -629,7 +629,7 @@ static void pch_pcie_init(struct device *dev)
pci_write_config16(dev, 0x1e, reg16);
}
static void pch_pcie_enable(device_t dev)
static void pch_pcie_enable(struct device *dev)
{
/* Add this device to the root port config structure. */
root_port_init_config(dev);
@ -649,7 +649,7 @@ static void pch_pcie_enable(device_t dev)
root_port_commit_config();
}
static void pcie_set_subsystem(device_t dev, unsigned int vendor,
static void pcie_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
/* NOTE: This is not the default position! */
@ -659,7 +659,7 @@ static void pcie_set_subsystem(device_t dev, unsigned int vendor,
pci_write_config32(dev, 0x94, (device << 16) | vendor);
}
static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off)
static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off)
{
/* Set max snoop and non-snoop latency for Broadwell */
pci_write_config32(dev, off, 0x10031003);

2
src/soc/intel/broadwell/sata.c
View File

@ -267,7 +267,7 @@ static void sata_init(struct device *dev)
* Set SATA controller mode early so the resource allocator can
* properly assign IO/Memory resources for the controller.
*/
static void sata_enable(device_t dev)
static void sata_enable(struct device *dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;

8
src/soc/intel/broadwell/smbus.c
View File

@ -27,7 +27,7 @@
#include <soc/ramstage.h>
#include <soc/smbus.h>
static void pch_smbus_init(device_t dev)
static void pch_smbus_init(struct device *dev)
{
struct resource *res;
u16 reg16;
@ -43,7 +43,7 @@ static void pch_smbus_init(device_t dev)
outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
}
static int lsmbus_read_byte(device_t dev, u8 address)
static int lsmbus_read_byte(struct device *dev, u8 address)
{
u16 device;
struct resource *res;
@ -56,7 +56,7 @@ static int lsmbus_read_byte(device_t dev, u8 address)
return do_smbus_read_byte(res->base, device, address);
}
static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
static int lsmbus_write_byte(struct device *dev, u8 address, u8 data)
{
u16 device;
struct resource *res;
@ -73,7 +73,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
.write_byte = lsmbus_write_byte,
};
static void smbus_read_resources(device_t dev)
static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
res->base = SMBUS_BASE_ADDRESS;

6
src/soc/intel/broadwell/smmrelocate.c
View File

@ -179,7 +179,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
}
}
static u32 northbridge_get_base_reg(device_t dev, int reg)
static u32 northbridge_get_base_reg(struct device *dev, int reg)
{
u32 value;
@ -189,7 +189,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg)
return value;
}
static void fill_in_relocation_params(device_t dev,
static void fill_in_relocation_params(struct device *dev,
struct smm_relocation_params *params)
{
u32 tseg_size;
@ -270,7 +270,7 @@ static void setup_ied_area(struct smm_relocation_params *params)
void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
size_t *smm_save_state_size)
{
device_t dev = SA_DEV_ROOT;
struct device *dev = SA_DEV_ROOT;
printk(BIOS_DEBUG, "Setting up SMI for CPU\n");

21
src/soc/intel/broadwell/systemagent.c
View File

@ -37,7 +37,8 @@ u8 systemagent_revision(void)
return pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);
}
static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
u32 *len)
{
u32 pciexbar_reg;
@ -70,7 +71,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
return 0;
}
static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
{
u32 bar;
@ -89,7 +90,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
/* There are special BARs that actually are programmed in the MCHBAR. These
* Intel special features, but they do consume resources that need to be
* accounted for. */
static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base,
static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base,
u32 *len)
{
u32 bar;
@ -109,7 +110,7 @@ static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base,
struct fixed_mmio_descriptor {
unsigned int index;
u32 size;
int (*get_resource)(device_t dev, unsigned int index,
int (*get_resource)(struct device *dev, unsigned int index,
u32 *base, u32 *size);
const char *description;
};
@ -127,7 +128,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = {
* Add all known fixed MMIO ranges that hang off the host bridge/memory
* controller device.
*/
static void mc_add_fixed_mmio_resources(device_t dev)
static void mc_add_fixed_mmio_resources(struct device *dev)
{
int i;
@ -184,7 +185,7 @@ struct map_entry {
const char *description;
};
static void read_map_entry(device_t dev, struct map_entry *entry,
static void read_map_entry(struct device *dev, struct map_entry *entry,
uint64_t *result)
{
uint64_t value;
@ -253,14 +254,14 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
[TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"),
};
static void mc_read_map_entries(device_t dev, uint64_t *values)
static void mc_read_map_entries(struct device *dev, uint64_t *values)
{
int i;
for (i = 0; i < NUM_MAP_ENTRIES; i++)
read_map_entry(dev, &memory_map[i], &values[i]);
}
static void mc_report_map_entries(device_t dev, uint64_t *values)
static void mc_report_map_entries(struct device *dev, uint64_t *values)
{
int i;
for (i = 0; i < NUM_MAP_ENTRIES; i++) {
@ -271,7 +272,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values)
printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
}
static void mc_add_dram_resources(device_t dev, int *resource_cnt)
static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
{
unsigned long base_k, size_k;
unsigned long touud_k;
@ -377,7 +378,7 @@ static void mc_add_dram_resources(device_t dev, int *resource_cnt)
*resource_cnt = index;
}
static void systemagent_read_resources(device_t dev)
static void systemagent_read_resources(struct device *dev)
{
int index = 0;
const bool vtd_capable =