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sio1007: Properly build '.c' files

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Properly build the super i/o .c files.  This prevents including
the .c file directly in romstage, which is generally bad practice.
Adding a Makefile and a .h file to include.

Change-Id: I0be66e94d3062a2c4a445cee2f12ec249598dc8b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4014
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Marc Jones
2013-10-30 16:18:07 -06:00
committed by Kyösti Mälkki
parent c4b6f3bacb
commit 04134a52b2
4 changed files with 53 additions and 8 deletions
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2
src/mainboard/intel/emeraldlake2/romstage.c
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@@ -29,7 +29,7 @@
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <cbmem.h> #include <cbmem.h>
#include <console/console.h> #include <console/console.h>
#include "superio/smsc/sio1007/early_serial.c" #include "superio/smsc/sio1007/chip.h"
#include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/sandybridge.h"
#include "northbridge/intel/sandybridge/raminit.h" #include "northbridge/intel/sandybridge/raminit.h"
#include "southbridge/intel/bd82x6x/pch.h" #include "southbridge/intel/bd82x6x/pch.h"

21
src/superio/smsc/sio1007/Makefile.inc Normal file
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@@ -0,0 +1,21 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2013 Sage Electronic Engineering LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
romstage-$(CONFIG_SUPERIO_SMSC_SIO1007) += early_serial.c

26
src/superio/smsc/sio1007/chip.h Normal file
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@@ -0,0 +1,26 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef SUPERIO_SMSC_1007_CHIP_H
#define SUPERIO_SMSC_1007_CHIP_H
void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask);
int sio1007_enable_uart_at(u16 port);
#endif

12
src/superio/smsc/sio1007/early_serial.c
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@@ -17,13 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
/* #include <stdint.h>
* The chip could be bootstrap mapped to one of four LPC addresses: #include <arch/io.h>
* 0x2e, 0x4e, 0x162e, and 0x164e. #include "chip.h"
*/
const u16 sio1007_lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e};
static void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask) void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask)
{ {
u8 reg_value; u8 reg_value;
@@ -34,7 +32,7 @@ static void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask)
outb(reg_value, lpc_port + 1); outb(reg_value, lpc_port + 1);
} }
static int sio1007_enable_uart_at(u16 port) int sio1007_enable_uart_at(u16 port)
{ {
/* Enable config mode. */ /* Enable config mode. */
outb(0x55, port); outb(0x55, port);