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Use broadcast SIPI to startup siblings

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The current code for initializing AP cpus has several shortcomings:

- it assumes APIC IDs are sequential
- it uses only the BSP for determining the AP count, which is bad if
  there's more than one physical CPU, and CPUs are of different type

Note that the new code call cpu->ops->init() in parallel, and therefore
some CPU code needs to be changed to address that. One example are old
Intel HT enabled CPUs which can't do microcode update in parallel.

Change-Id: Ic48a1ebab6a7c52aa76765f497268af09fa38c25
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1139
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Sven Schnelle
2012-06-17 10:32:55 +02:00
committed by Ronald G. Minnich
parent 9ed1456eff
commit 042c1461fb
25 changed files with 143 additions and 519 deletions
Download Patch File Download Diff File Expand all files Collapse all files

65
src/cpu/intel/hyperthreading/intel_sibling.c
View File

@@ -7,13 +7,6 @@
#include <smp/spinlock.h>
#include <assert.h>
#if !CONFIG_SERIAL_CPU_INIT
#error Intel hyper-threading requires serialized cpu init
#endif
static int first_time = 1;
static int disable_siblings = !CONFIG_LOGICAL_CPUS;
/* Return true if running thread does not have the smallest lapic ID
* within a CPU core.
*/
@@ -34,61 +27,3 @@ int intel_ht_sibling(void)
threads = (apic_ids / core_ids);
return !!(lapicid() & (threads-1));
}
void intel_sibling_init(device_t cpu)
{
unsigned i, siblings;
struct cpuid_result result;
/* On the bootstrap processor see if I want sibling cpus enabled */
if (first_time) {
first_time = 0;
get_option(&disable_siblings, "hyper_threading");
}
result = cpuid(1);
/* Is hyperthreading supported */
if (!(result.edx & (1 << 28))) {
return;
}
/* See how many sibling cpus we have */
siblings = (result.ebx >> 16) & 0xff;
if (siblings < 1) {
siblings = 1;
}
printk(BIOS_DEBUG, "CPU: %u %d siblings\n",
cpu->path.apic.apic_id,
siblings);
/* See if I am a sibling cpu */
if (cpu->path.apic.apic_id & (siblings -1)) {
if (disable_siblings) {
cpu->enabled = 0;
}
return;
}
/* I am the primary cpu start up my siblings */
for(i = 1; i < siblings; i++) {
struct device_path cpu_path;
device_t new;
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id = cpu->path.apic.apic_id + i;
/* Allocate new cpu device structure iff sibling CPU
* was not in static device tree.
*/
new = alloc_find_dev(cpu->bus, &cpu_path);
if (!new) {
continue;
}
printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
cpu->path.apic.apic_id,
new->path.apic.apic_id);
}
}

4
src/cpu/intel/model_1067x/model_1067x_init.c
View File

@@ -29,7 +29,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
@@ -221,9 +220,6 @@ static void model_1067x_init(device_t cpu)
/* PIC thermal sensor control */
configure_pic_thermal_sensors();
/* Start up my cpu siblings */
intel_sibling_init(cpu);
}
static struct device_operations cpu_dev_ops = {

1
src/cpu/intel/model_106cx/Kconfig
View File

@@ -3,4 +3,3 @@ config CPU_INTEL_MODEL_106CX
select SMP
select SSE2
select UDELAY_LAPIC
select AP_IN_SIPI_WAIT

4
src/cpu/intel/model_106cx/model_106cx_init.c
View File

@@ -27,7 +27,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <usbdebug.h>
@@ -178,9 +177,6 @@ static void model_106cx_init(device_t cpu)
configure_misc();
/* TODO: PIC thermal sensor control */
/* Start up my cpu siblings */
intel_sibling_init(cpu);
}
static struct device_operations cpu_dev_ops = {

1
src/cpu/intel/model_206ax/Kconfig
View File

@@ -12,7 +12,6 @@ config CPU_SPECIFIC_OPTIONS
select SSE2
select UDELAY_LAPIC
select SMM_TSEG
#select AP_IN_SIPI_WAIT
config BOOTBLOCK_CPU_INIT
string

9
src/cpu/intel/model_206ax/acpi.c
View File

@@ -26,6 +26,7 @@
#include <arch/acpigen.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/acpi.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/turbo.h>
@@ -88,8 +89,8 @@ static int generate_cstate_entries(acpi_cstate_t *cstates,
static int generate_C_state_entries(void)
{
struct cpu_info *info;
struct cpu_driver *cpu;
struct device *cpu_dev;
int len, lenif;
device_t lapic;
struct cpu_intel_model_206ax_config *conf = NULL;
@@ -103,10 +104,10 @@ static int generate_C_state_entries(void)
return 0;
/* Find CPU map of supported C-states */
info = cpu_info();
if (!info)
cpu_dev = dev_find_lapic(lapicid());
if (!cpu_dev)
return 0;
cpu = find_cpu_driver(info->cpu);
cpu = find_cpu_driver(cpu_dev);
if (!cpu || !cpu->cstates)
return 0;

55
src/cpu/intel/model_206ax/model_206ax_init.c
View File

@@ -414,58 +414,6 @@ static void configure_mca(void)
static unsigned ehci_debug_addr;
#endif
/*
* Initialize any extra cores/threads in this package.
*/
static void intel_cores_init(device_t cpu)
{
struct cpuid_result result;
unsigned cores, threads, i;
result = cpuid_ext(0xb, 0); /* Threads per core */
threads = result.ebx & 0xff;
result = cpuid_ext(0xb, 1); /* Cores per package */
cores = result.ebx & 0xff;
/* Only initialize extra cores from BSP */
if (cpu->path.apic.apic_id)
return;
printk(BIOS_DEBUG, "CPU: %u has %u cores %u threads\n",
cpu->path.apic.apic_id, cores, threads);
for (i = 1; i < cores; ++i) {
struct device_path cpu_path;
device_t new;
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id =
cpu->path.apic.apic_id + i;
/* Update APIC ID if no hyperthreading */
if (threads == 1)
cpu_path.apic.apic_id <<= 1;
/* Allocate the new cpu device structure */
new = alloc_dev(cpu->bus, &cpu_path);
if (!new)
continue;
printk(BIOS_DEBUG, "CPU: %u has core %u\n",
cpu->path.apic.apic_id,
new->path.apic.apic_id);
/* Start the new cpu */
if (!start_cpu(new)) {
/* Record the error in cpu? */
printk(BIOS_ERR, "CPU %u would not start!\n",
new->path.apic.apic_id);
}
}
}
static void model_206ax_init(device_t cpu)
{
char processor_name[49];
@@ -528,9 +476,6 @@ static void model_206ax_init(device_t cpu)
/* Enable Turbo */
enable_turbo();
/* Start up extra cores */
intel_cores_init(cpu);
}
static struct device_operations cpu_dev_ops = {

1
src/cpu/intel/model_6ex/Kconfig
View File

@@ -3,4 +3,3 @@ config CPU_INTEL_MODEL_6EX
select SMP
select SSE2
select UDELAY_LAPIC
select AP_IN_SIPI_WAIT

3
src/cpu/intel/model_6ex/model_6ex_init.c
View File

@@ -205,9 +205,6 @@ static void model_6ex_init(device_t cpu)
/* PIC thermal sensor control */
configure_pic_thermal_sensors();
/* Start up my cpu siblings */
intel_sibling_init(cpu);
}
static struct device_operations cpu_dev_ops = {

1
src/cpu/intel/model_6fx/Kconfig
View File

@@ -3,4 +3,3 @@ config CPU_INTEL_MODEL_6FX
select SMP
select SSE2
select UDELAY_LAPIC
select AP_IN_SIPI_WAIT

3
src/cpu/intel/model_6fx/model_6fx_init.c
View File

@@ -243,9 +243,6 @@ static void model_6fx_init(device_t cpu)
/* PIC thermal sensor control */
configure_pic_thermal_sensors();
/* Start up my cpu siblings */
intel_sibling_init(cpu);
}
static struct device_operations cpu_dev_ops = {

3
src/cpu/intel/model_f2x/model_f2x_init.c
View File

@@ -60,9 +60,6 @@ static void model_f2x_init(device_t cpu)
/* Enable the local cpu apics */
setup_lapic();
/* Start up my cpu siblings */
intel_sibling_init(cpu);
};
static struct device_operations cpu_dev_ops = {

3
src/cpu/intel/model_f3x/model_f3x_init.c
View File

@@ -43,9 +43,6 @@ static void model_f3x_init(device_t cpu)
/* Enable the local cpu apics */
setup_lapic();
/* Start up my cpu siblings */
intel_sibling_init(cpu);
};
static struct device_operations cpu_dev_ops = {

3
src/cpu/intel/model_f4x/model_f4x_init.c
View File

@@ -51,9 +51,6 @@ static void model_f4x_init(device_t cpu)
/* Enable the local cpu apics */
setup_lapic();
/* Start up my cpu siblings */
intel_sibling_init(cpu);
};
static struct device_operations cpu_dev_ops = {

1
src/cpu/intel/socket_LGA771/Kconfig
View File

@@ -3,4 +3,3 @@ config CPU_INTEL_SOCKET_LGA771
select CPU_INTEL_MODEL_6FX
select SSE2
select MMX
select AP_IN_SIPI_WAIT