From 04705bfc26f06881d608bea46b01397018bf904b Mon Sep 17 00:00:00 2001
From: Mario Scheithauer <mario.scheithauer@siemens.com>
Date: Wed, 10 May 2023 14:30:29 +0200
Subject: [PATCH] mb/siemens/mc_ehl4: Double payload size to 256 bytes for PCIe
 RP #2, #3

To improve the rate of data transfer for PCIe root port #2 (00:1c.1) and
root port #3 (00:1c.2) set the max payload size to 256 bytes for both
root ports.

Change-Id: I553f6cf090d799fbbaafb925646c6566d6951a86
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75127
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
---
 src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb
index 56cfc3bc03..e99dd48f06 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb
@@ -78,6 +78,9 @@ chip soc/intel/elkhartlake
 	register "PcieRpPcieSpeed[3]" = "1"
 	register "PcieRpPcieSpeed[4]" = "1"
 
+	register "PcieRpMaxPayload[1]" = "RpMaxPayload_256"
+	register "PcieRpMaxPayload[2]" = "RpMaxPayload_256"
+
 	# Storage (SATA/SDCARD/EMMC) related UPDs
 	register "SataSalpSupport" = "0"
 	register "SataPortsEnable[0]" = "1"